arch/alpha/kernel/sys_sio.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_sio.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code for all boards that route the PCI interrupts through the SIO
   9  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  10  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/screen_info.h>
  20
  21 #include <asm/compiler.h>
  22 #include <asm/ptrace.h>
  23 #include <asm/system.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31 #include <asm/tlbflush.h>
  32
  33 #include "proto.h"
  34 #include "irq_impl.h"
  35 #include "pci_impl.h"
  36 #include "machvec_impl.h"
  37
  38 #if defined(ALPHA_RESTORE_SRM_SETUP)
  39 /* Save LCA configuration data as the console had it set up.  */
  40 struct
  41 {
  42         unsigned int orig_route_tab; /* for SAVE/RESTORE */
  43 } saved_config __attribute((common));
  44 #endif
  45
  46
  47 static void __init
  48 sio_init_irq(void)
  49 {
  50         if (alpha_using_srm)
  51                 alpha_mv.device_interrupt = srm_device_interrupt;
  52
  53         init_i8259a_irqs();
  54         common_init_isa_dma();
  55 }
  56
  57 static inline void __init
  58 alphabook1_init_arch(void)
  59 {
  60         /* The AlphaBook1 has LCD video fixed at 800x600,
  61            37 rows and 100 cols. */
  62         screen_info.orig_y = 37;
  63         screen_info.orig_video_cols = 100;
  64         screen_info.orig_video_lines = 37;
  65
  66         lca_init_arch();
  67 }
  68
  69
  70 /*
  71  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
  72  *              PIRQ0 -> irq 15
  73  *              PIRQ1 -> irq  9
  74  *              PIRQ2 -> irq 10
  75  *              PIRQ3 -> irq 11
  76  *
  77  * This probably ought to be configurable via MILO.  For
  78  * example, sound boards seem to like using IRQ 9.
  79  *
  80  * This is NOT how we should do it. PIRQ0-X should have
  81  * their own IRQs, the way intel uses the IO-APIC IRQs.
  82  */
  83
  84 static void __init
  85 sio_pci_route(void)
  86 {
  87         unsigned int orig_route_tab;
  88
  89         /* First, ALWAYS read and print the original setting. */
  90         pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
  91                                   &orig_route_tab);
  92         printk("%s: PIRQ original 0x%x new 0x%x\n", __FUNCTION__,
  93                orig_route_tab, alpha_mv.sys.sio.route_tab);
  94
  95 #if defined(ALPHA_RESTORE_SRM_SETUP)
  96         saved_config.orig_route_tab = orig_route_tab;
  97 #endif
  98
  99         /* Now override with desired setting. */
 100         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 101                                    alpha_mv.sys.sio.route_tab);
 102 }
 103
 104 static unsigned int __init
 105 sio_collect_irq_levels(void)
 106 {
 107         unsigned int level_bits = 0;
 108         struct pci_dev *dev = NULL;
 109
 110         /* Iterate through the devices, collecting IRQ levels.  */
 111         for_each_pci_dev(dev) {
 112                 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 113                     (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 114                         continue;
 115
 116                 if (dev->irq)
 117                         level_bits |= (1 << dev->irq);
 118         }
 119         return level_bits;
 120 }
 121
 122 static void __init
 123 sio_fixup_irq_levels(unsigned int level_bits)
 124 {
 125         unsigned int old_level_bits;
 126
 127         /*
 128          * Now, make all PCI interrupts level sensitive.  Notice:
 129          * these registers must be accessed byte-wise.  inw()/outw()
 130          * don't work.
 131          *
 132          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 133          *  so that the only bits getting set are for devices actually found.
 134          * Note that we do preserve the remainder of the bits, which we hope
 135          *  will be set correctly by ARC/SRM.
 136          *
 137          * Note: we at least preserve any level-set bits on AlphaBook1
 138          */
 139         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 140
 141         level_bits |= (old_level_bits & 0x71ff);
 142
 143         outb((level_bits >> 0) & 0xff, 0x4d0);
 144         outb((level_bits >> 8) & 0xff, 0x4d1);
 145 }
 146
 147 static inline int __init
 148 noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 149 {
 150         /*
 151          * The Noname board has 5 PCI slots with each of the 4
 152          * interrupt pins routed to different pins on the PCI/ISA
 153          * bridge (PIRQ0-PIRQ3).  The table below is based on
 154          * information available at:
 155          *
 156          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 157          *
 158          * I have no information on the Avanti interrupt routing, but
 159          * the routing seems to be identical to the Noname except
 160          * that the Avanti has an additional slot whose routing I'm
 161          * unsure of.
 162          *
 163          * pirq_tab[0] is a fake entry to deal with old PCI boards
 164          * that have the interrupt pin number hardwired to 0 (meaning
 165          * that they use the default INTA line, if they are interrupt
 166          * driven at all).
 167          */
 168         static char irq_tab[][5] __initdata = {
 169                 /*INT A   B   C   D */
 170                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */
 171                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 172                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 173                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 174                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 175                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 176                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 177                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 178                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 179         };
 180         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 181         int irq = COMMON_TABLE_LOOKUP, tmp;
 182         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 183         return irq >= 0 ? tmp : -1;
 184 }
 185
 186 static inline int __init
 187 p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 188 {
 189         static char irq_tab[][5] __initdata = {
 190                 /*INT A   B   C   D */
 191                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 192                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 193                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 194                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 195                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 196                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 197                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 198         };
 199         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 200         int irq = COMMON_TABLE_LOOKUP, tmp;
 201         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 202         return irq >= 0 ? tmp : -1;
 203 }
 204
 205 static inline void __init
 206 noname_init_pci(void)
 207 {
 208         common_init_pci();
 209         sio_pci_route();
 210         sio_fixup_irq_levels(sio_collect_irq_levels());
 211         ns87312_enable_ide(0x26e);
 212 }
 213
 214 static inline void __init
 215 alphabook1_init_pci(void)
 216 {
 217         struct pci_dev *dev;
 218         unsigned char orig, config;
 219
 220         common_init_pci();
 221         sio_pci_route();
 222
 223         /*
 224          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 225          * is sensitive to PCI bus bursts, so we must DISABLE
 226          * burst mode for the NCR 8xx SCSI... :-(
 227          *
 228          * Note that the NCR810 SCSI driver must preserve the
 229          * setting of the bit in order for this to work.  At the
 230          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 231          * 53c7,8xx.c DOES.
 232          */
 233
 234         dev = NULL;
 235         while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
 236                 if (dev->device == PCI_DEVICE_ID_NCR_53C810
 237                     || dev->device == PCI_DEVICE_ID_NCR_53C815
 238                     || dev->device == PCI_DEVICE_ID_NCR_53C820
 239                     || dev->device == PCI_DEVICE_ID_NCR_53C825) {
 240                         unsigned long io_port;
 241                         unsigned char ctest4;
 242
 243                         io_port = dev->resource[0].start;
 244                         ctest4 = inb(io_port+0x21);
 245                         if (!(ctest4 & 0x80)) {
 246                                 printk("AlphaBook1 NCR init: setting"
 247                                        " burst disable\n");
 248                                 outb(ctest4 | 0x80, io_port+0x21);
 249                         }
 250                 }
 251         }
 252
 253         /* Do not set *ANY* level triggers for AlphaBook1. */
 254         sio_fixup_irq_levels(0);
 255
 256         /* Make sure that register PR1 indicates 1Mb mem */
 257         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 258         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 259         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 260         if ((config & 0xc0) != 0xc0) {
 261                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 262                 config |= 0xc0;
 263                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 264         }
 265         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 266 }
 267
 268 void
 269 sio_kill_arch(int mode)
 270 {
 271 #if defined(ALPHA_RESTORE_SRM_SETUP)
 272         /* Since we cannot read the PCI DMA Window CSRs, we
 273          * cannot restore them here.
 274          *
 275          * However, we CAN read the PIRQ route register, so restore it
 276          * now...
 277          */
 278         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 279                                    saved_config.orig_route_tab);
 280 #endif
 281 }
 282
 283
 284 /*
 285  * The System Vectors
 286  */
 287
 288 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 289 struct alpha_machine_vector alphabook1_mv __initmv = {
 290         .vector_name            = "AlphaBook1",
 291         DO_EV4_MMU,
 292         DO_DEFAULT_RTC,
 293         DO_LCA_IO,
 294         .machine_check          = lca_machine_check,
 295         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 296         .min_io_address         = DEFAULT_IO_BASE,
 297         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 298
 299         .nr_irqs                = 16,
 300         .device_interrupt       = isa_device_interrupt,
 301
 302         .init_arch              = alphabook1_init_arch,
 303         .init_irq               = sio_init_irq,
 304         .init_rtc               = common_init_rtc,
 305         .init_pci               = alphabook1_init_pci,
 306         .kill_arch              = sio_kill_arch,
 307         .pci_map_irq            = noname_map_irq,
 308         .pci_swizzle            = common_swizzle,
 309
 310         .sys = { .sio = {
 311                 /* NCR810 SCSI is 14, PCMCIA controller is 15.  */
 312                 .route_tab      = 0x0e0f0a0a,
 313         }}
 314 };
 315 ALIAS_MV(alphabook1)
 316 #endif
 317
 318 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 319 struct alpha_machine_vector avanti_mv __initmv = {
 320         .vector_name            = "Avanti",
 321         DO_EV4_MMU,
 322         DO_DEFAULT_RTC,
 323         DO_APECS_IO,
 324         .machine_check          = apecs_machine_check,
 325         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 326         .min_io_address         = DEFAULT_IO_BASE,
 327         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 328
 329         .nr_irqs                = 16,
 330         .device_interrupt       = isa_device_interrupt,
 331
 332         .init_arch              = apecs_init_arch,
 333         .init_irq               = sio_init_irq,
 334         .init_rtc               = common_init_rtc,
 335         .init_pci               = noname_init_pci,
 336         .kill_arch              = sio_kill_arch,
 337         .pci_map_irq            = noname_map_irq,
 338         .pci_swizzle            = common_swizzle,
 339
 340         .sys = { .sio = {
 341                 .route_tab      = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
 342         }}
 343 };
 344 ALIAS_MV(avanti)
 345 #endif
 346
 347 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 348 struct alpha_machine_vector noname_mv __initmv = {
 349         .vector_name            = "Noname",
 350         DO_EV4_MMU,
 351         DO_DEFAULT_RTC,
 352         DO_LCA_IO,
 353         .machine_check          = lca_machine_check,
 354         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 355         .min_io_address         = DEFAULT_IO_BASE,
 356         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 357
 358         .nr_irqs                = 16,
 359         .device_interrupt       = srm_device_interrupt,
 360
 361         .init_arch              = lca_init_arch,
 362         .init_irq               = sio_init_irq,
 363         .init_rtc               = common_init_rtc,
 364         .init_pci               = noname_init_pci,
 365         .kill_arch              = sio_kill_arch,
 366         .pci_map_irq            = noname_map_irq,
 367         .pci_swizzle            = common_swizzle,
 368
 369         .sys = { .sio = {
 370                 /* For UDB, the only available PCI slot must not map to IRQ 9,
 371                    since that's the builtin MSS sound chip. That PCI slot
 372                    will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 373                    instead.
 374
 375                    Unfortunately we have to do this for NONAME as well, since
 376                    they are co-indicated when the platform type "Noname" is
 377                    selected... :-(  */
 378
 379                 .route_tab      = 0x0b0a0f0d,
 380         }}
 381 };
 382 ALIAS_MV(noname)
 383 #endif
 384
 385 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 386 struct alpha_machine_vector p2k_mv __initmv = {
 387         .vector_name            = "Platform2000",
 388         DO_EV4_MMU,
 389         DO_DEFAULT_RTC,
 390         DO_LCA_IO,
 391         .machine_check          = lca_machine_check,
 392         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 393         .min_io_address         = DEFAULT_IO_BASE,
 394         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 395
 396         .nr_irqs                = 16,
 397         .device_interrupt       = srm_device_interrupt,
 398
 399         .init_arch              = lca_init_arch,
 400         .init_irq               = sio_init_irq,
 401         .init_rtc               = common_init_rtc,
 402         .init_pci               = noname_init_pci,
 403         .kill_arch              = sio_kill_arch,
 404         .pci_map_irq            = p2k_map_irq,
 405         .pci_swizzle            = common_swizzle,
 406
 407         .sys = { .sio = {
 408                 .route_tab      = 0x0b0a090f,
 409         }}
 410 };
 411 ALIAS_MV(p2k)
 412 #endif
 413
 414 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 415 struct alpha_machine_vector xl_mv __initmv = {
 416         .vector_name            = "XL",
 417         DO_EV4_MMU,
 418         DO_DEFAULT_RTC,
 419         DO_APECS_IO,
 420         .machine_check          = apecs_machine_check,
 421         .max_isa_dma_address    = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
 422         .min_io_address         = DEFAULT_IO_BASE,
 423         .min_mem_address        = XL_DEFAULT_MEM_BASE,
 424
 425         .nr_irqs                = 16,
 426         .device_interrupt       = isa_device_interrupt,
 427
 428         .init_arch              = apecs_init_arch,
 429         .init_irq               = sio_init_irq,
 430         .init_rtc               = common_init_rtc,
 431         .init_pci               = noname_init_pci,
 432         .kill_arch              = sio_kill_arch,
 433         .pci_map_irq            = noname_map_irq,
 434         .pci_swizzle            = common_swizzle,
 435
 436         .sys = { .sio = {
 437                 .route_tab      = 0x0b0a090f,
 438         }}
 439 };
 440 ALIAS_MV(xl)
 441 #endif