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m68knommu: move ColdFire pit.c to its own coldfire directory
[wrt350n-kernel.git] / arch / arm / mach-ep93xx / core.c
blob91f6a07a51d54d16d28b8111f953b9b4fe0a04a3
1 /*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/time.h>
30 #include <linux/timex.h>
31 #include <linux/delay.h>
32 #include <linux/termios.h>
33 #include <linux/amba/bus.h>
34 #include <linux/amba/serial.h>
35
36 #include <asm/types.h>
37 #include <asm/setup.h>
38 #include <asm/memory.h>
39 #include <asm/hardware.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/tlbflush.h>
43 #include <asm/pgtable.h>
44 #include <asm/io.h>
45
46 #include <asm/mach/map.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/irq.h>
49 #include <asm/arch/gpio.h>
50
51 #include <asm/hardware/vic.h>
52
53
54 /*************************************************************************
55 * Static I/O mappings that are needed for all EP93xx platforms
56 *************************************************************************/
57 static struct map_desc ep93xx_io_desc[] __initdata = {
58 {
59 .virtual = EP93XX_AHB_VIRT_BASE,
60 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
61 .length = EP93XX_AHB_SIZE,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = EP93XX_APB_VIRT_BASE,
65 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
66 .length = EP93XX_APB_SIZE,
67 .type = MT_DEVICE,
68 },
69 };
70
71 void __init ep93xx_map_io(void)
72 {
73 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
74 }
75
76
77 /*************************************************************************
78 * Timer handling for EP93xx
79 *************************************************************************
80 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
81 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
82 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
83 * is free-running, and can't generate interrupts.
84 *
85 * The 508 kHz timers are ideal for use for the timer interrupt, as the
86 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
87 * bit timers (timer 1) since we don't need more than 16 bits of reload
88 * value as long as HZ >= 8.
89 *
90 * The higher clock rate of timer 4 makes it a better choice than the
91 * other timers for use in gettimeoffset(), while the fact that it can't
92 * generate interrupts means we don't have to worry about not being able
93 * to use this timer for something else. We also use timer 4 for keeping
94 * track of lost jiffies.
95 */
96 static unsigned int last_jiffy_time;
97
98 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
99
100 static int ep93xx_timer_interrupt(int irq, void *dev_id)
101 {
102 __raw_writel(1, EP93XX_TIMER1_CLEAR);
103 while ((signed long)
104 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
105 >= TIMER4_TICKS_PER_JIFFY) {
106 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
107 timer_tick();
108 }
109
110 return IRQ_HANDLED;
111 }
112
113 static struct irqaction ep93xx_timer_irq = {
114 .name = "ep93xx timer",
115 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
116 .handler = ep93xx_timer_interrupt,
117 };
118
119 static void __init ep93xx_timer_init(void)
120 {
121 /* Enable periodic HZ timer. */
122 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
123 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
124 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
125
126 /* Enable lost jiffy timer. */
127 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
128
129 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
130 }
131
132 static unsigned long ep93xx_gettimeoffset(void)
133 {
134 int offset;
135
136 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
137
138 /* Calculate (1000000 / 983040) * offset. */
139 return offset + (53 * offset / 3072);
140 }
141
142 struct sys_timer ep93xx_timer = {
143 .init = ep93xx_timer_init,
144 .offset = ep93xx_gettimeoffset,
145 };
146
147
148 /*************************************************************************
149 * GPIO handling for EP93xx
150 *************************************************************************/
151 static unsigned char gpio_int_unmasked[3];
152 static unsigned char gpio_int_enabled[3];
153 static unsigned char gpio_int_type1[3];
154 static unsigned char gpio_int_type2[3];
155
156 /* Port ordering is: A B F */
157 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
158 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
159 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
160 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
161
162 static void update_gpio_int_params(unsigned port)
163 {
164 BUG_ON(port > 2);
165
166 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
167
168 __raw_writeb(gpio_int_type2[port],
169 EP93XX_GPIO_REG(int_type2_register_offset[port]));
170
171 __raw_writeb(gpio_int_type1[port],
172 EP93XX_GPIO_REG(int_type1_register_offset[port]));
173
174 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
175 EP93XX_GPIO_REG(int_en_register_offset[port]));
176 }
177
178 /* Port ordering is: A B F D E C G H */
179 static const u8 data_register_offset[8] = {
180 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
181 };
182
183 static const u8 data_direction_register_offset[8] = {
184 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
185 };
186
187 #define GPIO_IN 0
188 #define GPIO_OUT 1
189
190 static void ep93xx_gpio_set_direction(unsigned line, int direction)
191 {
192 unsigned int data_direction_register;
193 unsigned long flags;
194 unsigned char v;
195
196 data_direction_register =
197 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
198
199 local_irq_save(flags);
200 if (direction == GPIO_OUT) {
201 if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
202 /* Port A/B/F */
203 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
204 update_gpio_int_params(line >> 3);
205 }
206
207 v = __raw_readb(data_direction_register);
208 v |= 1 << (line & 7);
209 __raw_writeb(v, data_direction_register);
210 } else if (direction == GPIO_IN) {
211 v = __raw_readb(data_direction_register);
212 v &= ~(1 << (line & 7));
213 __raw_writeb(v, data_direction_register);
214 }
215 local_irq_restore(flags);
216 }
217
218 int gpio_direction_input(unsigned gpio)
219 {
220 if (gpio > EP93XX_GPIO_LINE_MAX)
221 return -EINVAL;
222
223 ep93xx_gpio_set_direction(gpio, GPIO_IN);
224
225 return 0;
226 }
227 EXPORT_SYMBOL(gpio_direction_input);
228
229 int gpio_direction_output(unsigned gpio, int value)
230 {
231 if (gpio > EP93XX_GPIO_LINE_MAX)
232 return -EINVAL;
233
234 gpio_set_value(gpio, value);
235 ep93xx_gpio_set_direction(gpio, GPIO_OUT);
236
237 return 0;
238 }
239 EXPORT_SYMBOL(gpio_direction_output);
240
241 int gpio_get_value(unsigned gpio)
242 {
243 unsigned int data_register;
244
245 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
246
247 return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
248 }
249 EXPORT_SYMBOL(gpio_get_value);
250
251 void gpio_set_value(unsigned gpio, int value)
252 {
253 unsigned int data_register;
254 unsigned long flags;
255 unsigned char v;
256
257 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
258
259 local_irq_save(flags);
260 v = __raw_readb(data_register);
261 if (value)
262 v |= 1 << (gpio & 7);
263 else
264 v &= ~(1 << (gpio & 7));
265 __raw_writeb(v, data_register);
266 local_irq_restore(flags);
267 }
268 EXPORT_SYMBOL(gpio_set_value);
269
270
271 /*************************************************************************
272 * EP93xx IRQ handling
273 *************************************************************************/
274 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
275 {
276 unsigned char status;
277 int i;
278
279 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
280 for (i = 0; i < 8; i++) {
281 if (status & (1 << i)) {
282 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
283 desc = irq_desc + gpio_irq;
284 desc_handle_irq(gpio_irq, desc);
285 }
286 }
287
288 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
289 for (i = 0; i < 8; i++) {
290 if (status & (1 << i)) {
291 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
292 desc = irq_desc + gpio_irq;
293 desc_handle_irq(gpio_irq, desc);
294 }
295 }
296 }
297
298 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
299 {
300 /*
301 * map discontiguous hw irq range to continous sw irq range:
302 *
303 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
304 */
305 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
306 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
307
308 desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
309 }
310
311 static void ep93xx_gpio_irq_ack(unsigned int irq)
312 {
313 int line = irq_to_gpio(irq);
314 int port = line >> 3;
315 int port_mask = 1 << (line & 7);
316
317 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
318 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
319 update_gpio_int_params(port);
320 }
321
322 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
323 }
324
325 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
326 {
327 int line = irq_to_gpio(irq);
328 int port = line >> 3;
329 int port_mask = 1 << (line & 7);
330
331 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE)
332 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
333
334 gpio_int_unmasked[port] &= ~port_mask;
335 update_gpio_int_params(port);
336
337 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
338 }
339
340 static void ep93xx_gpio_irq_mask(unsigned int irq)
341 {
342 int line = irq_to_gpio(irq);
343 int port = line >> 3;
344
345 gpio_int_unmasked[port] &= ~(1 << (line & 7));
346 update_gpio_int_params(port);
347 }
348
349 static void ep93xx_gpio_irq_unmask(unsigned int irq)
350 {
351 int line = irq_to_gpio(irq);
352 int port = line >> 3;
353
354 gpio_int_unmasked[port] |= 1 << (line & 7);
355 update_gpio_int_params(port);
356 }
357
358
359 /*
360 * gpio_int_type1 controls whether the interrupt is level (0) or
361 * edge (1) triggered, while gpio_int_type2 controls whether it
362 * triggers on low/falling (0) or high/rising (1).
363 */
364 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
365 {
366 struct irq_desc *desc = irq_desc + irq;
367 const int gpio = irq_to_gpio(irq);
368 const int port = gpio >> 3;
369 const int port_mask = 1 << (gpio & 7);
370
371 ep93xx_gpio_set_direction(gpio, GPIO_IN);
372
373 switch (type) {
374 case IRQT_RISING:
375 gpio_int_type1[port] |= port_mask;
376 gpio_int_type2[port] |= port_mask;
377 desc->handle_irq = handle_edge_irq;
378 break;
379 case IRQT_FALLING:
380 gpio_int_type1[port] |= port_mask;
381 gpio_int_type2[port] &= ~port_mask;
382 desc->handle_irq = handle_edge_irq;
383 break;
384 case IRQT_HIGH:
385 gpio_int_type1[port] &= ~port_mask;
386 gpio_int_type2[port] |= port_mask;
387 desc->handle_irq = handle_level_irq;
388 break;
389 case IRQT_LOW:
390 gpio_int_type1[port] &= ~port_mask;
391 gpio_int_type2[port] &= ~port_mask;
392 desc->handle_irq = handle_level_irq;
393 break;
394 case IRQT_BOTHEDGE:
395 gpio_int_type1[port] |= port_mask;
396 /* set initial polarity based on current input level */
397 if (gpio_get_value(gpio))
398 gpio_int_type2[port] &= ~port_mask; /* falling */
399 else
400 gpio_int_type2[port] |= port_mask; /* rising */
401 desc->handle_irq = handle_edge_irq;
402 break;
403 default:
404 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
405 type, gpio);
406 return -EINVAL;
407 }
408
409 gpio_int_enabled[port] |= port_mask;
410
411 desc->status &= ~IRQ_TYPE_SENSE_MASK;
412 desc->status |= type & IRQ_TYPE_SENSE_MASK;
413
414 update_gpio_int_params(port);
415
416 return 0;
417 }
418
419 static struct irq_chip ep93xx_gpio_irq_chip = {
420 .name = "GPIO",
421 .ack = ep93xx_gpio_irq_ack,
422 .mask_ack = ep93xx_gpio_irq_mask_ack,
423 .mask = ep93xx_gpio_irq_mask,
424 .unmask = ep93xx_gpio_irq_unmask,
425 .set_type = ep93xx_gpio_irq_type,
426 };
427
428
429 void __init ep93xx_init_irq(void)
430 {
431 int gpio_irq;
432
433 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
434 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
435
436 for (gpio_irq = gpio_to_irq(0);
437 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
438 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
439 set_irq_handler(gpio_irq, handle_level_irq);
440 set_irq_flags(gpio_irq, IRQF_VALID);
441 }
442
443 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
444 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
445 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
446 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
447 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
448 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
449 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
450 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
451 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
452 }
453
454
455 /*************************************************************************
456 * EP93xx peripheral handling
457 *************************************************************************/
458 #define EP93XX_UART_MCR_OFFSET (0x0100)
459
460 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
461 void __iomem *base, unsigned int mctrl)
462 {
463 unsigned int mcr;
464
465 mcr = 0;
466 if (!(mctrl & TIOCM_RTS))
467 mcr |= 2;
468 if (!(mctrl & TIOCM_DTR))
469 mcr |= 1;
470
471 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
472 }
473
474 static struct amba_pl010_data ep93xx_uart_data = {
475 .set_mctrl = ep93xx_uart_set_mctrl,
476 };
477
478 static struct amba_device uart1_device = {
479 .dev = {
480 .bus_id = "apb:uart1",
481 .platform_data = &ep93xx_uart_data,
482 },
483 .res = {
484 .start = EP93XX_UART1_PHYS_BASE,
485 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
486 .flags = IORESOURCE_MEM,
487 },
488 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
489 .periphid = 0x00041010,
490 };
491
492 static struct amba_device uart2_device = {
493 .dev = {
494 .bus_id = "apb:uart2",
495 .platform_data = &ep93xx_uart_data,
496 },
497 .res = {
498 .start = EP93XX_UART2_PHYS_BASE,
499 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
500 .flags = IORESOURCE_MEM,
501 },
502 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
503 .periphid = 0x00041010,
504 };
505
506 static struct amba_device uart3_device = {
507 .dev = {
508 .bus_id = "apb:uart3",
509 .platform_data = &ep93xx_uart_data,
510 },
511 .res = {
512 .start = EP93XX_UART3_PHYS_BASE,
513 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
514 .flags = IORESOURCE_MEM,
515 },
516 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
517 .periphid = 0x00041010,
518 };
519
520
521 static struct platform_device ep93xx_rtc_device = {
522 .name = "ep93xx-rtc",
523 .id = -1,
524 .num_resources = 0,
525 };
526
527
528 static struct resource ep93xx_ohci_resources[] = {
529 [0] = {
530 .start = EP93XX_USB_PHYS_BASE,
531 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
532 .flags = IORESOURCE_MEM,
533 },
534 [1] = {
535 .start = IRQ_EP93XX_USB,
536 .end = IRQ_EP93XX_USB,
537 .flags = IORESOURCE_IRQ,
538 },
539 };
540
541 static struct platform_device ep93xx_ohci_device = {
542 .name = "ep93xx-ohci",
543 .id = -1,
544 .dev = {
545 .dma_mask = (void *)0xffffffff,
546 .coherent_dma_mask = 0xffffffff,
547 },
548 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
549 .resource = ep93xx_ohci_resources,
550 };
551
552
553 void __init ep93xx_init_devices(void)
554 {
555 unsigned int v;
556
557 /*
558 * Disallow access to MaverickCrunch initially.
559 */
560 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
561 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
562 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
563 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
564
565 amba_device_register(&uart1_device, &iomem_resource);
566 amba_device_register(&uart2_device, &iomem_resource);
567 amba_device_register(&uart3_device, &iomem_resource);
568
569 platform_device_register(&ep93xx_rtc_device);
570 platform_device_register(&ep93xx_ohci_device);
571 }
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