arch/arm/mach-iop13xx/irq.c

   1 /*
   2  * iop13xx IRQ handling / support functions
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/sysctl.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/irq.h>
  26 #include <asm/hardware.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/arch/irqs.h>
  29 #include <asm/arch/msi.h>
  30
  31 /* INTCTL0 CP6 R0 Page 4
  32  */
  33 static u32 read_intctl_0(void)
  34 {
  35         u32 val;
  36         asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
  37         return val;
  38 }
  39 static void write_intctl_0(u32 val)
  40 {
  41         asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
  42 }
  43
  44 /* INTCTL1 CP6 R1 Page 4
  45  */
  46 static u32 read_intctl_1(void)
  47 {
  48         u32 val;
  49         asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
  50         return val;
  51 }
  52 static void write_intctl_1(u32 val)
  53 {
  54         asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
  55 }
  56
  57 /* INTCTL2 CP6 R2 Page 4
  58  */
  59 static u32 read_intctl_2(void)
  60 {
  61         u32 val;
  62         asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
  63         return val;
  64 }
  65 static void write_intctl_2(u32 val)
  66 {
  67         asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
  68 }
  69
  70 /* INTCTL3 CP6 R3 Page 4
  71  */
  72 static u32 read_intctl_3(void)
  73 {
  74         u32 val;
  75         asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
  76         return val;
  77 }
  78 static void write_intctl_3(u32 val)
  79 {
  80         asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
  81 }
  82
  83 /* INTSTR0 CP6 R0 Page 5
  84  */
  85 static void write_intstr_0(u32 val)
  86 {
  87         asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
  88 }
  89
  90 /* INTSTR1 CP6 R1 Page 5
  91  */
  92 static void write_intstr_1(u32 val)
  93 {
  94         asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
  95 }
  96
  97 /* INTSTR2 CP6 R2 Page 5
  98  */
  99 static void write_intstr_2(u32 val)
 100 {
 101         asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
 102 }
 103
 104 /* INTSTR3 CP6 R3 Page 5
 105  */
 106 static void write_intstr_3(u32 val)
 107 {
 108         asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
 109 }
 110
 111 /* INTBASE CP6 R0 Page 2
 112  */
 113 static void write_intbase(u32 val)
 114 {
 115         asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
 116 }
 117
 118 /* INTSIZE CP6 R2 Page 2
 119  */
 120 static void write_intsize(u32 val)
 121 {
 122         asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
 123 }
 124
 125 /* 0 = Interrupt Masked and 1 = Interrupt not masked */
 126 static void
 127 iop13xx_irq_mask0 (unsigned int irq)
 128 {
 129         write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
 130 }
 131
 132 static void
 133 iop13xx_irq_mask1 (unsigned int irq)
 134 {
 135         write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
 136 }
 137
 138 static void
 139 iop13xx_irq_mask2 (unsigned int irq)
 140 {
 141         write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
 142 }
 143
 144 static void
 145 iop13xx_irq_mask3 (unsigned int irq)
 146 {
 147         write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
 148 }
 149
 150 static void
 151 iop13xx_irq_unmask0(unsigned int irq)
 152 {
 153         write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
 154 }
 155
 156 static void
 157 iop13xx_irq_unmask1(unsigned int irq)
 158 {
 159         write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
 160 }
 161
 162 static void
 163 iop13xx_irq_unmask2(unsigned int irq)
 164 {
 165         write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
 166 }
 167
 168 static void
 169 iop13xx_irq_unmask3(unsigned int irq)
 170 {
 171         write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
 172 }
 173
 174 static struct irq_chip iop13xx_irqchip1 = {
 175         .name   = "IOP13xx-1",
 176         .ack    = iop13xx_irq_mask0,
 177         .mask   = iop13xx_irq_mask0,
 178         .unmask = iop13xx_irq_unmask0,
 179 };
 180
 181 static struct irq_chip iop13xx_irqchip2 = {
 182         .name   = "IOP13xx-2",
 183         .ack    = iop13xx_irq_mask1,
 184         .mask   = iop13xx_irq_mask1,
 185         .unmask = iop13xx_irq_unmask1,
 186 };
 187
 188 static struct irq_chip iop13xx_irqchip3 = {
 189         .name   = "IOP13xx-3",
 190         .ack    = iop13xx_irq_mask2,
 191         .mask   = iop13xx_irq_mask2,
 192         .unmask = iop13xx_irq_unmask2,
 193 };
 194
 195 static struct irq_chip iop13xx_irqchip4 = {
 196         .name   = "IOP13xx-4",
 197         .ack    = iop13xx_irq_mask3,
 198         .mask   = iop13xx_irq_mask3,
 199         .unmask = iop13xx_irq_unmask3,
 200 };
 201
 202 extern void iop_init_cp6_handler(void);
 203
 204 void __init iop13xx_init_irq(void)
 205 {
 206         unsigned int i;
 207
 208         iop_init_cp6_handler();
 209
 210         /* disable all interrupts */
 211         write_intctl_0(0);
 212         write_intctl_1(0);
 213         write_intctl_2(0);
 214         write_intctl_3(0);
 215
 216         /* treat all as IRQ */
 217         write_intstr_0(0);
 218         write_intstr_1(0);
 219         write_intstr_2(0);
 220         write_intstr_3(0);
 221
 222         /* initialize the interrupt vector generator */
 223         write_intbase(INTBASE);
 224         write_intsize(INTSIZE_4);
 225
 226         for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
 227                 if (i < 32)
 228                         set_irq_chip(i, &iop13xx_irqchip1);
 229                 else if (i < 64)
 230                         set_irq_chip(i, &iop13xx_irqchip2);
 231                 else if (i < 96)
 232                         set_irq_chip(i, &iop13xx_irqchip3);
 233                 else
 234                         set_irq_chip(i, &iop13xx_irqchip4);
 235
 236                 set_irq_handler(i, handle_level_irq);
 237                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 238         }
 239
 240         iop13xx_msi_init();
 241 }