arch/arm/mach-omap1/time.c

   1 /*
   2  * linux/arch/arm/mach-omap1/time.c
   3  *
   4  * OMAP Timers
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *
  11  * MPU timer code based on the older MPU timer code for OMAP
  12  * Copyright (C) 2000 RidgeRun, Inc.
  13  * Author: Greg Lonnon <glonnon@ridgerun.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the  GNU General Public License along
  32  * with this program; if not, write  to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/sched.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/clk.h>
  43 #include <linux/err.h>
  44 #include <linux/clocksource.h>
  45 #include <linux/clockchips.h>
  46
  47 #include <asm/system.h>
  48 #include <asm/hardware.h>
  49 #include <asm/io.h>
  50 #include <asm/leds.h>
  51 #include <asm/irq.h>
  52 #include <asm/mach/irq.h>
  53 #include <asm/mach/time.h>
  54
  55
  56 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
  57 #define OMAP_MPU_TIMER_OFFSET           0x100
  58
  59 /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
  60  * converted to use kHz by Kevin Hilman */
  61 /* convert from cycles(64bits) => nanoseconds (64bits)
  62  *  basic equation:
  63  *              ns = cycles / (freq / ns_per_sec)
  64  *              ns = cycles * (ns_per_sec / freq)
  65  *              ns = cycles * (10^9 / (cpu_khz * 10^3))
  66  *              ns = cycles * (10^6 / cpu_khz)
  67  *
  68  *      Then we use scaling math (suggested by george at mvista.com) to get:
  69  *              ns = cycles * (10^6 * SC / cpu_khz / SC
  70  *              ns = cycles * cyc2ns_scale / SC
  71  *
  72  *      And since SC is a constant power of two, we can convert the div
  73  *  into a shift.
  74  *                      -johnstul at us.ibm.com "math is hard, lets go shopping!"
  75  */
  76 static unsigned long cyc2ns_scale;
  77 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
  78
  79 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
  80 {
  81         cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
  82 }
  83
  84 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
  85 {
  86         return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
  87 }
  88
  89
  90 typedef struct {
  91         u32 cntl;                       /* CNTL_TIMER, R/W */
  92         u32 load_tim;                   /* LOAD_TIM,   W */
  93         u32 read_tim;                   /* READ_TIM,   R */
  94 } omap_mpu_timer_regs_t;
  95
  96 #define omap_mpu_timer_base(n)                                          \
  97 ((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +      \
  98                                  (n)*OMAP_MPU_TIMER_OFFSET))
  99
 100 static inline unsigned long omap_mpu_timer_read(int nr)
 101 {
 102         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 103         return timer->read_tim;
 104 }
 105
 106 static inline void omap_mpu_set_autoreset(int nr)
 107 {
 108         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 109
 110         timer->cntl = timer->cntl | MPU_TIMER_AR;
 111 }
 112
 113 static inline void omap_mpu_remove_autoreset(int nr)
 114 {
 115         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 116
 117         timer->cntl = timer->cntl & ~MPU_TIMER_AR;
 118 }
 119
 120 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
 121                                         int autoreset)
 122 {
 123         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 124         unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
 125
 126         if (autoreset) timerflags |= MPU_TIMER_AR;
 127
 128         timer->cntl = MPU_TIMER_CLOCK_ENABLE;
 129         udelay(1);
 130         timer->load_tim = load_val;
 131         udelay(1);
 132         timer->cntl = timerflags;
 133 }
 134
 135 /*
 136  * ---------------------------------------------------------------------------
 137  * MPU timer 1 ... count down to zero, interrupt, reload
 138  * ---------------------------------------------------------------------------
 139  */
 140 static int omap_mpu_set_next_event(unsigned long cycles,
 141                                     struct clock_event_device *evt)
 142 {
 143         omap_mpu_timer_start(0, cycles, 0);
 144         return 0;
 145 }
 146
 147 static void omap_mpu_set_mode(enum clock_event_mode mode,
 148                               struct clock_event_device *evt)
 149 {
 150         switch (mode) {
 151         case CLOCK_EVT_MODE_PERIODIC:
 152                 omap_mpu_set_autoreset(0);
 153                 break;
 154         case CLOCK_EVT_MODE_ONESHOT:
 155                 omap_mpu_remove_autoreset(0);
 156                 break;
 157         case CLOCK_EVT_MODE_UNUSED:
 158         case CLOCK_EVT_MODE_SHUTDOWN:
 159         case CLOCK_EVT_MODE_RESUME:
 160                 break;
 161         }
 162 }
 163
 164 static struct clock_event_device clockevent_mpu_timer1 = {
 165         .name           = "mpu_timer1",
 166         .features       = CLOCK_EVT_FEAT_PERIODIC, CLOCK_EVT_FEAT_ONESHOT,
 167         .shift          = 32,
 168         .set_next_event = omap_mpu_set_next_event,
 169         .set_mode       = omap_mpu_set_mode,
 170 };
 171
 172 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
 173 {
 174         struct clock_event_device *evt = &clockevent_mpu_timer1;
 175
 176         evt->event_handler(evt);
 177
 178         return IRQ_HANDLED;
 179 }
 180
 181 static struct irqaction omap_mpu_timer1_irq = {
 182         .name           = "mpu_timer1",
 183         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 184         .handler        = omap_mpu_timer1_interrupt,
 185 };
 186
 187 static __init void omap_init_mpu_timer(unsigned long rate)
 188 {
 189         set_cyc2ns_scale(rate / 1000);
 190
 191         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
 192         omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
 193
 194         clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
 195                                             clockevent_mpu_timer1.shift);
 196         clockevent_mpu_timer1.max_delta_ns =
 197                 clockevent_delta2ns(-1, &clockevent_mpu_timer1);
 198         clockevent_mpu_timer1.min_delta_ns =
 199                 clockevent_delta2ns(1, &clockevent_mpu_timer1);
 200
 201         clockevent_mpu_timer1.cpumask = cpumask_of_cpu(0);
 202         clockevents_register_device(&clockevent_mpu_timer1);
 203 }
 204
 205
 206 /*
 207  * ---------------------------------------------------------------------------
 208  * MPU timer 2 ... free running 32-bit clock source and scheduler clock
 209  * ---------------------------------------------------------------------------
 210  */
 211
 212 static unsigned long omap_mpu_timer2_overflows;
 213
 214 static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
 215 {
 216         omap_mpu_timer2_overflows++;
 217         return IRQ_HANDLED;
 218 }
 219
 220 static struct irqaction omap_mpu_timer2_irq = {
 221         .name           = "mpu_timer2",
 222         .flags          = IRQF_DISABLED,
 223         .handler        = omap_mpu_timer2_interrupt,
 224 };
 225
 226 static cycle_t mpu_read(void)
 227 {
 228         return ~omap_mpu_timer_read(1);
 229 }
 230
 231 static struct clocksource clocksource_mpu = {
 232         .name           = "mpu_timer2",
 233         .rating         = 300,
 234         .read           = mpu_read,
 235         .mask           = CLOCKSOURCE_MASK(32),
 236         .shift          = 24,
 237         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 238 };
 239
 240 static void __init omap_init_clocksource(unsigned long rate)
 241 {
 242         static char err[] __initdata = KERN_ERR
 243                         "%s: can't register clocksource!\n";
 244
 245         clocksource_mpu.mult
 246                 = clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
 247
 248         setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
 249         omap_mpu_timer_start(1, ~0, 1);
 250
 251         if (clocksource_register(&clocksource_mpu))
 252                 printk(err, clocksource_mpu.name);
 253 }
 254
 255
 256 /*
 257  * Scheduler clock - returns current time in nanosec units.
 258  */
 259 unsigned long long sched_clock(void)
 260 {
 261         unsigned long ticks = 0 - omap_mpu_timer_read(1);
 262         unsigned long long ticks64;
 263
 264         ticks64 = omap_mpu_timer2_overflows;
 265         ticks64 <<= 32;
 266         ticks64 |= ticks;
 267
 268         return cycles_2_ns(ticks64);
 269 }
 270
 271 /*
 272  * ---------------------------------------------------------------------------
 273  * Timer initialization
 274  * ---------------------------------------------------------------------------
 275  */
 276 static void __init omap_timer_init(void)
 277 {
 278         struct clk      *ck_ref = clk_get(NULL, "ck_ref");
 279         unsigned long   rate;
 280
 281         BUG_ON(IS_ERR(ck_ref));
 282
 283         rate = clk_get_rate(ck_ref);
 284         clk_put(ck_ref);
 285
 286         /* PTV = 0 */
 287         rate /= 2;
 288
 289         omap_init_mpu_timer(rate);
 290         omap_init_clocksource(rate);
 291 }
 292
 293 struct sys_timer omap_timer = {
 294         .init           = omap_timer_init,
 295 };