m68knommu: move ColdFire pit.c to its own coldfire directory
[wrt350n-kernel.git] / arch / arm / mach-omap2 / irq.c
blobf064f725e724aed9394178820167c54d2eb29b56
1 /*
2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <asm/hardware.h>
17 #include <asm/mach/irq.h>
18 #include <asm/irq.h>
19 #include <asm/io.h>
21 #define INTC_REVISION 0x0000
22 #define INTC_SYSCONFIG 0x0010
23 #define INTC_SYSSTATUS 0x0014
24 #define INTC_CONTROL 0x0048
25 #define INTC_MIR_CLEAR0 0x0088
26 #define INTC_MIR_SET0 0x008c
29 * OMAP2 has a number of different interrupt controllers, each interrupt
30 * controller is identified as its own "bank". Register definitions are
31 * fairly consistent for each bank, but not all registers are implemented
32 * for each bank.. when in doubt, consult the TRM.
34 static struct omap_irq_bank {
35 unsigned long base_reg;
36 unsigned int nr_irqs;
37 } __attribute__ ((aligned(4))) irq_banks[] = {
39 /* MPU INTC */
40 .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE),
41 .nr_irqs = 96,
42 }, {
43 /* XXX: DSP INTC */
47 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
48 static void omap_ack_irq(unsigned int irq)
50 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
53 static void omap_mask_irq(unsigned int irq)
55 int offset = (irq >> 5) << 5;
57 if (irq >= 64) {
58 irq %= 64;
59 } else if (irq >= 32) {
60 irq %= 32;
63 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
66 static void omap_unmask_irq(unsigned int irq)
68 int offset = (irq >> 5) << 5;
70 if (irq >= 64) {
71 irq %= 64;
72 } else if (irq >= 32) {
73 irq %= 32;
76 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
79 static void omap_mask_ack_irq(unsigned int irq)
81 omap_mask_irq(irq);
82 omap_ack_irq(irq);
85 static struct irq_chip omap_irq_chip = {
86 .name = "INTC",
87 .ack = omap_mask_ack_irq,
88 .mask = omap_mask_irq,
89 .unmask = omap_unmask_irq,
92 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
94 unsigned long tmp;
96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
98 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
101 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
102 tmp |= 1 << 1; /* soft reset */
103 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
105 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
106 /* Wait for reset to complete */;
108 /* Enable autoidle */
109 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
112 void __init omap_init_irq(void)
114 unsigned long nr_irqs = 0;
115 unsigned int nr_banks = 0;
116 int i;
118 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
119 struct omap_irq_bank *bank = irq_banks + i;
121 /* XXX */
122 if (!bank->base_reg)
123 continue;
125 omap_irq_bank_init_one(bank);
127 nr_irqs += bank->nr_irqs;
128 nr_banks++;
131 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
132 nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
134 for (i = 0; i < nr_irqs; i++) {
135 set_irq_chip(i, &omap_irq_chip);
136 set_irq_handler(i, handle_level_irq);
137 set_irq_flags(i, IRQF_VALID);