arch/arm/mach-omap2/memory.c

   1 /*
   2  * linux/arch/arm/mach-omap2/memory.c
   3  *
   4  * Memory timing related functions for OMAP24XX
   5  *
   6  * Copyright (C) 2005 Texas Instruments Inc.
   7  * Richard Woodruff <r-woodruff2@ti.com>
   8  *
   9  * Copyright (C) 2005 Nokia Corporation
  10  * Tony Lindgren <tony@atomide.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/list.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/io.h>
  26
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/sram.h>
  29
  30 #include "prcm-regs.h"
  31 #include "memory.h"
  32
  33
  34 static struct memory_timings mem_timings;
  35
  36 u32 omap2_memory_get_slow_dll_ctrl(void)
  37 {
  38         return mem_timings.slow_dll_ctrl;
  39 }
  40
  41 u32 omap2_memory_get_fast_dll_ctrl(void)
  42 {
  43         return mem_timings.fast_dll_ctrl;
  44 }
  45
  46 u32 omap2_memory_get_type(void)
  47 {
  48         return mem_timings.m_type;
  49 }
  50
  51 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
  52 {
  53         unsigned long dll_cnt;
  54         u32 fast_dll = 0;
  55
  56         mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
  57
  58         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
  59          * In the case of 2422, its ok to use CS1 instead of CS0.
  60          */
  61         if (cpu_is_omap2422())
  62                 mem_timings.base_cs = 1;
  63         else
  64                 mem_timings.base_cs = 0;
  65
  66         if (mem_timings.m_type != M_DDR)
  67                 return;
  68
  69         /* With DDR we need to determine the low frequency DLL value */
  70         if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
  71                 mem_timings.dll_mode = M_UNLOCK;
  72         else
  73                 mem_timings.dll_mode = M_LOCK;
  74
  75         if (mem_timings.base_cs == 0) {
  76                 fast_dll = SDRC_DLLA_CTRL;
  77                 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
  78         } else {
  79                 fast_dll = SDRC_DLLB_CTRL;
  80                 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
  81         }
  82         if (force_lock_to_unlock_mode) {
  83                 fast_dll &= ~0xff00;
  84                 fast_dll |= dll_cnt;            /* Current lock mode */
  85         }
  86         /* set fast timings with DLL filter disabled */
  87         mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
  88
  89         /* No disruptions, DDR will be offline & C-ABI not followed */
  90         omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
  91                             mem_timings.fast_dll_ctrl,
  92                             mem_timings.base_cs,
  93                             force_lock_to_unlock_mode);
  94         mem_timings.slow_dll_ctrl &= 0xff00;    /* Keep lock value */
  95
  96         /* Turn status into unlock ctrl */
  97         mem_timings.slow_dll_ctrl |=
  98                 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
  99
 100         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
 101         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 102 }
 103
 104 /* turn on smart idle modes for SDRAM scheduler and controller */
 105 void __init omap2_init_memory(void)
 106 {
 107         u32 l;
 108
 109         l = SMS_SYSCONFIG;
 110         l &= ~(0x3 << 3);
 111         l |= (0x2 << 3);
 112         SMS_SYSCONFIG = l;
 113
 114         l = SDRC_SYSCONFIG;
 115         l &= ~(0x3 << 3);
 116         l |= (0x2 << 3);
 117         SDRC_SYSCONFIG = l;
 118
 119 }