arch/arm/mach-orion/db88f5281-setup.c

   1 /*
   2  * arch/arm/mach-orion/db88f5281-setup.c
   3  *
   4  * Marvell Orion-2 Development Board Setup
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pci.h>
  17 #include <linux/irq.h>
  18 #include <linux/mtd/physmap.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/timer.h>
  21 #include <linux/mv643xx_eth.h>
  22 #include <linux/i2c.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/gpio.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/pci.h>
  27 #include <asm/arch/orion.h>
  28 #include <asm/arch/platform.h>
  29 #include "common.h"
  30
  31 /*****************************************************************************
  32  * DB-88F5281 on board devices
  33  ****************************************************************************/
  34
  35 /*
  36  * 512K NOR flash Device bus boot chip select
  37  */
  38
  39 #define DB88F5281_NOR_BOOT_BASE         0xf4000000
  40 #define DB88F5281_NOR_BOOT_SIZE         SZ_512K
  41
  42 /*
  43  * 7-Segment on Device bus chip select 0
  44  */
  45
  46 #define DB88F5281_7SEG_BASE             0xfa000000
  47 #define DB88F5281_7SEG_SIZE             SZ_1K
  48
  49 /*
  50  * 32M NOR flash on Device bus chip select 1
  51  */
  52
  53 #define DB88F5281_NOR_BASE              0xfc000000
  54 #define DB88F5281_NOR_SIZE              SZ_32M
  55
  56 /*
  57  * 32M NAND flash on Device bus chip select 2
  58  */
  59
  60 #define DB88F5281_NAND_BASE             0xfa800000
  61 #define DB88F5281_NAND_SIZE             SZ_1K
  62
  63 /*
  64  * PCI
  65  */
  66
  67 #define DB88F5281_PCI_SLOT0_OFFS                7
  68 #define DB88F5281_PCI_SLOT0_IRQ_PIN             12
  69 #define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN       13
  70
  71 /*****************************************************************************
  72  * 512M NOR Flash on Device bus Boot CS
  73  ****************************************************************************/
  74
  75 static struct physmap_flash_data db88f5281_boot_flash_data = {
  76         .width          = 1,    /* 8 bit bus width */
  77 };
  78
  79 static struct resource db88f5281_boot_flash_resource = {
  80         .flags          = IORESOURCE_MEM,
  81         .start          = DB88F5281_NOR_BOOT_BASE,
  82         .end            = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
  83 };
  84
  85 static struct platform_device db88f5281_boot_flash = {
  86         .name           = "physmap-flash",
  87         .id             = 0,
  88         .dev            = {
  89                 .platform_data = &db88f5281_boot_flash_data,
  90         },
  91         .num_resources  = 1,
  92         .resource       = &db88f5281_boot_flash_resource,
  93 };
  94
  95 /*****************************************************************************
  96  * 32M NOR Flash on Device bus CS1
  97  ****************************************************************************/
  98
  99 static struct physmap_flash_data db88f5281_nor_flash_data = {
 100         .width          = 4,    /* 32 bit bus width */
 101 };
 102
 103 static struct resource db88f5281_nor_flash_resource = {
 104         .flags          = IORESOURCE_MEM,
 105         .start          = DB88F5281_NOR_BASE,
 106         .end            = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
 107 };
 108
 109 static struct platform_device db88f5281_nor_flash = {
 110         .name           = "physmap-flash",
 111         .id             = 1,
 112         .dev            = {
 113                 .platform_data = &db88f5281_nor_flash_data,
 114         },
 115         .num_resources  = 1,
 116         .resource       = &db88f5281_nor_flash_resource,
 117 };
 118
 119 /*****************************************************************************
 120  * 32M NAND Flash on Device bus CS2
 121  ****************************************************************************/
 122
 123 static struct mtd_partition db88f5281_nand_parts[] = {
 124         {
 125                 .name = "kernel",
 126                 .offset = 0,
 127                 .size = SZ_2M,
 128         },
 129         {
 130                 .name = "root",
 131                 .offset = SZ_2M,
 132                 .size = (SZ_16M - SZ_2M),
 133         },
 134         {
 135                 .name = "user",
 136                 .offset = SZ_16M,
 137                 .size = SZ_8M,
 138         },
 139         {
 140                 .name = "recovery",
 141                 .offset = (SZ_16M + SZ_8M),
 142                 .size = SZ_8M,
 143         },
 144 };
 145
 146 static struct resource db88f5281_nand_resource = {
 147         .flags          = IORESOURCE_MEM,
 148         .start          = DB88F5281_NAND_BASE,
 149         .end            = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
 150 };
 151
 152 static struct orion_nand_data db88f5281_nand_data = {
 153         .parts          = db88f5281_nand_parts,
 154         .nr_parts       = ARRAY_SIZE(db88f5281_nand_parts),
 155         .cle            = 0,
 156         .ale            = 1,
 157         .width          = 8,
 158 };
 159
 160 static struct platform_device db88f5281_nand_flash = {
 161         .name           = "orion_nand",
 162         .id             = -1,
 163         .dev            = {
 164                 .platform_data  = &db88f5281_nand_data,
 165         },
 166         .resource       = &db88f5281_nand_resource,
 167         .num_resources  = 1,
 168 };
 169
 170 /*****************************************************************************
 171  * 7-Segment on Device bus CS0
 172  * Dummy counter every 2 sec
 173  ****************************************************************************/
 174
 175 static void __iomem *db88f5281_7seg;
 176 static struct timer_list db88f5281_timer;
 177
 178 static void db88f5281_7seg_event(unsigned long data)
 179 {
 180         static int count = 0;
 181         writel(0, db88f5281_7seg + (count << 4));
 182         count = (count + 1) & 7;
 183         mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
 184 }
 185
 186 static int __init db88f5281_7seg_init(void)
 187 {
 188         if (machine_is_db88f5281()) {
 189                 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
 190                                         DB88F5281_7SEG_SIZE);
 191                 if (!db88f5281_7seg) {
 192                         printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
 193                         return -EIO;
 194                 }
 195                 setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
 196                 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
 197         }
 198
 199         return 0;
 200 }
 201
 202 __initcall(db88f5281_7seg_init);
 203
 204 /*****************************************************************************
 205  * PCI
 206  ****************************************************************************/
 207
 208 void __init db88f5281_pci_preinit(void)
 209 {
 210         int pin;
 211
 212         /*
 213          * Configure PCI GPIO IRQ pins
 214          */
 215         pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
 216         if (gpio_request(pin, "PCI Int1") == 0) {
 217                 if (gpio_direction_input(pin) == 0) {
 218                         set_irq_type(gpio_to_irq(pin), IRQT_LOW);
 219                 } else {
 220                         printk(KERN_ERR "db88f5281_pci_preinit faield to "
 221                                         "set_irq_type pin %d\n", pin);
 222                         gpio_free(pin);
 223                 }
 224         } else {
 225                 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
 226         }
 227
 228         pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
 229         if (gpio_request(pin, "PCI Int2") == 0) {
 230                 if (gpio_direction_input(pin) == 0) {
 231                         set_irq_type(gpio_to_irq(pin), IRQT_LOW);
 232                 } else {
 233                         printk(KERN_ERR "db88f5281_pci_preinit faield "
 234                                         "to set_irq_type pin %d\n", pin);
 235                         gpio_free(pin);
 236                 }
 237         } else {
 238                 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
 239         }
 240 }
 241
 242 static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 243 {
 244         /*
 245          * PCIE IRQ is connected internally (not GPIO)
 246          */
 247         if (dev->bus->number == orion_pcie_local_bus_nr())
 248                 return IRQ_ORION_PCIE0_INT;
 249
 250         /*
 251          * PCI IRQs are connected via GPIOs
 252          */
 253         switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
 254         case 0:
 255                 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
 256         case 1:
 257         case 2:
 258                 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
 259         default:
 260                 return -1;
 261         }
 262 }
 263
 264 static struct hw_pci db88f5281_pci __initdata = {
 265         .nr_controllers = 2,
 266         .preinit        = db88f5281_pci_preinit,
 267         .swizzle        = pci_std_swizzle,
 268         .setup          = orion_pci_sys_setup,
 269         .scan           = orion_pci_sys_scan_bus,
 270         .map_irq        = db88f5281_pci_map_irq,
 271 };
 272
 273 static int __init db88f5281_pci_init(void)
 274 {
 275         if (machine_is_db88f5281())
 276                 pci_common_init(&db88f5281_pci);
 277
 278         return 0;
 279 }
 280
 281 subsys_initcall(db88f5281_pci_init);
 282
 283 /*****************************************************************************
 284  * Ethernet
 285  ****************************************************************************/
 286 static struct mv643xx_eth_platform_data db88f5281_eth_data = {
 287         .phy_addr       = 8,
 288         .force_phy_addr = 1,
 289 };
 290
 291 /*****************************************************************************
 292  * RTC DS1339 on I2C bus
 293  ****************************************************************************/
 294 static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
 295         .driver_name    = "rtc-ds1307",
 296         .type           = "ds1339",
 297         .addr           = 0x68,
 298 };
 299
 300 /*****************************************************************************
 301  * General Setup
 302  ****************************************************************************/
 303
 304 static struct platform_device *db88f5281_devs[] __initdata = {
 305         &db88f5281_boot_flash,
 306         &db88f5281_nor_flash,
 307         &db88f5281_nand_flash,
 308 };
 309
 310 static void __init db88f5281_init(void)
 311 {
 312         /*
 313          * Basic Orion setup. Need to be called early.
 314          */
 315         orion_init();
 316
 317         /*
 318          * Setup the CPU address decode windows for our on-board devices
 319          */
 320         orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
 321                                 DB88F5281_NOR_BOOT_SIZE, -1);
 322         orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
 323                                 DB88F5281_7SEG_SIZE, -1);
 324         orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
 325                                 DB88F5281_NOR_SIZE, -1);
 326         orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
 327                                 DB88F5281_NAND_SIZE, -1);
 328
 329         /*
 330          * Setup Multiplexing Pins:
 331          * MPP0: GPIO (USB Over Current)        MPP1: GPIO (USB Vbat input)
 332          * MPP2: PCI_REQn[2]                    MPP3: PCI_GNTn[2]
 333          * MPP4: PCI_REQn[3]                    MPP5: PCI_GNTn[3]
 334          * MPP6: GPIO (JP0, CON17.2)            MPP7: GPIO (JP1, CON17.1)
 335          * MPP8: GPIO (JP2, CON11.2)            MPP9: GPIO (JP3, CON11.3)
 336          * MPP10: GPIO (RTC int)                MPP11: GPIO (Baud Rate Generator)
 337          * MPP12: GPIO (PCI int 1)              MPP13: GPIO (PCI int 2)
 338          * MPP14: NAND_REn[2]                   MPP15: NAND_WEn[2]
 339          * MPP16: UART1_RX                      MPP17: UART1_TX
 340          * MPP18: UART1_CTS                     MPP19: UART1_RTS
 341          * MPP-DEV: DEV_D[16:31]
 342          */
 343         orion_write(MPP_0_7_CTRL, 0x00222203);
 344         orion_write(MPP_8_15_CTRL, 0x44000000);
 345         orion_write(MPP_16_19_CTRL, 0);
 346         orion_write(MPP_DEV_CTRL, 0);
 347
 348         orion_gpio_set_valid_pins(0x00003fc3);
 349
 350         platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
 351         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
 352         orion_eth_init(&db88f5281_eth_data);
 353 }
 354
 355 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
 356         /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
 357         .phys_io        = ORION_REGS_BASE,
 358         .io_pg_offst    = ((ORION_REGS_BASE) >> 18) & 0xfffc,
 359         .boot_params    = 0x00000100,
 360         .init_machine   = db88f5281_init,
 361         .map_io         = orion_map_io,
 362         .init_irq       = orion_init_irq,
 363         .timer          = &orion_timer,
 364 MACHINE_END