2 * File: arch/blackfin/mach-common/ints-priority-dc.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2006 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
50 * - we have separated the physical Hardware interrupt from the
51 * levels that the LINUX kernel sees (see the description in irq.h)
55 /* Initialize this to an actual value to force it into the .data
56 * section so that we know it is properly initialized at entry into
57 * the kernel but before bss is initialized to zero (which is where
58 * it would live otherwise). The 0x1f magic represents the IRQs we
59 * cannot actually mask out in hardware.
61 unsigned long irq_flags
= 0x1f;
63 /* The number of spurious interrupts */
64 atomic_t num_spurious
;
67 /* irq number for request_irq, available in mach-bf561/irq.h */
69 /* corresponding bit in the SICA_ISR0 register */
71 /* corresponding bit in the SICA_ISR1 register */
73 } ivg_table
[NR_PERI_INTS
];
76 /* position of first irq in ivg_table for given ivg */
79 } ivg7_13
[IVG13
- IVG7
+ 1];
81 static void search_IAR(void);
84 * Search SIC_IAR and fill tables with the irqvalues
85 * and their positions in the SIC_ISR register.
87 static void __init
search_IAR(void)
89 unsigned ivg
, irq_pos
= 0;
90 for (ivg
= 0; ivg
<= IVG13
- IVG7
; ivg
++) {
93 ivg7_13
[ivg
].istop
= ivg7_13
[ivg
].ifirst
= &ivg_table
[irq_pos
];
95 for (irqn
= 0; irqn
< NR_PERI_INTS
; irqn
++) {
96 int iar_shift
= (irqn
& 7) * 4;
99 bfin_read32((unsigned long *)SICA_IAR0
+
100 (irqn
>> 3)) >> iar_shift
)) {
101 ivg_table
[irq_pos
].irqno
= IVG7
+ irqn
;
102 ivg_table
[irq_pos
].isrflag0
=
103 (irqn
< 32 ? (1 << irqn
) : 0);
104 ivg_table
[irq_pos
].isrflag1
=
105 (irqn
< 32 ? 0 : (1 << (irqn
- 32)));
106 ivg7_13
[ivg
].istop
++;
114 * This is for BF561 internal IRQs
117 static void ack_noop(unsigned int irq
)
119 /* Dummy function. */
122 static void bf561_core_mask_irq(unsigned int irq
)
124 irq_flags
&= ~(1 << irq
);
125 if (!irqs_disabled())
129 static void bf561_core_unmask_irq(unsigned int irq
)
131 irq_flags
|= 1 << irq
;
133 * If interrupts are enabled, IMASK must contain the same value
134 * as irq_flags. Make sure that invariant holds. If interrupts
135 * are currently disabled we need not do anything; one of the
136 * callers will take care of setting IMASK to the proper value
137 * when reenabling interrupts.
138 * local_irq_enable just does "STI irq_flags", so it's exactly
141 if (!irqs_disabled())
146 static void bf561_internal_mask_irq(unsigned int irq
)
148 unsigned long irq_mask
;
149 if ((irq
- (IRQ_CORETMR
+ 1)) < 32) {
150 irq_mask
= (1 << (irq
- (IRQ_CORETMR
+ 1)));
151 bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() & ~irq_mask
);
153 irq_mask
= (1 << (irq
- (IRQ_CORETMR
+ 1) - 32));
154 bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() & ~irq_mask
);
158 static void bf561_internal_unmask_irq(unsigned int irq
)
160 unsigned long irq_mask
;
162 if ((irq
- (IRQ_CORETMR
+ 1)) < 32) {
163 irq_mask
= (1 << (irq
- (IRQ_CORETMR
+ 1)));
164 bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() | irq_mask
);
166 irq_mask
= (1 << (irq
- (IRQ_CORETMR
+ 1) - 32));
167 bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() | irq_mask
);
172 static struct irq_chip bf561_core_irqchip
= {
174 .mask
= bf561_core_mask_irq
,
175 .unmask
= bf561_core_unmask_irq
,
178 static struct irq_chip bf561_internal_irqchip
= {
180 .mask
= bf561_internal_mask_irq
,
181 .unmask
= bf561_internal_unmask_irq
,
184 static unsigned short gpio_enabled
[gpio_bank(MAX_BLACKFIN_GPIOS
)];
185 static unsigned short gpio_edge_triggered
[gpio_bank(MAX_BLACKFIN_GPIOS
)];
187 static void bf561_gpio_ack_irq(unsigned int irq
)
189 u16 gpionr
= irq
- IRQ_PF0
;
191 if (gpio_edge_triggered
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)) {
192 set_gpio_data(gpionr
, 0);
197 static void bf561_gpio_mask_ack_irq(unsigned int irq
)
199 u16 gpionr
= irq
- IRQ_PF0
;
201 if (gpio_edge_triggered
[gpio_bank(gpionr
)] & gpio_bit(gpionr
)) {
202 set_gpio_data(gpionr
, 0);
206 set_gpio_maska(gpionr
, 0);
210 static void bf561_gpio_mask_irq(unsigned int irq
)
212 set_gpio_maska(irq
- IRQ_PF0
, 0);
216 static void bf561_gpio_unmask_irq(unsigned int irq
)
218 set_gpio_maska(irq
- IRQ_PF0
, 1);
222 static unsigned int bf561_gpio_irq_startup(unsigned int irq
)
226 u16 gpionr
= irq
- IRQ_PF0
;
228 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
))) {
229 snprintf(buf
, sizeof buf
, "IRQ %d", irq
);
230 ret
= gpio_request(gpionr
, buf
);
236 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
237 bf561_gpio_unmask_irq(irq
);
243 static void bf561_gpio_irq_shutdown(unsigned int irq
)
245 bf561_gpio_mask_irq(irq
);
246 gpio_free(irq
- IRQ_PF0
);
247 gpio_enabled
[gpio_bank(irq
- IRQ_PF0
)] &= ~gpio_bit(irq
- IRQ_PF0
);
250 static int bf561_gpio_irq_type(unsigned int irq
, unsigned int type
)
255 u16 gpionr
= irq
- IRQ_PF0
;
258 if (type
== IRQ_TYPE_PROBE
) {
259 /* only probe unenabled GPIO interrupt lines */
260 if (gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
))
262 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
266 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
267 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
269 if (!(gpio_enabled
[gpio_bank(gpionr
)] & gpio_bit(gpionr
))) {
270 snprintf(buf
, sizeof buf
, "IRQ %d", irq
);
271 ret
= gpio_request(gpionr
, buf
);
277 gpio_enabled
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
279 gpio_enabled
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
284 set_gpio_dir(gpionr
, 0);
285 set_gpio_inen(gpionr
, 1);
288 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
289 gpio_edge_triggered
[gpio_bank(gpionr
)] |= gpio_bit(gpionr
);
290 set_gpio_edge(gpionr
, 1);
292 set_gpio_edge(gpionr
, 0);
293 gpio_edge_triggered
[gpio_bank(gpionr
)] &= ~gpio_bit(gpionr
);
296 if ((type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
297 == (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
298 set_gpio_both(gpionr
, 1);
300 set_gpio_both(gpionr
, 0);
302 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
303 set_gpio_polar(gpionr
, 1); /* low or falling edge denoted by one */
305 set_gpio_polar(gpionr
, 0); /* high or rising edge denoted by zero */
309 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
310 set_irq_handler(irq
, handle_edge_irq
);
312 set_irq_handler(irq
, handle_level_irq
);
317 static struct irq_chip bf561_gpio_irqchip
= {
318 .ack
= bf561_gpio_ack_irq
,
319 .mask
= bf561_gpio_mask_irq
,
320 .mask_ack
= bf561_gpio_mask_ack_irq
,
321 .unmask
= bf561_gpio_unmask_irq
,
322 .set_type
= bf561_gpio_irq_type
,
323 .startup
= bf561_gpio_irq_startup
,
324 .shutdown
= bf561_gpio_irq_shutdown
327 static void bf561_demux_gpio_irq(unsigned int inta_irq
,
328 struct irq_desc
*intb_desc
)
330 int irq
, flag_d
, mask
;
348 gpio
= irq
- IRQ_PF0
;
350 flag_d
= get_gpiop_data(gpio
);
351 mask
= flag_d
& (gpio_enabled
[gpio_bank(gpio
)] &
352 get_gpiop_maska(gpio
));
356 struct irq_desc
*desc
= irq_desc
+ irq
;
357 desc
->handle_irq(irq
, desc
);
366 void __init
init_exception_vectors(void)
370 /* cannot program in software:
371 * evt0 - emulation (jtag)
374 bfin_write_EVT2(evt_nmi
);
375 bfin_write_EVT3(trap
);
376 bfin_write_EVT5(evt_ivhw
);
377 bfin_write_EVT6(evt_timer
);
378 bfin_write_EVT7(evt_evt7
);
379 bfin_write_EVT8(evt_evt8
);
380 bfin_write_EVT9(evt_evt9
);
381 bfin_write_EVT10(evt_evt10
);
382 bfin_write_EVT11(evt_evt11
);
383 bfin_write_EVT12(evt_evt12
);
384 bfin_write_EVT13(evt_evt13
);
385 bfin_write_EVT14(evt14_softirq
);
386 bfin_write_EVT15(evt_system_call
);
391 * This function should be called during kernel startup to initialize
392 * the BFin IRQ handling routines.
394 int __init
init_arch_irq(void)
397 unsigned long ilat
= 0;
398 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
399 bfin_write_SICA_IMASK0(SIC_UNMASK_ALL
);
400 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL
);
403 bfin_write_SICA_IWR0(IWR_ENABLE_ALL
);
404 bfin_write_SICA_IWR1(IWR_ENABLE_ALL
);
408 init_exception_buff();
410 for (irq
= 0; irq
<= SYS_IRQS
; irq
++) {
411 if (irq
<= IRQ_CORETMR
)
412 set_irq_chip(irq
, &bf561_core_irqchip
);
414 set_irq_chip(irq
, &bf561_internal_irqchip
);
416 if ((irq
!= IRQ_PROG0_INTA
) &&
417 (irq
!= IRQ_PROG1_INTA
) &&
418 (irq
!= IRQ_PROG2_INTA
))
419 set_irq_handler(irq
, handle_simple_irq
);
421 set_irq_chained_handler(irq
, bf561_demux_gpio_irq
);
424 for (irq
= IRQ_PF0
; irq
<= IRQ_PF47
; irq
++) {
425 set_irq_chip(irq
, &bf561_gpio_irqchip
);
426 /* if configured as edge, then will be changed to do_edge_IRQ */
427 set_irq_handler(irq
, handle_level_irq
);
432 ilat
= bfin_read_ILAT();
434 bfin_write_ILAT(ilat
);
437 printk(KERN_INFO
"Configuring Blackfin Priority Driven Interrupts\n");
438 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
442 /* Therefore it's better to setup IARs before interrupts enabled */
445 /* Enable interrupts IVG7-15 */
446 irq_flags
= irq_flags
| IMASK_IVG15
|
447 IMASK_IVG14
| IMASK_IVG13
| IMASK_IVG12
| IMASK_IVG11
|
448 IMASK_IVG10
| IMASK_IVG9
| IMASK_IVG8
| IMASK_IVG7
| IMASK_IVGHW
;
453 #ifdef CONFIG_DO_IRQ_L1
454 __attribute__((l1_text
))
456 void do_irq(int vec
, struct pt_regs
*fp
)
458 if (vec
== EVT_IVTMR_P
) {
461 struct ivgx
*ivg
= ivg7_13
[vec
- IVG7
].ifirst
;
462 struct ivgx
*ivg_stop
= ivg7_13
[vec
- IVG7
].istop
;
463 unsigned long sic_status0
, sic_status1
;
466 sic_status0
= bfin_read_SICA_IMASK0() & bfin_read_SICA_ISR0();
467 sic_status1
= bfin_read_SICA_IMASK1() & bfin_read_SICA_ISR1();
470 if (ivg
>= ivg_stop
) {
471 atomic_inc(&num_spurious
);
473 } else if ((sic_status0
& ivg
->isrflag0
) ||
474 (sic_status1
& ivg
->isrflag1
))
482 kgdb_process_breakpoint();