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oom: suppress extraneous stack and memory dump
[wrt350n-kernel.git] / drivers / kvm / x86_emulate.c
blob9737c3b2f48c1a2006cd6420ce192f04a323c7e3
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf( _f , ## _a )
27 #else
28 #include "kvm.h"
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include "x86_emulate.h"
32 #include <linux/module.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65
66 static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 SrcImmByte, SrcImm, 0, 0,
87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 /* 0x50 - 0x57 */
102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
107 /* 0x60 - 0x67 */
108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
129 /* 0x90 - 0x9F */
130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165 };
166
167 static u16 twobyte_table[256] = {
168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
170 0, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
203 /* 0xA8 - 0xAF */
204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
207 DstMem | SrcReg | ModRM | BitOp,
208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
215 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0xD0 - 0xDF */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
218 /* 0xE0 - 0xEF */
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
220 /* 0xF0 - 0xFF */
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
222 };
223
224 /* Type, address-of, and value of an instruction's operand. */
225 struct operand {
226 enum { OP_REG, OP_MEM, OP_IMM } type;
227 unsigned int bytes;
228 unsigned long val, orig_val, *ptr;
229 };
230
231 /* EFLAGS bit definitions. */
232 #define EFLG_OF (1<<11)
233 #define EFLG_DF (1<<10)
234 #define EFLG_SF (1<<7)
235 #define EFLG_ZF (1<<6)
236 #define EFLG_AF (1<<4)
237 #define EFLG_PF (1<<2)
238 #define EFLG_CF (1<<0)
239
240 /*
241 * Instruction emulation:
242 * Most instructions are emulated directly via a fragment of inline assembly
243 * code. This allows us to save/restore EFLAGS and thus very easily pick up
244 * any modified flags.
245 */
246
247 #if defined(CONFIG_X86_64)
248 #define _LO32 "k" /* force 32-bit operand */
249 #define _STK "%%rsp" /* stack pointer */
250 #elif defined(__i386__)
251 #define _LO32 "" /* force 32-bit operand */
252 #define _STK "%%esp" /* stack pointer */
253 #endif
254
255 /*
256 * These EFLAGS bits are restored from saved value during emulation, and
257 * any changes are written back to the saved value after emulation.
258 */
259 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
260
261 /* Before executing instruction: restore necessary bits in EFLAGS. */
262 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
263 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
264 "push %"_sav"; " \
265 "movl %"_msk",%"_LO32 _tmp"; " \
266 "andl %"_LO32 _tmp",("_STK"); " \
267 "pushf; " \
268 "notl %"_LO32 _tmp"; " \
269 "andl %"_LO32 _tmp",("_STK"); " \
270 "pop %"_tmp"; " \
271 "orl %"_LO32 _tmp",("_STK"); " \
272 "popf; " \
273 /* _sav &= ~msk; */ \
274 "movl %"_msk",%"_LO32 _tmp"; " \
275 "notl %"_LO32 _tmp"; " \
276 "andl %"_LO32 _tmp",%"_sav"; "
277
278 /* After executing instruction: write-back necessary bits in EFLAGS. */
279 #define _POST_EFLAGS(_sav, _msk, _tmp) \
280 /* _sav |= EFLAGS & _msk; */ \
281 "pushf; " \
282 "pop %"_tmp"; " \
283 "andl %"_msk",%"_LO32 _tmp"; " \
284 "orl %"_LO32 _tmp",%"_sav"; "
285
286 /* Raw emulation: instruction has two explicit operands. */
287 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
288 do { \
289 unsigned long _tmp; \
290 \
291 switch ((_dst).bytes) { \
292 case 2: \
293 __asm__ __volatile__ ( \
294 _PRE_EFLAGS("0","4","2") \
295 _op"w %"_wx"3,%1; " \
296 _POST_EFLAGS("0","4","2") \
297 : "=m" (_eflags), "=m" ((_dst).val), \
298 "=&r" (_tmp) \
299 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
300 break; \
301 case 4: \
302 __asm__ __volatile__ ( \
303 _PRE_EFLAGS("0","4","2") \
304 _op"l %"_lx"3,%1; " \
305 _POST_EFLAGS("0","4","2") \
306 : "=m" (_eflags), "=m" ((_dst).val), \
307 "=&r" (_tmp) \
308 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
309 break; \
310 case 8: \
311 __emulate_2op_8byte(_op, _src, _dst, \
312 _eflags, _qx, _qy); \
313 break; \
314 } \
315 } while (0)
316
317 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
318 do { \
319 unsigned long _tmp; \
320 switch ( (_dst).bytes ) \
321 { \
322 case 1: \
323 __asm__ __volatile__ ( \
324 _PRE_EFLAGS("0","4","2") \
325 _op"b %"_bx"3,%1; " \
326 _POST_EFLAGS("0","4","2") \
327 : "=m" (_eflags), "=m" ((_dst).val), \
328 "=&r" (_tmp) \
329 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
330 break; \
331 default: \
332 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
333 _wx, _wy, _lx, _ly, _qx, _qy); \
334 break; \
335 } \
336 } while (0)
337
338 /* Source operand is byte-sized and may be restricted to just %cl. */
339 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
340 __emulate_2op(_op, _src, _dst, _eflags, \
341 "b", "c", "b", "c", "b", "c", "b", "c")
342
343 /* Source operand is byte, word, long or quad sized. */
344 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
345 __emulate_2op(_op, _src, _dst, _eflags, \
346 "b", "q", "w", "r", _LO32, "r", "", "r")
347
348 /* Source operand is word, long or quad sized. */
349 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
350 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
351 "w", "r", _LO32, "r", "", "r")
352
353 /* Instruction has only one explicit operand (no source operand). */
354 #define emulate_1op(_op, _dst, _eflags) \
355 do { \
356 unsigned long _tmp; \
357 \
358 switch ( (_dst).bytes ) \
359 { \
360 case 1: \
361 __asm__ __volatile__ ( \
362 _PRE_EFLAGS("0","3","2") \
363 _op"b %1; " \
364 _POST_EFLAGS("0","3","2") \
365 : "=m" (_eflags), "=m" ((_dst).val), \
366 "=&r" (_tmp) \
367 : "i" (EFLAGS_MASK) ); \
368 break; \
369 case 2: \
370 __asm__ __volatile__ ( \
371 _PRE_EFLAGS("0","3","2") \
372 _op"w %1; " \
373 _POST_EFLAGS("0","3","2") \
374 : "=m" (_eflags), "=m" ((_dst).val), \
375 "=&r" (_tmp) \
376 : "i" (EFLAGS_MASK) ); \
377 break; \
378 case 4: \
379 __asm__ __volatile__ ( \
380 _PRE_EFLAGS("0","3","2") \
381 _op"l %1; " \
382 _POST_EFLAGS("0","3","2") \
383 : "=m" (_eflags), "=m" ((_dst).val), \
384 "=&r" (_tmp) \
385 : "i" (EFLAGS_MASK) ); \
386 break; \
387 case 8: \
388 __emulate_1op_8byte(_op, _dst, _eflags); \
389 break; \
390 } \
391 } while (0)
392
393 /* Emulate an instruction with quadword operands (x86/64 only). */
394 #if defined(CONFIG_X86_64)
395 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
396 do { \
397 __asm__ __volatile__ ( \
398 _PRE_EFLAGS("0","4","2") \
399 _op"q %"_qx"3,%1; " \
400 _POST_EFLAGS("0","4","2") \
401 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
402 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
403 } while (0)
404
405 #define __emulate_1op_8byte(_op, _dst, _eflags) \
406 do { \
407 __asm__ __volatile__ ( \
408 _PRE_EFLAGS("0","3","2") \
409 _op"q %1; " \
410 _POST_EFLAGS("0","3","2") \
411 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
412 : "i" (EFLAGS_MASK) ); \
413 } while (0)
414
415 #elif defined(__i386__)
416 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
417 #define __emulate_1op_8byte(_op, _dst, _eflags)
418 #endif /* __i386__ */
419
420 /* Fetch next part of the instruction being emulated. */
421 #define insn_fetch(_type, _size, _eip) \
422 ({ unsigned long _x; \
423 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
424 (_size), ctxt->vcpu); \
425 if ( rc != 0 ) \
426 goto done; \
427 (_eip) += (_size); \
428 (_type)_x; \
429 })
430
431 /* Access/update address held in a register, based on addressing mode. */
432 #define address_mask(reg) \
433 ((ad_bytes == sizeof(unsigned long)) ? \
434 (reg) : ((reg) & ((1UL << (ad_bytes << 3)) - 1)))
435 #define register_address(base, reg) \
436 ((base) + address_mask(reg))
437 #define register_address_increment(reg, inc) \
438 do { \
439 /* signed type ensures sign extension to long */ \
440 int _inc = (inc); \
441 if ( ad_bytes == sizeof(unsigned long) ) \
442 (reg) += _inc; \
443 else \
444 (reg) = ((reg) & ~((1UL << (ad_bytes << 3)) - 1)) | \
445 (((reg) + _inc) & ((1UL << (ad_bytes << 3)) - 1)); \
446 } while (0)
447
448 #define JMP_REL(rel) \
449 do { \
450 _eip += (int)(rel); \
451 _eip = ((op_bytes == 2) ? (uint16_t)_eip : (uint32_t)_eip); \
452 } while (0)
453
454 /*
455 * Given the 'reg' portion of a ModRM byte, and a register block, return a
456 * pointer into the block that addresses the relevant register.
457 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
458 */
459 static void *decode_register(u8 modrm_reg, unsigned long *regs,
460 int highbyte_regs)
461 {
462 void *p;
463
464 p = &regs[modrm_reg];
465 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
466 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
467 return p;
468 }
469
470 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
471 struct x86_emulate_ops *ops,
472 void *ptr,
473 u16 *size, unsigned long *address, int op_bytes)
474 {
475 int rc;
476
477 if (op_bytes == 2)
478 op_bytes = 3;
479 *address = 0;
480 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
481 ctxt->vcpu);
482 if (rc)
483 return rc;
484 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
485 ctxt->vcpu);
486 return rc;
487 }
488
489 static int test_cc(unsigned int condition, unsigned int flags)
490 {
491 int rc = 0;
492
493 switch ((condition & 15) >> 1) {
494 case 0: /* o */
495 rc |= (flags & EFLG_OF);
496 break;
497 case 1: /* b/c/nae */
498 rc |= (flags & EFLG_CF);
499 break;
500 case 2: /* z/e */
501 rc |= (flags & EFLG_ZF);
502 break;
503 case 3: /* be/na */
504 rc |= (flags & (EFLG_CF|EFLG_ZF));
505 break;
506 case 4: /* s */
507 rc |= (flags & EFLG_SF);
508 break;
509 case 5: /* p/pe */
510 rc |= (flags & EFLG_PF);
511 break;
512 case 7: /* le/ng */
513 rc |= (flags & EFLG_ZF);
514 /* fall through */
515 case 6: /* l/nge */
516 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
517 break;
518 }
519
520 /* Odd condition identifiers (lsb == 1) have inverted sense. */
521 return (!!rc ^ (condition & 1));
522 }
523
524 int
525 x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
526 {
527 unsigned d;
528 u8 b, sib, twobyte = 0, rex_prefix = 0;
529 u8 modrm, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
530 unsigned long *override_base = NULL;
531 unsigned int op_bytes, ad_bytes, lock_prefix = 0, rep_prefix = 0, i;
532 int rc = 0;
533 struct operand src, dst;
534 unsigned long cr2 = ctxt->cr2;
535 int mode = ctxt->mode;
536 unsigned long modrm_ea;
537 int use_modrm_ea, index_reg = 0, base_reg = 0, scale, rip_relative = 0;
538 int no_wb = 0;
539 u64 msr_data;
540
541 /* Shadow copy of register state. Committed on successful emulation. */
542 unsigned long _regs[NR_VCPU_REGS];
543 unsigned long _eip = ctxt->vcpu->rip, _eflags = ctxt->eflags;
544 unsigned long modrm_val = 0;
545
546 memcpy(_regs, ctxt->vcpu->regs, sizeof _regs);
547
548 switch (mode) {
549 case X86EMUL_MODE_REAL:
550 case X86EMUL_MODE_PROT16:
551 op_bytes = ad_bytes = 2;
552 break;
553 case X86EMUL_MODE_PROT32:
554 op_bytes = ad_bytes = 4;
555 break;
556 #ifdef CONFIG_X86_64
557 case X86EMUL_MODE_PROT64:
558 op_bytes = 4;
559 ad_bytes = 8;
560 break;
561 #endif
562 default:
563 return -1;
564 }
565
566 /* Legacy prefixes. */
567 for (i = 0; i < 8; i++) {
568 switch (b = insn_fetch(u8, 1, _eip)) {
569 case 0x66: /* operand-size override */
570 op_bytes ^= 6; /* switch between 2/4 bytes */
571 break;
572 case 0x67: /* address-size override */
573 if (mode == X86EMUL_MODE_PROT64)
574 ad_bytes ^= 12; /* switch between 4/8 bytes */
575 else
576 ad_bytes ^= 6; /* switch between 2/4 bytes */
577 break;
578 case 0x2e: /* CS override */
579 override_base = &ctxt->cs_base;
580 break;
581 case 0x3e: /* DS override */
582 override_base = &ctxt->ds_base;
583 break;
584 case 0x26: /* ES override */
585 override_base = &ctxt->es_base;
586 break;
587 case 0x64: /* FS override */
588 override_base = &ctxt->fs_base;
589 break;
590 case 0x65: /* GS override */
591 override_base = &ctxt->gs_base;
592 break;
593 case 0x36: /* SS override */
594 override_base = &ctxt->ss_base;
595 break;
596 case 0xf0: /* LOCK */
597 lock_prefix = 1;
598 break;
599 case 0xf3: /* REP/REPE/REPZ */
600 rep_prefix = 1;
601 break;
602 case 0xf2: /* REPNE/REPNZ */
603 break;
604 default:
605 goto done_prefixes;
606 }
607 }
608
609 done_prefixes:
610
611 /* REX prefix. */
612 if ((mode == X86EMUL_MODE_PROT64) && ((b & 0xf0) == 0x40)) {
613 rex_prefix = b;
614 if (b & 8)
615 op_bytes = 8; /* REX.W */
616 modrm_reg = (b & 4) << 1; /* REX.R */
617 index_reg = (b & 2) << 2; /* REX.X */
618 modrm_rm = base_reg = (b & 1) << 3; /* REG.B */
619 b = insn_fetch(u8, 1, _eip);
620 }
621
622 /* Opcode byte(s). */
623 d = opcode_table[b];
624 if (d == 0) {
625 /* Two-byte opcode? */
626 if (b == 0x0f) {
627 twobyte = 1;
628 b = insn_fetch(u8, 1, _eip);
629 d = twobyte_table[b];
630 }
631
632 /* Unrecognised? */
633 if (d == 0)
634 goto cannot_emulate;
635 }
636
637 /* ModRM and SIB bytes. */
638 if (d & ModRM) {
639 modrm = insn_fetch(u8, 1, _eip);
640 modrm_mod |= (modrm & 0xc0) >> 6;
641 modrm_reg |= (modrm & 0x38) >> 3;
642 modrm_rm |= (modrm & 0x07);
643 modrm_ea = 0;
644 use_modrm_ea = 1;
645
646 if (modrm_mod == 3) {
647 modrm_val = *(unsigned long *)
648 decode_register(modrm_rm, _regs, d & ByteOp);
649 goto modrm_done;
650 }
651
652 if (ad_bytes == 2) {
653 unsigned bx = _regs[VCPU_REGS_RBX];
654 unsigned bp = _regs[VCPU_REGS_RBP];
655 unsigned si = _regs[VCPU_REGS_RSI];
656 unsigned di = _regs[VCPU_REGS_RDI];
657
658 /* 16-bit ModR/M decode. */
659 switch (modrm_mod) {
660 case 0:
661 if (modrm_rm == 6)
662 modrm_ea += insn_fetch(u16, 2, _eip);
663 break;
664 case 1:
665 modrm_ea += insn_fetch(s8, 1, _eip);
666 break;
667 case 2:
668 modrm_ea += insn_fetch(u16, 2, _eip);
669 break;
670 }
671 switch (modrm_rm) {
672 case 0:
673 modrm_ea += bx + si;
674 break;
675 case 1:
676 modrm_ea += bx + di;
677 break;
678 case 2:
679 modrm_ea += bp + si;
680 break;
681 case 3:
682 modrm_ea += bp + di;
683 break;
684 case 4:
685 modrm_ea += si;
686 break;
687 case 5:
688 modrm_ea += di;
689 break;
690 case 6:
691 if (modrm_mod != 0)
692 modrm_ea += bp;
693 break;
694 case 7:
695 modrm_ea += bx;
696 break;
697 }
698 if (modrm_rm == 2 || modrm_rm == 3 ||
699 (modrm_rm == 6 && modrm_mod != 0))
700 if (!override_base)
701 override_base = &ctxt->ss_base;
702 modrm_ea = (u16)modrm_ea;
703 } else {
704 /* 32/64-bit ModR/M decode. */
705 switch (modrm_rm) {
706 case 4:
707 case 12:
708 sib = insn_fetch(u8, 1, _eip);
709 index_reg |= (sib >> 3) & 7;
710 base_reg |= sib & 7;
711 scale = sib >> 6;
712
713 switch (base_reg) {
714 case 5:
715 if (modrm_mod != 0)
716 modrm_ea += _regs[base_reg];
717 else
718 modrm_ea += insn_fetch(s32, 4, _eip);
719 break;
720 default:
721 modrm_ea += _regs[base_reg];
722 }
723 switch (index_reg) {
724 case 4:
725 break;
726 default:
727 modrm_ea += _regs[index_reg] << scale;
728
729 }
730 break;
731 case 5:
732 if (modrm_mod != 0)
733 modrm_ea += _regs[modrm_rm];
734 else if (mode == X86EMUL_MODE_PROT64)
735 rip_relative = 1;
736 break;
737 default:
738 modrm_ea += _regs[modrm_rm];
739 break;
740 }
741 switch (modrm_mod) {
742 case 0:
743 if (modrm_rm == 5)
744 modrm_ea += insn_fetch(s32, 4, _eip);
745 break;
746 case 1:
747 modrm_ea += insn_fetch(s8, 1, _eip);
748 break;
749 case 2:
750 modrm_ea += insn_fetch(s32, 4, _eip);
751 break;
752 }
753 }
754 if (!override_base)
755 override_base = &ctxt->ds_base;
756 if (mode == X86EMUL_MODE_PROT64 &&
757 override_base != &ctxt->fs_base &&
758 override_base != &ctxt->gs_base)
759 override_base = NULL;
760
761 if (override_base)
762 modrm_ea += *override_base;
763
764 if (rip_relative) {
765 modrm_ea += _eip;
766 switch (d & SrcMask) {
767 case SrcImmByte:
768 modrm_ea += 1;
769 break;
770 case SrcImm:
771 if (d & ByteOp)
772 modrm_ea += 1;
773 else
774 if (op_bytes == 8)
775 modrm_ea += 4;
776 else
777 modrm_ea += op_bytes;
778 }
779 }
780 if (ad_bytes != 8)
781 modrm_ea = (u32)modrm_ea;
782 cr2 = modrm_ea;
783 modrm_done:
784 ;
785 }
786
787 /*
788 * Decode and fetch the source operand: register, memory
789 * or immediate.
790 */
791 switch (d & SrcMask) {
792 case SrcNone:
793 break;
794 case SrcReg:
795 src.type = OP_REG;
796 if (d & ByteOp) {
797 src.ptr = decode_register(modrm_reg, _regs,
798 (rex_prefix == 0));
799 src.val = src.orig_val = *(u8 *) src.ptr;
800 src.bytes = 1;
801 } else {
802 src.ptr = decode_register(modrm_reg, _regs, 0);
803 switch ((src.bytes = op_bytes)) {
804 case 2:
805 src.val = src.orig_val = *(u16 *) src.ptr;
806 break;
807 case 4:
808 src.val = src.orig_val = *(u32 *) src.ptr;
809 break;
810 case 8:
811 src.val = src.orig_val = *(u64 *) src.ptr;
812 break;
813 }
814 }
815 break;
816 case SrcMem16:
817 src.bytes = 2;
818 goto srcmem_common;
819 case SrcMem32:
820 src.bytes = 4;
821 goto srcmem_common;
822 case SrcMem:
823 src.bytes = (d & ByteOp) ? 1 : op_bytes;
824 /* Don't fetch the address for invlpg: it could be unmapped. */
825 if (twobyte && b == 0x01 && modrm_reg == 7)
826 break;
827 srcmem_common:
828 src.type = OP_MEM;
829 src.ptr = (unsigned long *)cr2;
830 src.val = 0;
831 if ((rc = ops->read_emulated((unsigned long)src.ptr,
832 &src.val, src.bytes, ctxt->vcpu)) != 0)
833 goto done;
834 src.orig_val = src.val;
835 break;
836 case SrcImm:
837 src.type = OP_IMM;
838 src.ptr = (unsigned long *)_eip;
839 src.bytes = (d & ByteOp) ? 1 : op_bytes;
840 if (src.bytes == 8)
841 src.bytes = 4;
842 /* NB. Immediates are sign-extended as necessary. */
843 switch (src.bytes) {
844 case 1:
845 src.val = insn_fetch(s8, 1, _eip);
846 break;
847 case 2:
848 src.val = insn_fetch(s16, 2, _eip);
849 break;
850 case 4:
851 src.val = insn_fetch(s32, 4, _eip);
852 break;
853 }
854 break;
855 case SrcImmByte:
856 src.type = OP_IMM;
857 src.ptr = (unsigned long *)_eip;
858 src.bytes = 1;
859 src.val = insn_fetch(s8, 1, _eip);
860 break;
861 }
862
863 /* Decode and fetch the destination operand: register or memory. */
864 switch (d & DstMask) {
865 case ImplicitOps:
866 /* Special instructions do their own operand decoding. */
867 goto special_insn;
868 case DstReg:
869 dst.type = OP_REG;
870 if ((d & ByteOp)
871 && !(twobyte && (b == 0xb6 || b == 0xb7))) {
872 dst.ptr = decode_register(modrm_reg, _regs,
873 (rex_prefix == 0));
874 dst.val = *(u8 *) dst.ptr;
875 dst.bytes = 1;
876 } else {
877 dst.ptr = decode_register(modrm_reg, _regs, 0);
878 switch ((dst.bytes = op_bytes)) {
879 case 2:
880 dst.val = *(u16 *)dst.ptr;
881 break;
882 case 4:
883 dst.val = *(u32 *)dst.ptr;
884 break;
885 case 8:
886 dst.val = *(u64 *)dst.ptr;
887 break;
888 }
889 }
890 break;
891 case DstMem:
892 dst.type = OP_MEM;
893 dst.ptr = (unsigned long *)cr2;
894 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
895 dst.val = 0;
896 if (d & BitOp) {
897 unsigned long mask = ~(dst.bytes * 8 - 1);
898
899 dst.ptr = (void *)dst.ptr + (src.val & mask) / 8;
900 }
901 if (!(d & Mov) && /* optimisation - avoid slow emulated read */
902 ((rc = ops->read_emulated((unsigned long)dst.ptr,
903 &dst.val, dst.bytes, ctxt->vcpu)) != 0))
904 goto done;
905 break;
906 }
907 dst.orig_val = dst.val;
908
909 if (twobyte)
910 goto twobyte_insn;
911
912 switch (b) {
913 case 0x00 ... 0x05:
914 add: /* add */
915 emulate_2op_SrcV("add", src, dst, _eflags);
916 break;
917 case 0x08 ... 0x0d:
918 or: /* or */
919 emulate_2op_SrcV("or", src, dst, _eflags);
920 break;
921 case 0x10 ... 0x15:
922 adc: /* adc */
923 emulate_2op_SrcV("adc", src, dst, _eflags);
924 break;
925 case 0x18 ... 0x1d:
926 sbb: /* sbb */
927 emulate_2op_SrcV("sbb", src, dst, _eflags);
928 break;
929 case 0x20 ... 0x23:
930 and: /* and */
931 emulate_2op_SrcV("and", src, dst, _eflags);
932 break;
933 case 0x24: /* and al imm8 */
934 dst.type = OP_REG;
935 dst.ptr = &_regs[VCPU_REGS_RAX];
936 dst.val = *(u8 *)dst.ptr;
937 dst.bytes = 1;
938 dst.orig_val = dst.val;
939 goto and;
940 case 0x25: /* and ax imm16, or eax imm32 */
941 dst.type = OP_REG;
942 dst.bytes = op_bytes;
943 dst.ptr = &_regs[VCPU_REGS_RAX];
944 if (op_bytes == 2)
945 dst.val = *(u16 *)dst.ptr;
946 else
947 dst.val = *(u32 *)dst.ptr;
948 dst.orig_val = dst.val;
949 goto and;
950 case 0x28 ... 0x2d:
951 sub: /* sub */
952 emulate_2op_SrcV("sub", src, dst, _eflags);
953 break;
954 case 0x30 ... 0x35:
955 xor: /* xor */
956 emulate_2op_SrcV("xor", src, dst, _eflags);
957 break;
958 case 0x38 ... 0x3d:
959 cmp: /* cmp */
960 emulate_2op_SrcV("cmp", src, dst, _eflags);
961 break;
962 case 0x63: /* movsxd */
963 if (mode != X86EMUL_MODE_PROT64)
964 goto cannot_emulate;
965 dst.val = (s32) src.val;
966 break;
967 case 0x6a: /* push imm8 */
968 src.val = 0L;
969 src.val = insn_fetch(s8, 1, _eip);
970 push:
971 dst.type = OP_MEM;
972 dst.bytes = op_bytes;
973 dst.val = src.val;
974 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
975 dst.ptr = (void *) register_address(ctxt->ss_base,
976 _regs[VCPU_REGS_RSP]);
977 break;
978 case 0x80 ... 0x83: /* Grp1 */
979 switch (modrm_reg) {
980 case 0:
981 goto add;
982 case 1:
983 goto or;
984 case 2:
985 goto adc;
986 case 3:
987 goto sbb;
988 case 4:
989 goto and;
990 case 5:
991 goto sub;
992 case 6:
993 goto xor;
994 case 7:
995 goto cmp;
996 }
997 break;
998 case 0x84 ... 0x85:
999 test: /* test */
1000 emulate_2op_SrcV("test", src, dst, _eflags);
1001 break;
1002 case 0x86 ... 0x87: /* xchg */
1003 /* Write back the register source. */
1004 switch (dst.bytes) {
1005 case 1:
1006 *(u8 *) src.ptr = (u8) dst.val;
1007 break;
1008 case 2:
1009 *(u16 *) src.ptr = (u16) dst.val;
1010 break;
1011 case 4:
1012 *src.ptr = (u32) dst.val;
1013 break; /* 64b reg: zero-extend */
1014 case 8:
1015 *src.ptr = dst.val;
1016 break;
1017 }
1018 /*
1019 * Write back the memory destination with implicit LOCK
1020 * prefix.
1021 */
1022 dst.val = src.val;
1023 lock_prefix = 1;
1024 break;
1025 case 0x88 ... 0x8b: /* mov */
1026 goto mov;
1027 case 0x8d: /* lea r16/r32, m */
1028 dst.val = modrm_val;
1029 break;
1030 case 0x8f: /* pop (sole member of Grp1a) */
1031 /* 64-bit mode: POP always pops a 64-bit operand. */
1032 if (mode == X86EMUL_MODE_PROT64)
1033 dst.bytes = 8;
1034 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1035 _regs[VCPU_REGS_RSP]),
1036 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1037 goto done;
1038 register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
1039 break;
1040 case 0xa0 ... 0xa1: /* mov */
1041 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1042 dst.val = src.val;
1043 _eip += ad_bytes; /* skip src displacement */
1044 break;
1045 case 0xa2 ... 0xa3: /* mov */
1046 dst.val = (unsigned long)_regs[VCPU_REGS_RAX];
1047 _eip += ad_bytes; /* skip dst displacement */
1048 break;
1049 case 0xc0 ... 0xc1:
1050 grp2: /* Grp2 */
1051 switch (modrm_reg) {
1052 case 0: /* rol */
1053 emulate_2op_SrcB("rol", src, dst, _eflags);
1054 break;
1055 case 1: /* ror */
1056 emulate_2op_SrcB("ror", src, dst, _eflags);
1057 break;
1058 case 2: /* rcl */
1059 emulate_2op_SrcB("rcl", src, dst, _eflags);
1060 break;
1061 case 3: /* rcr */
1062 emulate_2op_SrcB("rcr", src, dst, _eflags);
1063 break;
1064 case 4: /* sal/shl */
1065 case 6: /* sal/shl */
1066 emulate_2op_SrcB("sal", src, dst, _eflags);
1067 break;
1068 case 5: /* shr */
1069 emulate_2op_SrcB("shr", src, dst, _eflags);
1070 break;
1071 case 7: /* sar */
1072 emulate_2op_SrcB("sar", src, dst, _eflags);
1073 break;
1074 }
1075 break;
1076 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1077 mov:
1078 dst.val = src.val;
1079 break;
1080 case 0xd0 ... 0xd1: /* Grp2 */
1081 src.val = 1;
1082 goto grp2;
1083 case 0xd2 ... 0xd3: /* Grp2 */
1084 src.val = _regs[VCPU_REGS_RCX];
1085 goto grp2;
1086 case 0xe8: /* call (near) */ {
1087 long int rel;
1088 switch (op_bytes) {
1089 case 2:
1090 rel = insn_fetch(s16, 2, _eip);
1091 break;
1092 case 4:
1093 rel = insn_fetch(s32, 4, _eip);
1094 break;
1095 case 8:
1096 rel = insn_fetch(s64, 8, _eip);
1097 break;
1098 default:
1099 DPRINTF("Call: Invalid op_bytes\n");
1100 goto cannot_emulate;
1101 }
1102 src.val = (unsigned long) _eip;
1103 JMP_REL(rel);
1104 goto push;
1105 }
1106 case 0xe9: /* jmp rel */
1107 case 0xeb: /* jmp rel short */
1108 JMP_REL(src.val);
1109 no_wb = 1; /* Disable writeback. */
1110 break;
1111 case 0xf6 ... 0xf7: /* Grp3 */
1112 switch (modrm_reg) {
1113 case 0 ... 1: /* test */
1114 /*
1115 * Special case in Grp3: test has an immediate
1116 * source operand.
1117 */
1118 src.type = OP_IMM;
1119 src.ptr = (unsigned long *)_eip;
1120 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1121 if (src.bytes == 8)
1122 src.bytes = 4;
1123 switch (src.bytes) {
1124 case 1:
1125 src.val = insn_fetch(s8, 1, _eip);
1126 break;
1127 case 2:
1128 src.val = insn_fetch(s16, 2, _eip);
1129 break;
1130 case 4:
1131 src.val = insn_fetch(s32, 4, _eip);
1132 break;
1133 }
1134 goto test;
1135 case 2: /* not */
1136 dst.val = ~dst.val;
1137 break;
1138 case 3: /* neg */
1139 emulate_1op("neg", dst, _eflags);
1140 break;
1141 default:
1142 goto cannot_emulate;
1143 }
1144 break;
1145 case 0xfe ... 0xff: /* Grp4/Grp5 */
1146 switch (modrm_reg) {
1147 case 0: /* inc */
1148 emulate_1op("inc", dst, _eflags);
1149 break;
1150 case 1: /* dec */
1151 emulate_1op("dec", dst, _eflags);
1152 break;
1153 case 4: /* jmp abs */
1154 if (b == 0xff)
1155 _eip = dst.val;
1156 else
1157 goto cannot_emulate;
1158 break;
1159 case 6: /* push */
1160 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1161 if (mode == X86EMUL_MODE_PROT64) {
1162 dst.bytes = 8;
1163 if ((rc = ops->read_std((unsigned long)dst.ptr,
1164 &dst.val, 8,
1165 ctxt->vcpu)) != 0)
1166 goto done;
1167 }
1168 register_address_increment(_regs[VCPU_REGS_RSP],
1169 -dst.bytes);
1170 if ((rc = ops->write_std(
1171 register_address(ctxt->ss_base,
1172 _regs[VCPU_REGS_RSP]),
1173 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1174 goto done;
1175 no_wb = 1;
1176 break;
1177 default:
1178 goto cannot_emulate;
1179 }
1180 break;
1181 }
1182
1183 writeback:
1184 if (!no_wb) {
1185 switch (dst.type) {
1186 case OP_REG:
1187 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1188 switch (dst.bytes) {
1189 case 1:
1190 *(u8 *)dst.ptr = (u8)dst.val;
1191 break;
1192 case 2:
1193 *(u16 *)dst.ptr = (u16)dst.val;
1194 break;
1195 case 4:
1196 *dst.ptr = (u32)dst.val;
1197 break; /* 64b: zero-ext */
1198 case 8:
1199 *dst.ptr = dst.val;
1200 break;
1201 }
1202 break;
1203 case OP_MEM:
1204 if (lock_prefix)
1205 rc = ops->cmpxchg_emulated((unsigned long)dst.
1206 ptr, &dst.orig_val,
1207 &dst.val, dst.bytes,
1208 ctxt->vcpu);
1209 else
1210 rc = ops->write_emulated((unsigned long)dst.ptr,
1211 &dst.val, dst.bytes,
1212 ctxt->vcpu);
1213 if (rc != 0)
1214 goto done;
1215 default:
1216 break;
1217 }
1218 }
1219
1220 /* Commit shadow register state. */
1221 memcpy(ctxt->vcpu->regs, _regs, sizeof _regs);
1222 ctxt->eflags = _eflags;
1223 ctxt->vcpu->rip = _eip;
1224
1225 done:
1226 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1227
1228 special_insn:
1229 if (twobyte)
1230 goto twobyte_special_insn;
1231 switch(b) {
1232 case 0x50 ... 0x57: /* push reg */
1233 if (op_bytes == 2)
1234 src.val = (u16) _regs[b & 0x7];
1235 else
1236 src.val = (u32) _regs[b & 0x7];
1237 dst.type = OP_MEM;
1238 dst.bytes = op_bytes;
1239 dst.val = src.val;
1240 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
1241 dst.ptr = (void *) register_address(
1242 ctxt->ss_base, _regs[VCPU_REGS_RSP]);
1243 break;
1244 case 0x58 ... 0x5f: /* pop reg */
1245 dst.ptr = (unsigned long *)&_regs[b & 0x7];
1246 pop_instruction:
1247 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1248 _regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt->vcpu))
1249 != 0)
1250 goto done;
1251
1252 register_address_increment(_regs[VCPU_REGS_RSP], op_bytes);
1253 no_wb = 1; /* Disable writeback. */
1254 break;
1255 case 0x6c: /* insb */
1256 case 0x6d: /* insw/insd */
1257 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1258 1, /* in */
1259 (d & ByteOp) ? 1 : op_bytes, /* size */
1260 rep_prefix ?
1261 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
1262 (_eflags & EFLG_DF), /* down */
1263 register_address(ctxt->es_base,
1264 _regs[VCPU_REGS_RDI]), /* address */
1265 rep_prefix,
1266 _regs[VCPU_REGS_RDX] /* port */
1267 ) == 0)
1268 return -1;
1269 return 0;
1270 case 0x6e: /* outsb */
1271 case 0x6f: /* outsw/outsd */
1272 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1273 0, /* in */
1274 (d & ByteOp) ? 1 : op_bytes, /* size */
1275 rep_prefix ?
1276 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
1277 (_eflags & EFLG_DF), /* down */
1278 register_address(override_base ?
1279 *override_base : ctxt->ds_base,
1280 _regs[VCPU_REGS_RSI]), /* address */
1281 rep_prefix,
1282 _regs[VCPU_REGS_RDX] /* port */
1283 ) == 0)
1284 return -1;
1285 return 0;
1286 case 0x70 ... 0x7f: /* jcc (short) */ {
1287 int rel = insn_fetch(s8, 1, _eip);
1288
1289 if (test_cc(b, _eflags))
1290 JMP_REL(rel);
1291 break;
1292 }
1293 case 0x9c: /* pushf */
1294 src.val = (unsigned long) _eflags;
1295 goto push;
1296 case 0x9d: /* popf */
1297 dst.ptr = (unsigned long *) &_eflags;
1298 goto pop_instruction;
1299 case 0xc3: /* ret */
1300 dst.ptr = &_eip;
1301 goto pop_instruction;
1302 case 0xf4: /* hlt */
1303 ctxt->vcpu->halt_request = 1;
1304 goto done;
1305 }
1306 if (rep_prefix) {
1307 if (_regs[VCPU_REGS_RCX] == 0) {
1308 ctxt->vcpu->rip = _eip;
1309 goto done;
1310 }
1311 _regs[VCPU_REGS_RCX]--;
1312 _eip = ctxt->vcpu->rip;
1313 }
1314 switch (b) {
1315 case 0xa4 ... 0xa5: /* movs */
1316 dst.type = OP_MEM;
1317 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1318 dst.ptr = (unsigned long *)register_address(ctxt->es_base,
1319 _regs[VCPU_REGS_RDI]);
1320 if ((rc = ops->read_emulated(register_address(
1321 override_base ? *override_base : ctxt->ds_base,
1322 _regs[VCPU_REGS_RSI]), &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1323 goto done;
1324 register_address_increment(_regs[VCPU_REGS_RSI],
1325 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1326 register_address_increment(_regs[VCPU_REGS_RDI],
1327 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1328 break;
1329 case 0xa6 ... 0xa7: /* cmps */
1330 DPRINTF("Urk! I don't handle CMPS.\n");
1331 goto cannot_emulate;
1332 case 0xaa ... 0xab: /* stos */
1333 dst.type = OP_MEM;
1334 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1335 dst.ptr = (unsigned long *)cr2;
1336 dst.val = _regs[VCPU_REGS_RAX];
1337 register_address_increment(_regs[VCPU_REGS_RDI],
1338 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1339 break;
1340 case 0xac ... 0xad: /* lods */
1341 dst.type = OP_REG;
1342 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1343 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1344 if ((rc = ops->read_emulated(cr2, &dst.val, dst.bytes,
1345 ctxt->vcpu)) != 0)
1346 goto done;
1347 register_address_increment(_regs[VCPU_REGS_RSI],
1348 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1349 break;
1350 case 0xae ... 0xaf: /* scas */
1351 DPRINTF("Urk! I don't handle SCAS.\n");
1352 goto cannot_emulate;
1353
1354 }
1355 goto writeback;
1356
1357 twobyte_insn:
1358 switch (b) {
1359 case 0x01: /* lgdt, lidt, lmsw */
1360 /* Disable writeback. */
1361 no_wb = 1;
1362 switch (modrm_reg) {
1363 u16 size;
1364 unsigned long address;
1365
1366 case 2: /* lgdt */
1367 rc = read_descriptor(ctxt, ops, src.ptr,
1368 &size, &address, op_bytes);
1369 if (rc)
1370 goto done;
1371 realmode_lgdt(ctxt->vcpu, size, address);
1372 break;
1373 case 3: /* lidt */
1374 rc = read_descriptor(ctxt, ops, src.ptr,
1375 &size, &address, op_bytes);
1376 if (rc)
1377 goto done;
1378 realmode_lidt(ctxt->vcpu, size, address);
1379 break;
1380 case 4: /* smsw */
1381 if (modrm_mod != 3)
1382 goto cannot_emulate;
1383 *(u16 *)&_regs[modrm_rm]
1384 = realmode_get_cr(ctxt->vcpu, 0);
1385 break;
1386 case 6: /* lmsw */
1387 if (modrm_mod != 3)
1388 goto cannot_emulate;
1389 realmode_lmsw(ctxt->vcpu, (u16)modrm_val, &_eflags);
1390 break;
1391 case 7: /* invlpg*/
1392 emulate_invlpg(ctxt->vcpu, cr2);
1393 break;
1394 default:
1395 goto cannot_emulate;
1396 }
1397 break;
1398 case 0x21: /* mov from dr to reg */
1399 no_wb = 1;
1400 if (modrm_mod != 3)
1401 goto cannot_emulate;
1402 rc = emulator_get_dr(ctxt, modrm_reg, &_regs[modrm_rm]);
1403 break;
1404 case 0x23: /* mov from reg to dr */
1405 no_wb = 1;
1406 if (modrm_mod != 3)
1407 goto cannot_emulate;
1408 rc = emulator_set_dr(ctxt, modrm_reg, _regs[modrm_rm]);
1409 break;
1410 case 0x40 ... 0x4f: /* cmov */
1411 dst.val = dst.orig_val = src.val;
1412 no_wb = 1;
1413 /*
1414 * First, assume we're decoding an even cmov opcode
1415 * (lsb == 0).
1416 */
1417 switch ((b & 15) >> 1) {
1418 case 0: /* cmovo */
1419 no_wb = (_eflags & EFLG_OF) ? 0 : 1;
1420 break;
1421 case 1: /* cmovb/cmovc/cmovnae */
1422 no_wb = (_eflags & EFLG_CF) ? 0 : 1;
1423 break;
1424 case 2: /* cmovz/cmove */
1425 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
1426 break;
1427 case 3: /* cmovbe/cmovna */
1428 no_wb = (_eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
1429 break;
1430 case 4: /* cmovs */
1431 no_wb = (_eflags & EFLG_SF) ? 0 : 1;
1432 break;
1433 case 5: /* cmovp/cmovpe */
1434 no_wb = (_eflags & EFLG_PF) ? 0 : 1;
1435 break;
1436 case 7: /* cmovle/cmovng */
1437 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
1438 /* fall through */
1439 case 6: /* cmovl/cmovnge */
1440 no_wb &= (!(_eflags & EFLG_SF) !=
1441 !(_eflags & EFLG_OF)) ? 0 : 1;
1442 break;
1443 }
1444 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
1445 no_wb ^= b & 1;
1446 break;
1447 case 0xa3:
1448 bt: /* bt */
1449 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1450 emulate_2op_SrcV_nobyte("bt", src, dst, _eflags);
1451 break;
1452 case 0xab:
1453 bts: /* bts */
1454 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1455 emulate_2op_SrcV_nobyte("bts", src, dst, _eflags);
1456 break;
1457 case 0xb0 ... 0xb1: /* cmpxchg */
1458 /*
1459 * Save real source value, then compare EAX against
1460 * destination.
1461 */
1462 src.orig_val = src.val;
1463 src.val = _regs[VCPU_REGS_RAX];
1464 emulate_2op_SrcV("cmp", src, dst, _eflags);
1465 if (_eflags & EFLG_ZF) {
1466 /* Success: write back to memory. */
1467 dst.val = src.orig_val;
1468 } else {
1469 /* Failure: write the value we saw to EAX. */
1470 dst.type = OP_REG;
1471 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1472 }
1473 break;
1474 case 0xb3:
1475 btr: /* btr */
1476 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1477 emulate_2op_SrcV_nobyte("btr", src, dst, _eflags);
1478 break;
1479 case 0xb6 ... 0xb7: /* movzx */
1480 dst.bytes = op_bytes;
1481 dst.val = (d & ByteOp) ? (u8) src.val : (u16) src.val;
1482 break;
1483 case 0xba: /* Grp8 */
1484 switch (modrm_reg & 3) {
1485 case 0:
1486 goto bt;
1487 case 1:
1488 goto bts;
1489 case 2:
1490 goto btr;
1491 case 3:
1492 goto btc;
1493 }
1494 break;
1495 case 0xbb:
1496 btc: /* btc */
1497 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1498 emulate_2op_SrcV_nobyte("btc", src, dst, _eflags);
1499 break;
1500 case 0xbe ... 0xbf: /* movsx */
1501 dst.bytes = op_bytes;
1502 dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
1503 break;
1504 }
1505 goto writeback;
1506
1507 twobyte_special_insn:
1508 /* Disable writeback. */
1509 no_wb = 1;
1510 switch (b) {
1511 case 0x06:
1512 emulate_clts(ctxt->vcpu);
1513 break;
1514 case 0x09: /* wbinvd */
1515 break;
1516 case 0x0d: /* GrpP (prefetch) */
1517 case 0x18: /* Grp16 (prefetch/nop) */
1518 break;
1519 case 0x20: /* mov cr, reg */
1520 if (modrm_mod != 3)
1521 goto cannot_emulate;
1522 _regs[modrm_rm] = realmode_get_cr(ctxt->vcpu, modrm_reg);
1523 break;
1524 case 0x22: /* mov reg, cr */
1525 if (modrm_mod != 3)
1526 goto cannot_emulate;
1527 realmode_set_cr(ctxt->vcpu, modrm_reg, modrm_val, &_eflags);
1528 break;
1529 case 0x30:
1530 /* wrmsr */
1531 msr_data = (u32)_regs[VCPU_REGS_RAX]
1532 | ((u64)_regs[VCPU_REGS_RDX] << 32);
1533 rc = kvm_set_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], msr_data);
1534 if (rc) {
1535 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1536 _eip = ctxt->vcpu->rip;
1537 }
1538 rc = X86EMUL_CONTINUE;
1539 break;
1540 case 0x32:
1541 /* rdmsr */
1542 rc = kvm_get_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], &msr_data);
1543 if (rc) {
1544 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1545 _eip = ctxt->vcpu->rip;
1546 } else {
1547 _regs[VCPU_REGS_RAX] = (u32)msr_data;
1548 _regs[VCPU_REGS_RDX] = msr_data >> 32;
1549 }
1550 rc = X86EMUL_CONTINUE;
1551 break;
1552 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1553 long int rel;
1554
1555 switch (op_bytes) {
1556 case 2:
1557 rel = insn_fetch(s16, 2, _eip);
1558 break;
1559 case 4:
1560 rel = insn_fetch(s32, 4, _eip);
1561 break;
1562 case 8:
1563 rel = insn_fetch(s64, 8, _eip);
1564 break;
1565 default:
1566 DPRINTF("jnz: Invalid op_bytes\n");
1567 goto cannot_emulate;
1568 }
1569 if (test_cc(b, _eflags))
1570 JMP_REL(rel);
1571 break;
1572 }
1573 case 0xc7: /* Grp9 (cmpxchg8b) */
1574 {
1575 u64 old, new;
1576 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu))
1577 != 0)
1578 goto done;
1579 if (((u32) (old >> 0) != (u32) _regs[VCPU_REGS_RAX]) ||
1580 ((u32) (old >> 32) != (u32) _regs[VCPU_REGS_RDX])) {
1581 _regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1582 _regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1583 _eflags &= ~EFLG_ZF;
1584 } else {
1585 new = ((u64)_regs[VCPU_REGS_RCX] << 32)
1586 | (u32) _regs[VCPU_REGS_RBX];
1587 if ((rc = ops->cmpxchg_emulated(cr2, &old,
1588 &new, 8, ctxt->vcpu)) != 0)
1589 goto done;
1590 _eflags |= EFLG_ZF;
1591 }
1592 break;
1593 }
1594 }
1595 goto writeback;
1596
1597 cannot_emulate:
1598 DPRINTF("Cannot emulate %02x\n", b);
1599 return -1;
1600 }
1601
1602 #ifdef __XEN__
1603
1604 #include <asm/mm.h>
1605 #include <asm/uaccess.h>
1606
1607 int
1608 x86_emulate_read_std(unsigned long addr,
1609 unsigned long *val,
1610 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1611 {
1612 unsigned int rc;
1613
1614 *val = 0;
1615
1616 if ((rc = copy_from_user((void *)val, (void *)addr, bytes)) != 0) {
1617 propagate_page_fault(addr + bytes - rc, 0); /* read fault */
1618 return X86EMUL_PROPAGATE_FAULT;
1619 }
1620
1621 return X86EMUL_CONTINUE;
1622 }
1623
1624 int
1625 x86_emulate_write_std(unsigned long addr,
1626 unsigned long val,
1627 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1628 {
1629 unsigned int rc;
1630
1631 if ((rc = copy_to_user((void *)addr, (void *)&val, bytes)) != 0) {
1632 propagate_page_fault(addr + bytes - rc, PGERR_write_access);
1633 return X86EMUL_PROPAGATE_FAULT;
1634 }
1635
1636 return X86EMUL_CONTINUE;
1637 }
1638
1639 #endif
WRT350N Kernel Patches