include/asm-arm/arch-ebsa285/hardware.h

   1 /*
   2  *  linux/include/asm-arm/arch-ebsa285/hardware.h
   3  *
   4  *  Copyright (C) 1998-1999 Russell King.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This file contains the hardware definitions of the EBSA-285.
  11  */
  12 #ifndef __ASM_ARCH_HARDWARE_H
  13 #define __ASM_ARCH_HARDWARE_H
  14
  15 #include <asm/arch/memory.h>
  16
  17 #ifdef CONFIG_ARCH_FOOTBRIDGE
  18 /*   Virtual      Physical      Size
  19  * 0xff800000   0x40000000      1MB     X-Bus
  20  * 0xff000000   0x7c000000      1MB     PCI I/O space
  21  * 0xfe000000   0x42000000      1MB     CSR
  22  * 0xfd000000   0x78000000      1MB     Outbound write flush (not supported)
  23  * 0xfc000000   0x79000000      1MB     PCI IACK/special space
  24  * 0xfb000000   0x7a000000      16MB    PCI Config type 1
  25  * 0xfa000000   0x7b000000      16MB    PCI Config type 0
  26  * 0xf9000000   0x50000000      1MB     Cache flush
  27  * 0xf0000000   0x80000000      16MB    ISA memory
  28  */
  29 #define XBUS_SIZE               0x00100000
  30 #define XBUS_BASE               0xff800000
  31
  32 #define PCIO_SIZE               0x00100000
  33 #define PCIO_BASE               0xff000000
  34
  35 #define ARMCSR_SIZE             0x00100000
  36 #define ARMCSR_BASE             0xfe000000
  37
  38 #define WFLUSH_SIZE             0x00100000
  39 #define WFLUSH_BASE             0xfd000000
  40
  41 #define PCIIACK_SIZE            0x00100000
  42 #define PCIIACK_BASE            0xfc000000
  43
  44 #define PCICFG1_SIZE            0x01000000
  45 #define PCICFG1_BASE            0xfb000000
  46
  47 #define PCICFG0_SIZE            0x01000000
  48 #define PCICFG0_BASE            0xfa000000
  49
  50 #define PCIMEM_SIZE             0x01000000
  51 #define PCIMEM_BASE             0xf0000000
  52
  53 #elif defined(CONFIG_ARCH_CO285)
  54 /*
  55  * This is the COEBSA285 cut-down mapping
  56  */
  57 #define PCIMEM_SIZE             0x80000000
  58 #define PCIMEM_BASE             0x80000000
  59
  60 #define WFLUSH_SIZE             0x01000000
  61 #define WFLUSH_BASE             0x7d000000
  62
  63 #define ARMCSR_SIZE             0x00100000
  64 #define ARMCSR_BASE             0x7cf00000
  65
  66 #define XBUS_SIZE               0x00020000
  67 #define XBUS_BASE               0x7cee0000
  68
  69 #define PCIO_SIZE               0x00010000
  70 #define PCIO_BASE               0x7ced0000
  71
  72 #else
  73
  74 #error "Undefined footbridge architecture"
  75
  76 #endif
  77
  78 #define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
  79 #define XBUS_LED_AMBER          (1 << 0)
  80 #define XBUS_LED_GREEN          (1 << 1)
  81 #define XBUS_LED_RED            (1 << 2)
  82 #define XBUS_LED_TOGGLE         (1 << 8)
  83
  84 #define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
  85 #define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
  86 #define XBUS_SWITCH_J17_13      ((*XBUS_SWITCH) & (1 << 4))
  87 #define XBUS_SWITCH_J17_11      ((*XBUS_SWITCH) & (1 << 5))
  88 #define XBUS_SWITCH_J17_9       ((*XBUS_SWITCH) & (1 << 6))
  89
  90 #define UNCACHEABLE_ADDR        (ARMCSR_BASE + 0x108)
  91
  92
  93 /* PIC irq control */
  94 #define PIC_LO                  0x20
  95 #define PIC_MASK_LO             0x21
  96 #define PIC_HI                  0xA0
  97 #define PIC_MASK_HI             0xA1
  98
  99 /* GPIO pins */
 100 #define GPIO_CCLK               0x800
 101 #define GPIO_DSCLK              0x400
 102 #define GPIO_E2CLK              0x200
 103 #define GPIO_IOLOAD             0x100
 104 #define GPIO_RED_LED            0x080
 105 #define GPIO_WDTIMER            0x040
 106 #define GPIO_DATA               0x020
 107 #define GPIO_IOCLK              0x010
 108 #define GPIO_DONE               0x008
 109 #define GPIO_FAN                0x004
 110 #define GPIO_GREEN_LED          0x002
 111 #define GPIO_RESET              0x001
 112
 113 /* CPLD pins */
 114 #define CPLD_DS_ENABLE          8
 115 #define CPLD_7111_DISABLE       4
 116 #define CPLD_UNMUTE             2
 117 #define CPLD_FLASH_WR_ENABLE    1
 118
 119 #ifndef __ASSEMBLY__
 120 extern void gpio_modify_op(int mask, int set);
 121 extern void gpio_modify_io(int mask, int in);
 122 extern int  gpio_read(void);
 123 extern void cpld_modify(int mask, int set);
 124 #endif
 125
 126 #define pcibios_assign_all_busses()     1
 127
 128 #define PCIBIOS_MIN_IO          0x1000
 129 #define PCIBIOS_MIN_MEM         0x81000000
 130
 131 #endif