arch/powerpc/boot/dts/mpc834x_mds.dts

   1 /*
   2  * MPC8349E MDS Device Tree Source
   3  *
   4  * Copyright 2005, 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8349EMDS";
  16         compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8349@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;
  37                         i-cache-line-size = <32>;
  38                         d-cache-size = <32768>;
  39                         i-cache-size = <32768>;
  40                         timebase-frequency = <0>;       // from bootloader
  41                         bus-frequency = <0>;            // from bootloader
  42                         clock-frequency = <0>;          // from bootloader
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x00000000 0x10000000>;  // 256MB at 0
  49         };
  50
  51         bcsr@e2400000 {
  52                 device_type = "board-control";
  53                 reg = <0xe2400000 0x8000>;
  54         };
  55
  56         soc8349@e0000000 {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 device_type = "soc";
  60                 ranges = <0x0 0xe0000000 0x00100000>;
  61                 reg = <0xe0000000 0x00000200>;
  62                 bus-frequency = <0>;
  63
  64                 wdt@200 {
  65                         device_type = "watchdog";
  66                         compatible = "mpc83xx_wdt";
  67                         reg = <0x200 0x100>;
  68                 };
  69
  70                 i2c@3000 {
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         cell-index = <0>;
  74                         compatible = "fsl-i2c";
  75                         reg = <0x3000 0x100>;
  76                         interrupts = <14 0x8>;
  77                         interrupt-parent = <&ipic>;
  78                         dfsrr;
  79
  80                         rtc@68 {
  81                                 compatible = "dallas,ds1374";
  82                                 reg = <0x68>;
  83                         };
  84                 };
  85
  86                 i2c@3100 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         cell-index = <1>;
  90                         compatible = "fsl-i2c";
  91                         reg = <0x3100 0x100>;
  92                         interrupts = <15 0x8>;
  93                         interrupt-parent = <&ipic>;
  94                         dfsrr;
  95                 };
  96
  97                 spi@7000 {
  98                         cell-index = <0>;
  99                         compatible = "fsl,spi";
 100                         reg = <0x7000 0x1000>;
 101                         interrupts = <16 0x8>;
 102                         interrupt-parent = <&ipic>;
 103                         mode = "cpu";
 104                 };
 105
 106                 /* phy type (ULPI or SERIAL) are only types supported for MPH */
 107                 /* port = 0 or 1 */
 108                 usb@22000 {
 109                         compatible = "fsl-usb2-mph";
 110                         reg = <0x22000 0x1000>;
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         interrupt-parent = <&ipic>;
 114                         interrupts = <39 0x8>;
 115                         phy_type = "ulpi";
 116                         port1;
 117                 };
 118                 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
 119                 usb@23000 {
 120                         compatible = "fsl-usb2-dr";
 121                         reg = <0x23000 0x1000>;
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         interrupt-parent = <&ipic>;
 125                         interrupts = <38 0x8>;
 126                         dr_mode = "otg";
 127                         phy_type = "ulpi";
 128                 };
 129
 130                 mdio@24520 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         compatible = "fsl,gianfar-mdio";
 134                         reg = <0x24520 0x20>;
 135
 136                         phy0: ethernet-phy@0 {
 137                                 interrupt-parent = <&ipic>;
 138                                 interrupts = <17 0x8>;
 139                                 reg = <0x0>;
 140                                 device_type = "ethernet-phy";
 141                         };
 142                         phy1: ethernet-phy@1 {
 143                                 interrupt-parent = <&ipic>;
 144                                 interrupts = <18 0x8>;
 145                                 reg = <0x1>;
 146                                 device_type = "ethernet-phy";
 147                         };
 148                 };
 149
 150                 enet0: ethernet@24000 {
 151                         cell-index = <0>;
 152                         device_type = "network";
 153                         model = "TSEC";
 154                         compatible = "gianfar";
 155                         reg = <0x24000 0x1000>;
 156                         local-mac-address = [ 00 00 00 00 00 00 ];
 157                         interrupts = <32 0x8 33 0x8 34 0x8>;
 158                         interrupt-parent = <&ipic>;
 159                         phy-handle = <&phy0>;
 160                         linux,network-index = <0>;
 161                 };
 162
 163                 enet1: ethernet@25000 {
 164                         cell-index = <1>;
 165                         device_type = "network";
 166                         model = "TSEC";
 167                         compatible = "gianfar";
 168                         reg = <0x25000 0x1000>;
 169                         local-mac-address = [ 00 00 00 00 00 00 ];
 170                         interrupts = <35 0x8 36 0x8 37 0x8>;
 171                         interrupt-parent = <&ipic>;
 172                         phy-handle = <&phy1>;
 173                         linux,network-index = <1>;
 174                 };
 175
 176                 serial0: serial@4500 {
 177                         cell-index = <0>;
 178                         device_type = "serial";
 179                         compatible = "ns16550";
 180                         reg = <0x4500 0x100>;
 181                         clock-frequency = <0>;
 182                         interrupts = <9 0x8>;
 183                         interrupt-parent = <&ipic>;
 184                 };
 185
 186                 serial1: serial@4600 {
 187                         cell-index = <1>;
 188                         device_type = "serial";
 189                         compatible = "ns16550";
 190                         reg = <0x4600 0x100>;
 191                         clock-frequency = <0>;
 192                         interrupts = <10 0x8>;
 193                         interrupt-parent = <&ipic>;
 194                 };
 195
 196                 /* May need to remove if on a part without crypto engine */
 197                 crypto@30000 {
 198                         device_type = "crypto";
 199                         model = "SEC2";
 200                         compatible = "talitos";
 201                         reg = <0x30000 0x10000>;
 202                         interrupts = <11 0x8>;
 203                         interrupt-parent = <&ipic>;
 204                         num-channels = <4>;
 205                         channel-fifo-len = <24>;
 206                         exec-units-mask = <0x0000007e>;
 207                         /* desc mask is for rev2.0,
 208                          * we need runtime fixup for >2.0 */
 209                         descriptor-types-mask = <0x01010ebf>;
 210                 };
 211
 212                 /* IPIC
 213                  * interrupts cell = <intr #, sense>
 214                  * sense values match linux IORESOURCE_IRQ_* defines:
 215                  * sense == 8: Level, low assertion
 216                  * sense == 2: Edge, high-to-low change
 217                  */
 218                 ipic: pic@700 {
 219                         interrupt-controller;
 220                         #address-cells = <0>;
 221                         #interrupt-cells = <2>;
 222                         reg = <0x700 0x100>;
 223                         device_type = "ipic";
 224                 };
 225         };
 226
 227         pci0: pci@e0008500 {
 228                 cell-index = <1>;
 229                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 230                 interrupt-map = <
 231
 232                                 /* IDSEL 0x11 */
 233                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 234                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 235                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 236                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 237
 238                                 /* IDSEL 0x12 */
 239                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 240                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 241                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 242                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 243
 244                                 /* IDSEL 0x13 */
 245                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 246                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 247                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 248                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 249
 250                                 /* IDSEL 0x15 */
 251                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 252                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 253                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 254                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 255
 256                                 /* IDSEL 0x16 */
 257                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 258                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 259                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 260                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 261
 262                                 /* IDSEL 0x17 */
 263                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 264                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 265                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 266                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 267
 268                                 /* IDSEL 0x18 */
 269                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 270                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 271                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 272                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 273                 interrupt-parent = <&ipic>;
 274                 interrupts = <66 0x8>;
 275                 bus-range = <0 0>;
 276                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 277                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 278                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
 279                 clock-frequency = <66666666>;
 280                 #interrupt-cells = <1>;
 281                 #size-cells = <2>;
 282                 #address-cells = <3>;
 283                 reg = <0xe0008500 0x100>;
 284                 compatible = "fsl,mpc8349-pci";
 285                 device_type = "pci";
 286         };
 287
 288         pci1: pci@e0008600 {
 289                 cell-index = <2>;
 290                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 291                 interrupt-map = <
 292
 293                                 /* IDSEL 0x11 */
 294                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 295                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 296                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 297                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 298
 299                                 /* IDSEL 0x12 */
 300                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 301                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 302                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 303                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 304
 305                                 /* IDSEL 0x13 */
 306                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 307                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 308                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 309                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 310
 311                                 /* IDSEL 0x15 */
 312                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 313                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 314                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 315                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 316
 317                                 /* IDSEL 0x16 */
 318                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 319                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 320                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 321                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 322
 323                                 /* IDSEL 0x17 */
 324                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 325                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 326                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 327                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 328
 329                                 /* IDSEL 0x18 */
 330                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 331                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 332                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 333                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 334                 interrupt-parent = <&ipic>;
 335                 interrupts = <67 0x8>;
 336                 bus-range = <0 0>;
 337                 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
 338                           0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 339                           0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
 340                 clock-frequency = <66666666>;
 341                 #interrupt-cells = <1>;
 342                 #size-cells = <2>;
 343                 #address-cells = <3>;
 344                 reg = <0xe0008600 0x100>;
 345                 compatible = "fsl,mpc8349-pci";
 346                 device_type = "pci";
 347         };
 348 };