arch/powerpc/boot/dts/mpc8560ads.dts

   1 /*
   2  * MPC8560 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8560ADS";
  15         compatible = "MPC8560ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 ethernet3 = &enet3;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8560@0 {
  34                         device_type = "cpu";
  35                         reg = <0>;
  36                         d-cache-line-size = <20>;       // 32 bytes
  37                         i-cache-line-size = <20>;       // 32 bytes
  38                         d-cache-size = <8000>;          // L1, 32K
  39                         i-cache-size = <8000>;          // L1, 32K
  40                         timebase-frequency = <04ead9a0>;
  41                         bus-frequency = <13ab6680>;
  42                         clock-frequency = <312c8040>;
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <00000000 10000000>;
  49         };
  50
  51         soc8560@e0000000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 device_type = "soc";
  55                 ranges = <0 e0000000 00100000>;
  56                 reg = <e0000000 00000200>;
  57                 bus-frequency = <13ab6680>;
  58
  59                 memory-controller@2000 {
  60                         compatible = "fsl,8540-memory-controller";
  61                         reg = <2000 1000>;
  62                         interrupt-parent = <&mpic>;
  63                         interrupts = <12 2>;
  64                 };
  65
  66                 l2-cache-controller@20000 {
  67                         compatible = "fsl,8540-l2-cache-controller";
  68                         reg = <20000 1000>;
  69                         cache-line-size = <20>; // 32 bytes
  70                         cache-size = <40000>;   // L2, 256K
  71                         interrupt-parent = <&mpic>;
  72                         interrupts = <10 2>;
  73                 };
  74
  75                 mdio@24520 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         compatible = "fsl,gianfar-mdio";
  79                         reg = <24520 20>;
  80
  81                         phy0: ethernet-phy@0 {
  82                                 interrupt-parent = <&mpic>;
  83                                 interrupts = <5 1>;
  84                                 reg = <0>;
  85                                 device_type = "ethernet-phy";
  86                         };
  87                         phy1: ethernet-phy@1 {
  88                                 interrupt-parent = <&mpic>;
  89                                 interrupts = <5 1>;
  90                                 reg = <1>;
  91                                 device_type = "ethernet-phy";
  92                         };
  93                         phy2: ethernet-phy@2 {
  94                                 interrupt-parent = <&mpic>;
  95                                 interrupts = <7 1>;
  96                                 reg = <2>;
  97                                 device_type = "ethernet-phy";
  98                         };
  99                         phy3: ethernet-phy@3 {
 100                                 interrupt-parent = <&mpic>;
 101                                 interrupts = <7 1>;
 102                                 reg = <3>;
 103                                 device_type = "ethernet-phy";
 104                         };
 105                 };
 106
 107                 enet0: ethernet@24000 {
 108                         cell-index = <0>;
 109                         device_type = "network";
 110                         model = "TSEC";
 111                         compatible = "gianfar";
 112                         reg = <24000 1000>;
 113                         local-mac-address = [ 00 00 00 00 00 00 ];
 114                         interrupts = <1d 2 1e 2 22 2>;
 115                         interrupt-parent = <&mpic>;
 116                         phy-handle = <&phy0>;
 117                 };
 118
 119                 enet1: ethernet@25000 {
 120                         cell-index = <1>;
 121                         device_type = "network";
 122                         model = "TSEC";
 123                         compatible = "gianfar";
 124                         reg = <25000 1000>;
 125                         local-mac-address = [ 00 00 00 00 00 00 ];
 126                         interrupts = <23 2 24 2 28 2>;
 127                         interrupt-parent = <&mpic>;
 128                         phy-handle = <&phy1>;
 129                 };
 130
 131                 mpic: pic@40000 {
 132                         interrupt-controller;
 133                         #address-cells = <0>;
 134                         #interrupt-cells = <2>;
 135                         reg = <40000 40000>;
 136                         device_type = "open-pic";
 137                 };
 138
 139                 cpm@919c0 {
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
 143                         reg = <919c0 30>;
 144                         ranges;
 145
 146                         muram@80000 {
 147                                 #address-cells = <1>;
 148                                 #size-cells = <1>;
 149                                 ranges = <0 80000 10000>;
 150
 151                                 data@0 {
 152                                         compatible = "fsl,cpm-muram-data";
 153                                         reg = <0 4000 9000 2000>;
 154                                 };
 155                         };
 156
 157                         brg@919f0 {
 158                                 compatible = "fsl,mpc8560-brg",
 159                                              "fsl,cpm2-brg",
 160                                              "fsl,cpm-brg";
 161                                 reg = <919f0 10 915f0 10>;
 162                                 clock-frequency = <d#165000000>;
 163                         };
 164
 165                         cpmpic: pic@90c00 {
 166                                 interrupt-controller;
 167                                 #address-cells = <0>;
 168                                 #interrupt-cells = <2>;
 169                                 interrupts = <2e 2>;
 170                                 interrupt-parent = <&mpic>;
 171                                 reg = <90c00 80>;
 172                                 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
 173                         };
 174
 175                         serial0: serial@91a00 {
 176                                 device_type = "serial";
 177                                 compatible = "fsl,mpc8560-scc-uart",
 178                                              "fsl,cpm2-scc-uart";
 179                                 reg = <91a00 20 88000 100>;
 180                                 fsl,cpm-brg = <1>;
 181                                 fsl,cpm-command = <00800000>;
 182                                 current-speed = <1c200>;
 183                                 interrupts = <28 8>;
 184                                 interrupt-parent = <&cpmpic>;
 185                         };
 186
 187                         serial1: serial@91a20 {
 188                                 device_type = "serial";
 189                                 compatible = "fsl,mpc8560-scc-uart",
 190                                              "fsl,cpm2-scc-uart";
 191                                 reg = <91a20 20 88100 100>;
 192                                 fsl,cpm-brg = <2>;
 193                                 fsl,cpm-command = <04a00000>;
 194                                 current-speed = <1c200>;
 195                                 interrupts = <29 8>;
 196                                 interrupt-parent = <&cpmpic>;
 197                         };
 198
 199                         enet2: ethernet@91320 {
 200                                 device_type = "network";
 201                                 compatible = "fsl,mpc8560-fcc-enet",
 202                                              "fsl,cpm2-fcc-enet";
 203                                 reg = <91320 20 88500 100 913b0 1>;
 204                                 local-mac-address = [ 00 00 00 00 00 00 ];
 205                                 fsl,cpm-command = <16200300>;
 206                                 interrupts = <21 8>;
 207                                 interrupt-parent = <&cpmpic>;
 208                                 phy-handle = <&phy2>;
 209                         };
 210
 211                         enet3: ethernet@91340 {
 212                                 device_type = "network";
 213                                 compatible = "fsl,mpc8560-fcc-enet",
 214                                              "fsl,cpm2-fcc-enet";
 215                                 reg = <91340 20 88600 100 913d0 1>;
 216                                 local-mac-address = [ 00 00 00 00 00 00 ];
 217                                 fsl,cpm-command = <1a400300>;
 218                                 interrupts = <22 8>;
 219                                 interrupt-parent = <&cpmpic>;
 220                                 phy-handle = <&phy3>;
 221                         };
 222                 };
 223         };
 224
 225         pci0: pci@e0008000 {
 226                 cell-index = <0>;
 227                 #interrupt-cells = <1>;
 228                 #size-cells = <2>;
 229                 #address-cells = <3>;
 230                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 231                 device_type = "pci";
 232                 reg = <e0008000 1000>;
 233                 clock-frequency = <3f940aa>;
 234                 interrupt-map-mask = <f800 0 0 7>;
 235                 interrupt-map = <
 236
 237                                 /* IDSEL 0x2 */
 238                                  1000 0 0 1 &mpic 1 1
 239                                  1000 0 0 2 &mpic 2 1
 240                                  1000 0 0 3 &mpic 3 1
 241                                  1000 0 0 4 &mpic 4 1
 242
 243                                 /* IDSEL 0x3 */
 244                                  1800 0 0 1 &mpic 4 1
 245                                  1800 0 0 2 &mpic 1 1
 246                                  1800 0 0 3 &mpic 2 1
 247                                  1800 0 0 4 &mpic 3 1
 248
 249                                 /* IDSEL 0x4 */
 250                                  2000 0 0 1 &mpic 3 1
 251                                  2000 0 0 2 &mpic 4 1
 252                                  2000 0 0 3 &mpic 1 1
 253                                  2000 0 0 4 &mpic 2 1
 254
 255                                 /* IDSEL 0x5  */
 256                                  2800 0 0 1 &mpic 2 1
 257                                  2800 0 0 2 &mpic 3 1
 258                                  2800 0 0 3 &mpic 4 1
 259                                  2800 0 0 4 &mpic 1 1
 260
 261                                 /* IDSEL 12 */
 262                                  6000 0 0 1 &mpic 1 1
 263                                  6000 0 0 2 &mpic 2 1
 264                                  6000 0 0 3 &mpic 3 1
 265                                  6000 0 0 4 &mpic 4 1
 266
 267                                 /* IDSEL 13 */
 268                                  6800 0 0 1 &mpic 4 1
 269                                  6800 0 0 2 &mpic 1 1
 270                                  6800 0 0 3 &mpic 2 1
 271                                  6800 0 0 4 &mpic 3 1
 272
 273                                 /* IDSEL 14*/
 274                                  7000 0 0 1 &mpic 3 1
 275                                  7000 0 0 2 &mpic 4 1
 276                                  7000 0 0 3 &mpic 1 1
 277                                  7000 0 0 4 &mpic 2 1
 278
 279                                 /* IDSEL 15 */
 280                                  7800 0 0 1 &mpic 2 1
 281                                  7800 0 0 2 &mpic 3 1
 282                                  7800 0 0 3 &mpic 4 1
 283                                  7800 0 0 4 &mpic 1 1
 284
 285                                 /* IDSEL 18 */
 286                                  9000 0 0 1 &mpic 1 1
 287                                  9000 0 0 2 &mpic 2 1
 288                                  9000 0 0 3 &mpic 3 1
 289                                  9000 0 0 4 &mpic 4 1
 290
 291                                 /* IDSEL 19 */
 292                                  9800 0 0 1 &mpic 4 1
 293                                  9800 0 0 2 &mpic 1 1
 294                                  9800 0 0 3 &mpic 2 1
 295                                  9800 0 0 4 &mpic 3 1
 296
 297                                 /* IDSEL 20 */
 298                                  a000 0 0 1 &mpic 3 1
 299                                  a000 0 0 2 &mpic 4 1
 300                                  a000 0 0 3 &mpic 1 1
 301                                  a000 0 0 4 &mpic 2 1
 302
 303                                 /* IDSEL 21 */
 304                                  a800 0 0 1 &mpic 2 1
 305                                  a800 0 0 2 &mpic 3 1
 306                                  a800 0 0 3 &mpic 4 1
 307                                  a800 0 0 4 &mpic 1 1>;
 308
 309                 interrupt-parent = <&mpic>;
 310                 interrupts = <18 2>;
 311                 bus-range = <0 0>;
 312                 ranges = <02000000 0 80000000 80000000 0 20000000
 313                           01000000 0 00000000 e2000000 0 01000000>;
 314         };
 315 };