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x86: i8259A: remove redundant irq_descinitialization
[wrt350n-kernel.git] / include / asm-mips / mach-au1x00 / au1000.h
blobcb18af98964573a8dbfd7441e45e7bea2ca27403
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 /*
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
33 */
34
35 #ifndef _AU1000_H_
36 #define _AU1000_H_
37
38
39 #ifndef _LANGUAGE_ASSEMBLY
40
41 #include <linux/delay.h>
42 #include <linux/types.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46
47 /* cpu pipeline flush */
48 void static inline au_sync(void)
49 {
50 __asm__ volatile ("sync");
51 }
52
53 void static inline au_sync_udelay(int us)
54 {
55 __asm__ volatile ("sync");
56 udelay(us);
57 }
58
59 void static inline au_sync_delay(int ms)
60 {
61 __asm__ volatile ("sync");
62 mdelay(ms);
63 }
64
65 void static inline au_writeb(u8 val, unsigned long reg)
66 {
67 *(volatile u8 *)(reg) = val;
68 }
69
70 void static inline au_writew(u16 val, unsigned long reg)
71 {
72 *(volatile u16 *)(reg) = val;
73 }
74
75 void static inline au_writel(u32 val, unsigned long reg)
76 {
77 *(volatile u32 *)(reg) = val;
78 }
79
80 static inline u8 au_readb(unsigned long reg)
81 {
82 return (*(volatile u8 *)reg);
83 }
84
85 static inline u16 au_readw(unsigned long reg)
86 {
87 return (*(volatile u16 *)reg);
88 }
89
90 static inline u32 au_readl(unsigned long reg)
91 {
92 return (*(volatile u32 *)reg);
93 }
94
95
96 /* arch/mips/au1000/common/clocks.c */
97 extern void set_au1x00_speed(unsigned int new_freq);
98 extern unsigned int get_au1x00_speed(void);
99 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
100 extern unsigned long get_au1x00_uart_baud_base(void);
101 extern void set_au1x00_lcd_clock(void);
102 extern unsigned int get_au1x00_lcd_clock(void);
103
104 /*
105 * Every board describes its IRQ mapping with this table.
106 */
107 struct au1xxx_irqmap {
108 int im_irq;
109 int im_type;
110 int im_request;
111 };
112
113 /*
114 * init_IRQ looks for a table with this name.
115 */
116 extern struct au1xxx_irqmap au1xxx_irq_map[];
117
118 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
119
120 #ifdef CONFIG_PM
121 /* no CP0 timer irq */
122 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
123 #else
124 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
125 #endif
126
127 /*
128 * SDRAM Register Offsets
129 */
130 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
131 #define MEM_SDMODE0 (0x0000)
132 #define MEM_SDMODE1 (0x0004)
133 #define MEM_SDMODE2 (0x0008)
134 #define MEM_SDADDR0 (0x000C)
135 #define MEM_SDADDR1 (0x0010)
136 #define MEM_SDADDR2 (0x0014)
137 #define MEM_SDREFCFG (0x0018)
138 #define MEM_SDPRECMD (0x001C)
139 #define MEM_SDAUTOREF (0x0020)
140 #define MEM_SDWRMD0 (0x0024)
141 #define MEM_SDWRMD1 (0x0028)
142 #define MEM_SDWRMD2 (0x002C)
143 #define MEM_SDSLEEP (0x0030)
144 #define MEM_SDSMCKE (0x0034)
145
146 /*
147 * MEM_SDMODE register content definitions
148 */
149 #define MEM_SDMODE_F (1<<22)
150 #define MEM_SDMODE_SR (1<<21)
151 #define MEM_SDMODE_BS (1<<20)
152 #define MEM_SDMODE_RS (3<<18)
153 #define MEM_SDMODE_CS (7<<15)
154 #define MEM_SDMODE_TRAS (15<<11)
155 #define MEM_SDMODE_TMRD (3<<9)
156 #define MEM_SDMODE_TWR (3<<7)
157 #define MEM_SDMODE_TRP (3<<5)
158 #define MEM_SDMODE_TRCD (3<<3)
159 #define MEM_SDMODE_TCL (7<<0)
160
161 #define MEM_SDMODE_BS_2Bank (0<<20)
162 #define MEM_SDMODE_BS_4Bank (1<<20)
163 #define MEM_SDMODE_RS_11Row (0<<18)
164 #define MEM_SDMODE_RS_12Row (1<<18)
165 #define MEM_SDMODE_RS_13Row (2<<18)
166 #define MEM_SDMODE_RS_N(N) ((N)<<18)
167 #define MEM_SDMODE_CS_7Col (0<<15)
168 #define MEM_SDMODE_CS_8Col (1<<15)
169 #define MEM_SDMODE_CS_9Col (2<<15)
170 #define MEM_SDMODE_CS_10Col (3<<15)
171 #define MEM_SDMODE_CS_11Col (4<<15)
172 #define MEM_SDMODE_CS_N(N) ((N)<<15)
173 #define MEM_SDMODE_TRAS_N(N) ((N)<<11)
174 #define MEM_SDMODE_TMRD_N(N) ((N)<<9)
175 #define MEM_SDMODE_TWR_N(N) ((N)<<7)
176 #define MEM_SDMODE_TRP_N(N) ((N)<<5)
177 #define MEM_SDMODE_TRCD_N(N) ((N)<<3)
178 #define MEM_SDMODE_TCL_N(N) ((N)<<0)
179
180 /*
181 * MEM_SDADDR register contents definitions
182 */
183 #define MEM_SDADDR_E (1<<20)
184 #define MEM_SDADDR_CSBA (0x03FF<<10)
185 #define MEM_SDADDR_CSMASK (0x03FF<<0)
186 #define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
187 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
188
189 /*
190 * MEM_SDREFCFG register content definitions
191 */
192 #define MEM_SDREFCFG_TRC (15<<28)
193 #define MEM_SDREFCFG_TRPM (3<<26)
194 #define MEM_SDREFCFG_E (1<<25)
195 #define MEM_SDREFCFG_RE (0x1ffffff<<0)
196 #define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
197 #define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
198 #define MEM_SDREFCFG_REF_N(N) (N)
199 #endif
200
201 /***********************************************************************/
202
203 /*
204 * Au1550 SDRAM Register Offsets
205 */
206
207 /***********************************************************************/
208
209 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
210 #define MEM_SDMODE0 (0x0800)
211 #define MEM_SDMODE1 (0x0808)
212 #define MEM_SDMODE2 (0x0810)
213 #define MEM_SDADDR0 (0x0820)
214 #define MEM_SDADDR1 (0x0828)
215 #define MEM_SDADDR2 (0x0830)
216 #define MEM_SDCONFIGA (0x0840)
217 #define MEM_SDCONFIGB (0x0848)
218 #define MEM_SDSTAT (0x0850)
219 #define MEM_SDERRADDR (0x0858)
220 #define MEM_SDSTRIDE0 (0x0860)
221 #define MEM_SDSTRIDE1 (0x0868)
222 #define MEM_SDSTRIDE2 (0x0870)
223 #define MEM_SDWRMD0 (0x0880)
224 #define MEM_SDWRMD1 (0x0888)
225 #define MEM_SDWRMD2 (0x0890)
226 #define MEM_SDPRECMD (0x08C0)
227 #define MEM_SDAUTOREF (0x08C8)
228 #define MEM_SDSREF (0x08D0)
229 #define MEM_SDSLEEP MEM_SDSREF
230
231 #endif
232
233 /*
234 * Physical base addresses for integrated peripherals
235 */
236
237 #ifdef CONFIG_SOC_AU1000
238 #define MEM_PHYS_ADDR 0x14000000
239 #define STATIC_MEM_PHYS_ADDR 0x14001000
240 #define DMA0_PHYS_ADDR 0x14002000
241 #define DMA1_PHYS_ADDR 0x14002100
242 #define DMA2_PHYS_ADDR 0x14002200
243 #define DMA3_PHYS_ADDR 0x14002300
244 #define DMA4_PHYS_ADDR 0x14002400
245 #define DMA5_PHYS_ADDR 0x14002500
246 #define DMA6_PHYS_ADDR 0x14002600
247 #define DMA7_PHYS_ADDR 0x14002700
248 #define IC0_PHYS_ADDR 0x10400000
249 #define IC1_PHYS_ADDR 0x11800000
250 #define AC97_PHYS_ADDR 0x10000000
251 #define USBH_PHYS_ADDR 0x10100000
252 #define USBD_PHYS_ADDR 0x10200000
253 #define IRDA_PHYS_ADDR 0x10300000
254 #define MAC0_PHYS_ADDR 0x10500000
255 #define MAC1_PHYS_ADDR 0x10510000
256 #define MACEN_PHYS_ADDR 0x10520000
257 #define MACDMA0_PHYS_ADDR 0x14004000
258 #define MACDMA1_PHYS_ADDR 0x14004200
259 #define I2S_PHYS_ADDR 0x11000000
260 #define UART0_PHYS_ADDR 0x11100000
261 #define UART1_PHYS_ADDR 0x11200000
262 #define UART2_PHYS_ADDR 0x11300000
263 #define UART3_PHYS_ADDR 0x11400000
264 #define SSI0_PHYS_ADDR 0x11600000
265 #define SSI1_PHYS_ADDR 0x11680000
266 #define SYS_PHYS_ADDR 0x11900000
267 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
268 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
269 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
270 #endif
271
272 /********************************************************************/
273
274 #ifdef CONFIG_SOC_AU1500
275 #define MEM_PHYS_ADDR 0x14000000
276 #define STATIC_MEM_PHYS_ADDR 0x14001000
277 #define DMA0_PHYS_ADDR 0x14002000
278 #define DMA1_PHYS_ADDR 0x14002100
279 #define DMA2_PHYS_ADDR 0x14002200
280 #define DMA3_PHYS_ADDR 0x14002300
281 #define DMA4_PHYS_ADDR 0x14002400
282 #define DMA5_PHYS_ADDR 0x14002500
283 #define DMA6_PHYS_ADDR 0x14002600
284 #define DMA7_PHYS_ADDR 0x14002700
285 #define IC0_PHYS_ADDR 0x10400000
286 #define IC1_PHYS_ADDR 0x11800000
287 #define AC97_PHYS_ADDR 0x10000000
288 #define USBH_PHYS_ADDR 0x10100000
289 #define USBD_PHYS_ADDR 0x10200000
290 #define PCI_PHYS_ADDR 0x14005000
291 #define MAC0_PHYS_ADDR 0x11500000
292 #define MAC1_PHYS_ADDR 0x11510000
293 #define MACEN_PHYS_ADDR 0x11520000
294 #define MACDMA0_PHYS_ADDR 0x14004000
295 #define MACDMA1_PHYS_ADDR 0x14004200
296 #define I2S_PHYS_ADDR 0x11000000
297 #define UART0_PHYS_ADDR 0x11100000
298 #define UART3_PHYS_ADDR 0x11400000
299 #define GPIO2_PHYS_ADDR 0x11700000
300 #define SYS_PHYS_ADDR 0x11900000
301 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
302 #define PCI_IO_PHYS_ADDR 0x500000000ULL
303 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
304 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
305 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
306 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
307 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
308 #endif
309
310 /********************************************************************/
311
312 #ifdef CONFIG_SOC_AU1100
313 #define MEM_PHYS_ADDR 0x14000000
314 #define STATIC_MEM_PHYS_ADDR 0x14001000
315 #define DMA0_PHYS_ADDR 0x14002000
316 #define DMA1_PHYS_ADDR 0x14002100
317 #define DMA2_PHYS_ADDR 0x14002200
318 #define DMA3_PHYS_ADDR 0x14002300
319 #define DMA4_PHYS_ADDR 0x14002400
320 #define DMA5_PHYS_ADDR 0x14002500
321 #define DMA6_PHYS_ADDR 0x14002600
322 #define DMA7_PHYS_ADDR 0x14002700
323 #define IC0_PHYS_ADDR 0x10400000
324 #define SD0_PHYS_ADDR 0x10600000
325 #define SD1_PHYS_ADDR 0x10680000
326 #define IC1_PHYS_ADDR 0x11800000
327 #define AC97_PHYS_ADDR 0x10000000
328 #define USBH_PHYS_ADDR 0x10100000
329 #define USBD_PHYS_ADDR 0x10200000
330 #define IRDA_PHYS_ADDR 0x10300000
331 #define MAC0_PHYS_ADDR 0x10500000
332 #define MACEN_PHYS_ADDR 0x10520000
333 #define MACDMA0_PHYS_ADDR 0x14004000
334 #define MACDMA1_PHYS_ADDR 0x14004200
335 #define I2S_PHYS_ADDR 0x11000000
336 #define UART0_PHYS_ADDR 0x11100000
337 #define UART1_PHYS_ADDR 0x11200000
338 #define UART3_PHYS_ADDR 0x11400000
339 #define SSI0_PHYS_ADDR 0x11600000
340 #define SSI1_PHYS_ADDR 0x11680000
341 #define GPIO2_PHYS_ADDR 0x11700000
342 #define SYS_PHYS_ADDR 0x11900000
343 #define LCD_PHYS_ADDR 0x15000000
344 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
345 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
346 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
347 #endif
348
349 /***********************************************************************/
350
351 #ifdef CONFIG_SOC_AU1550
352 #define MEM_PHYS_ADDR 0x14000000
353 #define STATIC_MEM_PHYS_ADDR 0x14001000
354 #define IC0_PHYS_ADDR 0x10400000
355 #define IC1_PHYS_ADDR 0x11800000
356 #define USBH_PHYS_ADDR 0x14020000
357 #define USBD_PHYS_ADDR 0x10200000
358 #define PCI_PHYS_ADDR 0x14005000
359 #define MAC0_PHYS_ADDR 0x10500000
360 #define MAC1_PHYS_ADDR 0x10510000
361 #define MACEN_PHYS_ADDR 0x10520000
362 #define MACDMA0_PHYS_ADDR 0x14004000
363 #define MACDMA1_PHYS_ADDR 0x14004200
364 #define UART0_PHYS_ADDR 0x11100000
365 #define UART1_PHYS_ADDR 0x11200000
366 #define UART3_PHYS_ADDR 0x11400000
367 #define GPIO2_PHYS_ADDR 0x11700000
368 #define SYS_PHYS_ADDR 0x11900000
369 #define DDMA_PHYS_ADDR 0x14002000
370 #define PE_PHYS_ADDR 0x14008000
371 #define PSC0_PHYS_ADDR 0x11A00000
372 #define PSC1_PHYS_ADDR 0x11B00000
373 #define PSC2_PHYS_ADDR 0x10A00000
374 #define PSC3_PHYS_ADDR 0x10B00000
375 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
376 #define PCI_IO_PHYS_ADDR 0x500000000ULL
377 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
378 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
379 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
380 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
381 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
382 #endif
383
384 /***********************************************************************/
385
386 #ifdef CONFIG_SOC_AU1200
387 #define MEM_PHYS_ADDR 0x14000000
388 #define STATIC_MEM_PHYS_ADDR 0x14001000
389 #define AES_PHYS_ADDR 0x10300000
390 #define CIM_PHYS_ADDR 0x14004000
391 #define IC0_PHYS_ADDR 0x10400000
392 #define IC1_PHYS_ADDR 0x11800000
393 #define USBM_PHYS_ADDR 0x14020000
394 #define USBH_PHYS_ADDR 0x14020100
395 #define UART0_PHYS_ADDR 0x11100000
396 #define UART1_PHYS_ADDR 0x11200000
397 #define GPIO2_PHYS_ADDR 0x11700000
398 #define SYS_PHYS_ADDR 0x11900000
399 #define DDMA_PHYS_ADDR 0x14002000
400 #define PSC0_PHYS_ADDR 0x11A00000
401 #define PSC1_PHYS_ADDR 0x11B00000
402 #define SD0_PHYS_ADDR 0x10600000
403 #define SD1_PHYS_ADDR 0x10680000
404 #define LCD_PHYS_ADDR 0x15000000
405 #define SWCNT_PHYS_ADDR 0x1110010C
406 #define MAEFE_PHYS_ADDR 0x14012000
407 #define MAEBE_PHYS_ADDR 0x14010000
408 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
409 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
410 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
411 #endif
412
413
414 /* Static Bus Controller */
415 #define MEM_STCFG0 0xB4001000
416 #define MEM_STTIME0 0xB4001004
417 #define MEM_STADDR0 0xB4001008
418
419 #define MEM_STCFG1 0xB4001010
420 #define MEM_STTIME1 0xB4001014
421 #define MEM_STADDR1 0xB4001018
422
423 #define MEM_STCFG2 0xB4001020
424 #define MEM_STTIME2 0xB4001024
425 #define MEM_STADDR2 0xB4001028
426
427 #define MEM_STCFG3 0xB4001030
428 #define MEM_STTIME3 0xB4001034
429 #define MEM_STADDR3 0xB4001038
430
431 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
432 #define MEM_STNDCTL 0xB4001100
433 #define MEM_STSTAT 0xB4001104
434
435 #define MEM_STNAND_CMD (0x0)
436 #define MEM_STNAND_ADDR (0x4)
437 #define MEM_STNAND_DATA (0x20)
438 #endif
439
440 /* Interrupt Controller 0 */
441 #define IC0_CFG0RD 0xB0400040
442 #define IC0_CFG0SET 0xB0400040
443 #define IC0_CFG0CLR 0xB0400044
444
445 #define IC0_CFG1RD 0xB0400048
446 #define IC0_CFG1SET 0xB0400048
447 #define IC0_CFG1CLR 0xB040004C
448
449 #define IC0_CFG2RD 0xB0400050
450 #define IC0_CFG2SET 0xB0400050
451 #define IC0_CFG2CLR 0xB0400054
452
453 #define IC0_REQ0INT 0xB0400054
454 #define IC0_SRCRD 0xB0400058
455 #define IC0_SRCSET 0xB0400058
456 #define IC0_SRCCLR 0xB040005C
457 #define IC0_REQ1INT 0xB040005C
458
459 #define IC0_ASSIGNRD 0xB0400060
460 #define IC0_ASSIGNSET 0xB0400060
461 #define IC0_ASSIGNCLR 0xB0400064
462
463 #define IC0_WAKERD 0xB0400068
464 #define IC0_WAKESET 0xB0400068
465 #define IC0_WAKECLR 0xB040006C
466
467 #define IC0_MASKRD 0xB0400070
468 #define IC0_MASKSET 0xB0400070
469 #define IC0_MASKCLR 0xB0400074
470
471 #define IC0_RISINGRD 0xB0400078
472 #define IC0_RISINGCLR 0xB0400078
473 #define IC0_FALLINGRD 0xB040007C
474 #define IC0_FALLINGCLR 0xB040007C
475
476 #define IC0_TESTBIT 0xB0400080
477
478 /* Interrupt Controller 1 */
479 #define IC1_CFG0RD 0xB1800040
480 #define IC1_CFG0SET 0xB1800040
481 #define IC1_CFG0CLR 0xB1800044
482
483 #define IC1_CFG1RD 0xB1800048
484 #define IC1_CFG1SET 0xB1800048
485 #define IC1_CFG1CLR 0xB180004C
486
487 #define IC1_CFG2RD 0xB1800050
488 #define IC1_CFG2SET 0xB1800050
489 #define IC1_CFG2CLR 0xB1800054
490
491 #define IC1_REQ0INT 0xB1800054
492 #define IC1_SRCRD 0xB1800058
493 #define IC1_SRCSET 0xB1800058
494 #define IC1_SRCCLR 0xB180005C
495 #define IC1_REQ1INT 0xB180005C
496
497 #define IC1_ASSIGNRD 0xB1800060
498 #define IC1_ASSIGNSET 0xB1800060
499 #define IC1_ASSIGNCLR 0xB1800064
500
501 #define IC1_WAKERD 0xB1800068
502 #define IC1_WAKESET 0xB1800068
503 #define IC1_WAKECLR 0xB180006C
504
505 #define IC1_MASKRD 0xB1800070
506 #define IC1_MASKSET 0xB1800070
507 #define IC1_MASKCLR 0xB1800074
508
509 #define IC1_RISINGRD 0xB1800078
510 #define IC1_RISINGCLR 0xB1800078
511 #define IC1_FALLINGRD 0xB180007C
512 #define IC1_FALLINGCLR 0xB180007C
513
514 #define IC1_TESTBIT 0xB1800080
515
516 /* Interrupt Configuration Modes */
517 #define INTC_INT_DISABLED 0
518 #define INTC_INT_RISE_EDGE 0x1
519 #define INTC_INT_FALL_EDGE 0x2
520 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
521 #define INTC_INT_HIGH_LEVEL 0x5
522 #define INTC_INT_LOW_LEVEL 0x6
523 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
524
525 /* Interrupt Numbers */
526 /* Au1000 */
527 #ifdef CONFIG_SOC_AU1000
528 enum soc_au1000_ints {
529 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
530 AU1000_UART0_INT = AU1000_FIRST_INT,
531 AU1000_UART1_INT, /* au1000 */
532 AU1000_UART2_INT, /* au1000 */
533 AU1000_UART3_INT,
534 AU1000_SSI0_INT, /* au1000 */
535 AU1000_SSI1_INT, /* au1000 */
536 AU1000_DMA_INT_BASE,
537
538 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
539 AU1000_TOY_MATCH0_INT,
540 AU1000_TOY_MATCH1_INT,
541 AU1000_TOY_MATCH2_INT,
542 AU1000_RTC_INT,
543 AU1000_RTC_MATCH0_INT,
544 AU1000_RTC_MATCH1_INT,
545 AU1000_RTC_MATCH2_INT,
546 AU1000_IRDA_TX_INT, /* au1000 */
547 AU1000_IRDA_RX_INT, /* au1000 */
548 AU1000_USB_DEV_REQ_INT,
549 AU1000_USB_DEV_SUS_INT,
550 AU1000_USB_HOST_INT,
551 AU1000_ACSYNC_INT,
552 AU1000_MAC0_DMA_INT,
553 AU1000_MAC1_DMA_INT,
554 AU1000_I2S_UO_INT, /* au1000 */
555 AU1000_AC97C_INT,
556 AU1000_GPIO_0,
557 AU1000_GPIO_1,
558 AU1000_GPIO_2,
559 AU1000_GPIO_3,
560 AU1000_GPIO_4,
561 AU1000_GPIO_5,
562 AU1000_GPIO_6,
563 AU1000_GPIO_7,
564 AU1000_GPIO_8,
565 AU1000_GPIO_9,
566 AU1000_GPIO_10,
567 AU1000_GPIO_11,
568 AU1000_GPIO_12,
569 AU1000_GPIO_13,
570 AU1000_GPIO_14,
571 AU1000_GPIO_15,
572 AU1000_GPIO_16,
573 AU1000_GPIO_17,
574 AU1000_GPIO_18,
575 AU1000_GPIO_19,
576 AU1000_GPIO_20,
577 AU1000_GPIO_21,
578 AU1000_GPIO_22,
579 AU1000_GPIO_23,
580 AU1000_GPIO_24,
581 AU1000_GPIO_25,
582 AU1000_GPIO_26,
583 AU1000_GPIO_27,
584 AU1000_GPIO_28,
585 AU1000_GPIO_29,
586 AU1000_GPIO_30,
587 AU1000_GPIO_31,
588 };
589
590 #define UART0_ADDR 0xB1100000
591 #define UART1_ADDR 0xB1200000
592 #define UART2_ADDR 0xB1300000
593 #define UART3_ADDR 0xB1400000
594
595 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
596 #define USB_HOST_CONFIG 0xB017fffc
597
598 #define AU1000_ETH0_BASE 0xB0500000
599 #define AU1000_ETH1_BASE 0xB0510000
600 #define AU1000_MAC0_ENABLE 0xB0520000
601 #define AU1000_MAC1_ENABLE 0xB0520004
602 #define NUM_ETH_INTERFACES 2
603 #endif /* CONFIG_SOC_AU1000 */
604
605 /* Au1500 */
606 #ifdef CONFIG_SOC_AU1500
607 enum soc_au1500_ints {
608 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
609 AU1500_UART0_INT = AU1500_FIRST_INT,
610 AU1000_PCI_INTA, /* au1500 */
611 AU1000_PCI_INTB, /* au1500 */
612 AU1500_UART3_INT,
613 AU1000_PCI_INTC, /* au1500 */
614 AU1000_PCI_INTD, /* au1500 */
615 AU1000_DMA_INT_BASE,
616
617 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
618 AU1000_TOY_MATCH0_INT,
619 AU1000_TOY_MATCH1_INT,
620 AU1000_TOY_MATCH2_INT,
621 AU1000_RTC_INT,
622 AU1000_RTC_MATCH0_INT,
623 AU1000_RTC_MATCH1_INT,
624 AU1000_RTC_MATCH2_INT,
625 AU1500_PCI_ERR_INT,
626 AU1000_USB_DEV_REQ_INT,
627 AU1000_USB_DEV_SUS_INT,
628 AU1000_USB_HOST_INT,
629 AU1000_ACSYNC_INT,
630 AU1500_MAC0_DMA_INT,
631 AU1500_MAC1_DMA_INT,
632 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
633 AU1000_GPIO_0,
634 AU1000_GPIO_1,
635 AU1000_GPIO_2,
636 AU1000_GPIO_3,
637 AU1000_GPIO_4,
638 AU1000_GPIO_5,
639 AU1000_GPIO_6,
640 AU1000_GPIO_7,
641 AU1000_GPIO_8,
642 AU1000_GPIO_9,
643 AU1000_GPIO_10,
644 AU1000_GPIO_11,
645 AU1000_GPIO_12,
646 AU1000_GPIO_13,
647 AU1000_GPIO_14,
648 AU1000_GPIO_15,
649 AU1500_GPIO_200,
650 AU1500_GPIO_201,
651 AU1500_GPIO_202,
652 AU1500_GPIO_203,
653 AU1500_GPIO_20,
654 AU1500_GPIO_204,
655 AU1500_GPIO_205,
656 AU1500_GPIO_23,
657 AU1500_GPIO_24,
658 AU1500_GPIO_25,
659 AU1500_GPIO_26,
660 AU1500_GPIO_27,
661 AU1500_GPIO_28,
662 AU1500_GPIO_206,
663 AU1500_GPIO_207,
664 AU1500_GPIO_208_215,
665 };
666
667 /* shortcuts */
668 #define INTA AU1000_PCI_INTA
669 #define INTB AU1000_PCI_INTB
670 #define INTC AU1000_PCI_INTC
671 #define INTD AU1000_PCI_INTD
672
673 #define UART0_ADDR 0xB1100000
674 #define UART3_ADDR 0xB1400000
675
676 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
677 #define USB_HOST_CONFIG 0xB017fffc
678
679 #define AU1500_ETH0_BASE 0xB1500000
680 #define AU1500_ETH1_BASE 0xB1510000
681 #define AU1500_MAC0_ENABLE 0xB1520000
682 #define AU1500_MAC1_ENABLE 0xB1520004
683 #define NUM_ETH_INTERFACES 2
684 #endif /* CONFIG_SOC_AU1500 */
685
686 /* Au1100 */
687 #ifdef CONFIG_SOC_AU1100
688 enum soc_au1100_ints {
689 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
690 AU1100_UART0_INT,
691 AU1100_UART1_INT,
692 AU1100_SD_INT,
693 AU1100_UART3_INT,
694 AU1000_SSI0_INT,
695 AU1000_SSI1_INT,
696 AU1000_DMA_INT_BASE,
697
698 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
699 AU1000_TOY_MATCH0_INT,
700 AU1000_TOY_MATCH1_INT,
701 AU1000_TOY_MATCH2_INT,
702 AU1000_RTC_INT,
703 AU1000_RTC_MATCH0_INT,
704 AU1000_RTC_MATCH1_INT,
705 AU1000_RTC_MATCH2_INT,
706 AU1000_IRDA_TX_INT,
707 AU1000_IRDA_RX_INT,
708 AU1000_USB_DEV_REQ_INT,
709 AU1000_USB_DEV_SUS_INT,
710 AU1000_USB_HOST_INT,
711 AU1000_ACSYNC_INT,
712 AU1100_MAC0_DMA_INT,
713 AU1100_GPIO_208_215,
714 AU1100_LCD_INT,
715 AU1000_AC97C_INT,
716 AU1000_GPIO_0,
717 AU1000_GPIO_1,
718 AU1000_GPIO_2,
719 AU1000_GPIO_3,
720 AU1000_GPIO_4,
721 AU1000_GPIO_5,
722 AU1000_GPIO_6,
723 AU1000_GPIO_7,
724 AU1000_GPIO_8,
725 AU1000_GPIO_9,
726 AU1000_GPIO_10,
727 AU1000_GPIO_11,
728 AU1000_GPIO_12,
729 AU1000_GPIO_13,
730 AU1000_GPIO_14,
731 AU1000_GPIO_15,
732 AU1000_GPIO_16,
733 AU1000_GPIO_17,
734 AU1000_GPIO_18,
735 AU1000_GPIO_19,
736 AU1000_GPIO_20,
737 AU1000_GPIO_21,
738 AU1000_GPIO_22,
739 AU1000_GPIO_23,
740 AU1000_GPIO_24,
741 AU1000_GPIO_25,
742 AU1000_GPIO_26,
743 AU1000_GPIO_27,
744 AU1000_GPIO_28,
745 AU1000_GPIO_29,
746 AU1000_GPIO_30,
747 AU1000_GPIO_31,
748 };
749
750 #define UART0_ADDR 0xB1100000
751 #define UART1_ADDR 0xB1200000
752 #define UART3_ADDR 0xB1400000
753
754 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
755 #define USB_HOST_CONFIG 0xB017fffc
756
757 #define AU1100_ETH0_BASE 0xB0500000
758 #define AU1100_MAC0_ENABLE 0xB0520000
759 #define NUM_ETH_INTERFACES 1
760 #endif /* CONFIG_SOC_AU1100 */
761
762 #ifdef CONFIG_SOC_AU1550
763 enum soc_au1550_ints {
764 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
765 AU1550_UART0_INT = AU1550_FIRST_INT,
766 AU1550_PCI_INTA,
767 AU1550_PCI_INTB,
768 AU1550_DDMA_INT,
769 AU1550_CRYPTO_INT,
770 AU1550_PCI_INTC,
771 AU1550_PCI_INTD,
772 AU1550_PCI_RST_INT,
773 AU1550_UART1_INT,
774 AU1550_UART3_INT,
775 AU1550_PSC0_INT,
776 AU1550_PSC1_INT,
777 AU1550_PSC2_INT,
778 AU1550_PSC3_INT,
779 AU1000_TOY_INT,
780 AU1000_TOY_MATCH0_INT,
781 AU1000_TOY_MATCH1_INT,
782 AU1000_TOY_MATCH2_INT,
783 AU1000_RTC_INT,
784 AU1000_RTC_MATCH0_INT,
785 AU1000_RTC_MATCH1_INT,
786 AU1000_RTC_MATCH2_INT,
787
788 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
789 AU1550_USB_DEV_REQ_INT,
790 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
791 AU1550_USB_DEV_SUS_INT,
792 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
793 AU1550_USB_HOST_INT,
794 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
795 AU1550_MAC0_DMA_INT,
796 AU1550_MAC1_DMA_INT,
797 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
798 AU1000_GPIO_1,
799 AU1000_GPIO_2,
800 AU1000_GPIO_3,
801 AU1000_GPIO_4,
802 AU1000_GPIO_5,
803 AU1000_GPIO_6,
804 AU1000_GPIO_7,
805 AU1000_GPIO_8,
806 AU1000_GPIO_9,
807 AU1000_GPIO_10,
808 AU1000_GPIO_11,
809 AU1000_GPIO_12,
810 AU1000_GPIO_13,
811 AU1000_GPIO_14,
812 AU1000_GPIO_15,
813 AU1550_GPIO_200,
814 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
815 AU1500_GPIO_16,
816 AU1500_GPIO_17,
817 AU1500_GPIO_20,
818 AU1500_GPIO_21,
819 AU1500_GPIO_22,
820 AU1500_GPIO_23,
821 AU1500_GPIO_24,
822 AU1500_GPIO_25,
823 AU1500_GPIO_26,
824 AU1500_GPIO_27,
825 AU1500_GPIO_28,
826 AU1500_GPIO_206,
827 AU1500_GPIO_207,
828 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
829 };
830
831 /* shortcuts */
832 #define INTA AU1550_PCI_INTA
833 #define INTB AU1550_PCI_INTB
834 #define INTC AU1550_PCI_INTC
835 #define INTD AU1550_PCI_INTD
836
837 #define UART0_ADDR 0xB1100000
838 #define UART1_ADDR 0xB1200000
839 #define UART3_ADDR 0xB1400000
840
841 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
842 #define USB_OHCI_LEN 0x00060000
843 #define USB_HOST_CONFIG 0xB4027ffc
844
845 #define AU1550_ETH0_BASE 0xB0500000
846 #define AU1550_ETH1_BASE 0xB0510000
847 #define AU1550_MAC0_ENABLE 0xB0520000
848 #define AU1550_MAC1_ENABLE 0xB0520004
849 #define NUM_ETH_INTERFACES 2
850 #endif /* CONFIG_SOC_AU1550 */
851
852 #ifdef CONFIG_SOC_AU1200
853 enum soc_au1200_ints {
854 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
855 AU1200_UART0_INT = AU1200_FIRST_INT,
856 AU1200_SWT_INT,
857 AU1200_SD_INT,
858 AU1200_DDMA_INT,
859 AU1200_MAE_BE_INT,
860 AU1200_GPIO_200,
861 AU1200_GPIO_201,
862 AU1200_GPIO_202,
863 AU1200_UART1_INT,
864 AU1200_MAE_FE_INT,
865 AU1200_PSC0_INT,
866 AU1200_PSC1_INT,
867 AU1200_AES_INT,
868 AU1200_CAMERA_INT,
869 AU1000_TOY_INT,
870 AU1000_TOY_MATCH0_INT,
871 AU1000_TOY_MATCH1_INT,
872 AU1000_TOY_MATCH2_INT,
873 AU1000_RTC_INT,
874 AU1000_RTC_MATCH0_INT,
875 AU1000_RTC_MATCH1_INT,
876 AU1000_RTC_MATCH2_INT,
877
878 AU1200_NAND_INT = AU1200_FIRST_INT + 23,
879 AU1200_GPIO_204,
880 AU1200_GPIO_205,
881 AU1200_GPIO_206,
882 AU1200_GPIO_207,
883 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
884 AU1200_USB_INT,
885 AU1000_USB_HOST_INT = AU1200_USB_INT,
886 AU1200_LCD_INT,
887 AU1200_MAE_BOTH_INT,
888 AU1000_GPIO_0,
889 AU1000_GPIO_1,
890 AU1000_GPIO_2,
891 AU1000_GPIO_3,
892 AU1000_GPIO_4,
893 AU1000_GPIO_5,
894 AU1000_GPIO_6,
895 AU1000_GPIO_7,
896 AU1000_GPIO_8,
897 AU1000_GPIO_9,
898 AU1000_GPIO_10,
899 AU1000_GPIO_11,
900 AU1000_GPIO_12,
901 AU1000_GPIO_13,
902 AU1000_GPIO_14,
903 AU1000_GPIO_15,
904 AU1000_GPIO_16,
905 AU1000_GPIO_17,
906 AU1000_GPIO_18,
907 AU1000_GPIO_19,
908 AU1000_GPIO_20,
909 AU1000_GPIO_21,
910 AU1000_GPIO_22,
911 AU1000_GPIO_23,
912 AU1000_GPIO_24,
913 AU1000_GPIO_25,
914 AU1000_GPIO_26,
915 AU1000_GPIO_27,
916 AU1000_GPIO_28,
917 AU1000_GPIO_29,
918 AU1000_GPIO_30,
919 AU1000_GPIO_31,
920 };
921
922 #define UART0_ADDR 0xB1100000
923 #define UART1_ADDR 0xB1200000
924
925 #define USB_UOC_BASE 0x14020020
926 #define USB_UOC_LEN 0x20
927 #define USB_OHCI_BASE 0x14020100
928 #define USB_OHCI_LEN 0x100
929 #define USB_EHCI_BASE 0x14020200
930 #define USB_EHCI_LEN 0x100
931 #define USB_UDC_BASE 0x14022000
932 #define USB_UDC_LEN 0x2000
933 #define USB_MSR_BASE 0xB4020000
934 #define USB_MSR_MCFG 4
935 #define USBMSRMCFG_OMEMEN 0
936 #define USBMSRMCFG_OBMEN 1
937 #define USBMSRMCFG_EMEMEN 2
938 #define USBMSRMCFG_EBMEN 3
939 #define USBMSRMCFG_DMEMEN 4
940 #define USBMSRMCFG_DBMEN 5
941 #define USBMSRMCFG_GMEMEN 6
942 #define USBMSRMCFG_OHCCLKEN 16
943 #define USBMSRMCFG_EHCCLKEN 17
944 #define USBMSRMCFG_UDCCLKEN 18
945 #define USBMSRMCFG_PHYPLLEN 19
946 #define USBMSRMCFG_RDCOMB 30
947 #define USBMSRMCFG_PFEN 31
948
949 #endif /* CONFIG_SOC_AU1200 */
950
951 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
952 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
953 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
954 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
955
956 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
957 #define INTX 0xFF /* not valid */
958
959 /* Programmable Counters 0 and 1 */
960 #define SYS_BASE 0xB1900000
961 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
962 # define SYS_CNTRL_E1S (1<<23)
963 # define SYS_CNTRL_T1S (1<<20)
964 # define SYS_CNTRL_M21 (1<<19)
965 # define SYS_CNTRL_M11 (1<<18)
966 # define SYS_CNTRL_M01 (1<<17)
967 # define SYS_CNTRL_C1S (1<<16)
968 # define SYS_CNTRL_BP (1<<14)
969 # define SYS_CNTRL_EN1 (1<<13)
970 # define SYS_CNTRL_BT1 (1<<12)
971 # define SYS_CNTRL_EN0 (1<<11)
972 # define SYS_CNTRL_BT0 (1<<10)
973 # define SYS_CNTRL_E0 (1<<8)
974 # define SYS_CNTRL_E0S (1<<7)
975 # define SYS_CNTRL_32S (1<<5)
976 # define SYS_CNTRL_T0S (1<<4)
977 # define SYS_CNTRL_M20 (1<<3)
978 # define SYS_CNTRL_M10 (1<<2)
979 # define SYS_CNTRL_M00 (1<<1)
980 # define SYS_CNTRL_C0S (1<<0)
981
982 /* Programmable Counter 0 Registers */
983 #define SYS_TOYTRIM (SYS_BASE + 0)
984 #define SYS_TOYWRITE (SYS_BASE + 4)
985 #define SYS_TOYMATCH0 (SYS_BASE + 8)
986 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
987 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
988 #define SYS_TOYREAD (SYS_BASE + 0x40)
989
990 /* Programmable Counter 1 Registers */
991 #define SYS_RTCTRIM (SYS_BASE + 0x44)
992 #define SYS_RTCWRITE (SYS_BASE + 0x48)
993 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
994 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
995 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
996 #define SYS_RTCREAD (SYS_BASE + 0x58)
997
998 /* I2S Controller */
999 #define I2S_DATA 0xB1000000
1000 # define I2S_DATA_MASK (0xffffff)
1001 #define I2S_CONFIG 0xB1000004
1002 # define I2S_CONFIG_XU (1<<25)
1003 # define I2S_CONFIG_XO (1<<24)
1004 # define I2S_CONFIG_RU (1<<23)
1005 # define I2S_CONFIG_RO (1<<22)
1006 # define I2S_CONFIG_TR (1<<21)
1007 # define I2S_CONFIG_TE (1<<20)
1008 # define I2S_CONFIG_TF (1<<19)
1009 # define I2S_CONFIG_RR (1<<18)
1010 # define I2S_CONFIG_RE (1<<17)
1011 # define I2S_CONFIG_RF (1<<16)
1012 # define I2S_CONFIG_PD (1<<11)
1013 # define I2S_CONFIG_LB (1<<10)
1014 # define I2S_CONFIG_IC (1<<9)
1015 # define I2S_CONFIG_FM_BIT 7
1016 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1017 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1018 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1019 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1020 # define I2S_CONFIG_TN (1<<6)
1021 # define I2S_CONFIG_RN (1<<5)
1022 # define I2S_CONFIG_SZ_BIT 0
1023 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1024
1025 #define I2S_CONTROL 0xB1000008
1026 # define I2S_CONTROL_D (1<<1)
1027 # define I2S_CONTROL_CE (1<<0)
1028
1029 /* USB Host Controller */
1030 #ifndef USB_OHCI_LEN
1031 #define USB_OHCI_LEN 0x00100000
1032 #endif
1033
1034 #ifndef CONFIG_SOC_AU1200
1035
1036 /* USB Device Controller */
1037 #define USBD_EP0RD 0xB0200000
1038 #define USBD_EP0WR 0xB0200004
1039 #define USBD_EP2WR 0xB0200008
1040 #define USBD_EP3WR 0xB020000C
1041 #define USBD_EP4RD 0xB0200010
1042 #define USBD_EP5RD 0xB0200014
1043 #define USBD_INTEN 0xB0200018
1044 #define USBD_INTSTAT 0xB020001C
1045 # define USBDEV_INT_SOF (1<<12)
1046 # define USBDEV_INT_HF_BIT 6
1047 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1048 # define USBDEV_INT_CMPLT_BIT 0
1049 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1050 #define USBD_CONFIG 0xB0200020
1051 #define USBD_EP0CS 0xB0200024
1052 #define USBD_EP2CS 0xB0200028
1053 #define USBD_EP3CS 0xB020002C
1054 #define USBD_EP4CS 0xB0200030
1055 #define USBD_EP5CS 0xB0200034
1056 # define USBDEV_CS_SU (1<<14)
1057 # define USBDEV_CS_NAK (1<<13)
1058 # define USBDEV_CS_ACK (1<<12)
1059 # define USBDEV_CS_BUSY (1<<11)
1060 # define USBDEV_CS_TSIZE_BIT 1
1061 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1062 # define USBDEV_CS_STALL (1<<0)
1063 #define USBD_EP0RDSTAT 0xB0200040
1064 #define USBD_EP0WRSTAT 0xB0200044
1065 #define USBD_EP2WRSTAT 0xB0200048
1066 #define USBD_EP3WRSTAT 0xB020004C
1067 #define USBD_EP4RDSTAT 0xB0200050
1068 #define USBD_EP5RDSTAT 0xB0200054
1069 # define USBDEV_FSTAT_FLUSH (1<<6)
1070 # define USBDEV_FSTAT_UF (1<<5)
1071 # define USBDEV_FSTAT_OF (1<<4)
1072 # define USBDEV_FSTAT_FCNT_BIT 0
1073 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1074 #define USBD_ENABLE 0xB0200058
1075 # define USBDEV_ENABLE (1<<1)
1076 # define USBDEV_CE (1<<0)
1077
1078 #endif /* !CONFIG_SOC_AU1200 */
1079
1080 /* Ethernet Controllers */
1081
1082 /* 4 byte offsets from AU1000_ETH_BASE */
1083 #define MAC_CONTROL 0x0
1084 # define MAC_RX_ENABLE (1<<2)
1085 # define MAC_TX_ENABLE (1<<3)
1086 # define MAC_DEF_CHECK (1<<5)
1087 # define MAC_SET_BL(X) (((X)&0x3)<<6)
1088 # define MAC_AUTO_PAD (1<<8)
1089 # define MAC_DISABLE_RETRY (1<<10)
1090 # define MAC_DISABLE_BCAST (1<<11)
1091 # define MAC_LATE_COL (1<<12)
1092 # define MAC_HASH_MODE (1<<13)
1093 # define MAC_HASH_ONLY (1<<15)
1094 # define MAC_PASS_ALL (1<<16)
1095 # define MAC_INVERSE_FILTER (1<<17)
1096 # define MAC_PROMISCUOUS (1<<18)
1097 # define MAC_PASS_ALL_MULTI (1<<19)
1098 # define MAC_FULL_DUPLEX (1<<20)
1099 # define MAC_NORMAL_MODE 0
1100 # define MAC_INT_LOOPBACK (1<<21)
1101 # define MAC_EXT_LOOPBACK (1<<22)
1102 # define MAC_DISABLE_RX_OWN (1<<23)
1103 # define MAC_BIG_ENDIAN (1<<30)
1104 # define MAC_RX_ALL (1<<31)
1105 #define MAC_ADDRESS_HIGH 0x4
1106 #define MAC_ADDRESS_LOW 0x8
1107 #define MAC_MCAST_HIGH 0xC
1108 #define MAC_MCAST_LOW 0x10
1109 #define MAC_MII_CNTRL 0x14
1110 # define MAC_MII_BUSY (1<<0)
1111 # define MAC_MII_READ 0
1112 # define MAC_MII_WRITE (1<<1)
1113 # define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1114 # define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1115 #define MAC_MII_DATA 0x18
1116 #define MAC_FLOW_CNTRL 0x1C
1117 # define MAC_FLOW_CNTRL_BUSY (1<<0)
1118 # define MAC_FLOW_CNTRL_ENABLE (1<<1)
1119 # define MAC_PASS_CONTROL (1<<2)
1120 # define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1121 #define MAC_VLAN1_TAG 0x20
1122 #define MAC_VLAN2_TAG 0x24
1123
1124 /* Ethernet Controller Enable */
1125
1126 # define MAC_EN_CLOCK_ENABLE (1<<0)
1127 # define MAC_EN_RESET0 (1<<1)
1128 # define MAC_EN_TOSS (0<<2)
1129 # define MAC_EN_CACHEABLE (1<<3)
1130 # define MAC_EN_RESET1 (1<<4)
1131 # define MAC_EN_RESET2 (1<<5)
1132 # define MAC_DMA_RESET (1<<6)
1133
1134 /* Ethernet Controller DMA Channels */
1135
1136 #define MAC0_TX_DMA_ADDR 0xB4004000
1137 #define MAC1_TX_DMA_ADDR 0xB4004200
1138 /* offsets from MAC_TX_RING_ADDR address */
1139 #define MAC_TX_BUFF0_STATUS 0x0
1140 # define TX_FRAME_ABORTED (1<<0)
1141 # define TX_JAB_TIMEOUT (1<<1)
1142 # define TX_NO_CARRIER (1<<2)
1143 # define TX_LOSS_CARRIER (1<<3)
1144 # define TX_EXC_DEF (1<<4)
1145 # define TX_LATE_COLL_ABORT (1<<5)
1146 # define TX_EXC_COLL (1<<6)
1147 # define TX_UNDERRUN (1<<7)
1148 # define TX_DEFERRED (1<<8)
1149 # define TX_LATE_COLL (1<<9)
1150 # define TX_COLL_CNT_MASK (0xF<<10)
1151 # define TX_PKT_RETRY (1<<31)
1152 #define MAC_TX_BUFF0_ADDR 0x4
1153 # define TX_DMA_ENABLE (1<<0)
1154 # define TX_T_DONE (1<<1)
1155 # define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1156 #define MAC_TX_BUFF0_LEN 0x8
1157 #define MAC_TX_BUFF1_STATUS 0x10
1158 #define MAC_TX_BUFF1_ADDR 0x14
1159 #define MAC_TX_BUFF1_LEN 0x18
1160 #define MAC_TX_BUFF2_STATUS 0x20
1161 #define MAC_TX_BUFF2_ADDR 0x24
1162 #define MAC_TX_BUFF2_LEN 0x28
1163 #define MAC_TX_BUFF3_STATUS 0x30
1164 #define MAC_TX_BUFF3_ADDR 0x34
1165 #define MAC_TX_BUFF3_LEN 0x38
1166
1167 #define MAC0_RX_DMA_ADDR 0xB4004100
1168 #define MAC1_RX_DMA_ADDR 0xB4004300
1169 /* offsets from MAC_RX_RING_ADDR */
1170 #define MAC_RX_BUFF0_STATUS 0x0
1171 # define RX_FRAME_LEN_MASK 0x3fff
1172 # define RX_WDOG_TIMER (1<<14)
1173 # define RX_RUNT (1<<15)
1174 # define RX_OVERLEN (1<<16)
1175 # define RX_COLL (1<<17)
1176 # define RX_ETHER (1<<18)
1177 # define RX_MII_ERROR (1<<19)
1178 # define RX_DRIBBLING (1<<20)
1179 # define RX_CRC_ERROR (1<<21)
1180 # define RX_VLAN1 (1<<22)
1181 # define RX_VLAN2 (1<<23)
1182 # define RX_LEN_ERROR (1<<24)
1183 # define RX_CNTRL_FRAME (1<<25)
1184 # define RX_U_CNTRL_FRAME (1<<26)
1185 # define RX_MCAST_FRAME (1<<27)
1186 # define RX_BCAST_FRAME (1<<28)
1187 # define RX_FILTER_FAIL (1<<29)
1188 # define RX_PACKET_FILTER (1<<30)
1189 # define RX_MISSED_FRAME (1<<31)
1190
1191 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1192 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1193 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1194 #define MAC_RX_BUFF0_ADDR 0x4
1195 # define RX_DMA_ENABLE (1<<0)
1196 # define RX_T_DONE (1<<1)
1197 # define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1198 # define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1199 #define MAC_RX_BUFF1_STATUS 0x10
1200 #define MAC_RX_BUFF1_ADDR 0x14
1201 #define MAC_RX_BUFF2_STATUS 0x20
1202 #define MAC_RX_BUFF2_ADDR 0x24
1203 #define MAC_RX_BUFF3_STATUS 0x30
1204 #define MAC_RX_BUFF3_ADDR 0x34
1205
1206
1207 /* UARTS 0-3 */
1208 #define UART_BASE UART0_ADDR
1209 #ifdef CONFIG_SOC_AU1200
1210 #define UART_DEBUG_BASE UART1_ADDR
1211 #else
1212 #define UART_DEBUG_BASE UART3_ADDR
1213 #endif
1214
1215 #define UART_RX 0 /* Receive buffer */
1216 #define UART_TX 4 /* Transmit buffer */
1217 #define UART_IER 8 /* Interrupt Enable Register */
1218 #define UART_IIR 0xC /* Interrupt ID Register */
1219 #define UART_FCR 0x10 /* FIFO Control Register */
1220 #define UART_LCR 0x14 /* Line Control Register */
1221 #define UART_MCR 0x18 /* Modem Control Register */
1222 #define UART_LSR 0x1C /* Line Status Register */
1223 #define UART_MSR 0x20 /* Modem Status Register */
1224 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1225 #define UART_MOD_CNTRL 0x100 /* Module Control */
1226
1227 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1228 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1229 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1230 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1231 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1232 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1233 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1234 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1235 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1236 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1237 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1238 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1239 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1240
1241 /*
1242 * These are the definitions for the Line Control Register
1243 */
1244 #define UART_LCR_SBC 0x40 /* Set break control */
1245 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1246 #define UART_LCR_EPAR 0x10 /* Even parity select */
1247 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1248 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1249 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1250 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1251 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1252 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1253
1254 /*
1255 * These are the definitions for the Line Status Register
1256 */
1257 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1258 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1259 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1260 #define UART_LSR_FE 0x08 /* Frame error indicator */
1261 #define UART_LSR_PE 0x04 /* Parity error indicator */
1262 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1263 #define UART_LSR_DR 0x01 /* Receiver data ready */
1264
1265 /*
1266 * These are the definitions for the Interrupt Identification Register
1267 */
1268 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1269 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1270 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1271 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1272 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1273 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1274
1275 /*
1276 * These are the definitions for the Interrupt Enable Register
1277 */
1278 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1279 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1280 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1281 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1282
1283 /*
1284 * These are the definitions for the Modem Control Register
1285 */
1286 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1287 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1288 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1289 #define UART_MCR_RTS 0x02 /* RTS complement */
1290 #define UART_MCR_DTR 0x01 /* DTR complement */
1291
1292 /*
1293 * These are the definitions for the Modem Status Register
1294 */
1295 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1296 #define UART_MSR_RI 0x40 /* Ring Indicator */
1297 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1298 #define UART_MSR_CTS 0x10 /* Clear to Send */
1299 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1300 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1301 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1302 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1303 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1304
1305
1306
1307 /* SSIO */
1308 #define SSI0_STATUS 0xB1600000
1309 # define SSI_STATUS_BF (1<<4)
1310 # define SSI_STATUS_OF (1<<3)
1311 # define SSI_STATUS_UF (1<<2)
1312 # define SSI_STATUS_D (1<<1)
1313 # define SSI_STATUS_B (1<<0)
1314 #define SSI0_INT 0xB1600004
1315 # define SSI_INT_OI (1<<3)
1316 # define SSI_INT_UI (1<<2)
1317 # define SSI_INT_DI (1<<1)
1318 #define SSI0_INT_ENABLE 0xB1600008
1319 # define SSI_INTE_OIE (1<<3)
1320 # define SSI_INTE_UIE (1<<2)
1321 # define SSI_INTE_DIE (1<<1)
1322 #define SSI0_CONFIG 0xB1600020
1323 # define SSI_CONFIG_AO (1<<24)
1324 # define SSI_CONFIG_DO (1<<23)
1325 # define SSI_CONFIG_ALEN_BIT 20
1326 # define SSI_CONFIG_ALEN_MASK (0x7<<20)
1327 # define SSI_CONFIG_DLEN_BIT 16
1328 # define SSI_CONFIG_DLEN_MASK (0x7<<16)
1329 # define SSI_CONFIG_DD (1<<11)
1330 # define SSI_CONFIG_AD (1<<10)
1331 # define SSI_CONFIG_BM_BIT 8
1332 # define SSI_CONFIG_BM_MASK (0x3<<8)
1333 # define SSI_CONFIG_CE (1<<7)
1334 # define SSI_CONFIG_DP (1<<6)
1335 # define SSI_CONFIG_DL (1<<5)
1336 # define SSI_CONFIG_EP (1<<4)
1337 #define SSI0_ADATA 0xB1600024
1338 # define SSI_AD_D (1<<24)
1339 # define SSI_AD_ADDR_BIT 16
1340 # define SSI_AD_ADDR_MASK (0xff<<16)
1341 # define SSI_AD_DATA_BIT 0
1342 # define SSI_AD_DATA_MASK (0xfff<<0)
1343 #define SSI0_CLKDIV 0xB1600028
1344 #define SSI0_CONTROL 0xB1600100
1345 # define SSI_CONTROL_CD (1<<1)
1346 # define SSI_CONTROL_E (1<<0)
1347
1348 /* SSI1 */
1349 #define SSI1_STATUS 0xB1680000
1350 #define SSI1_INT 0xB1680004
1351 #define SSI1_INT_ENABLE 0xB1680008
1352 #define SSI1_CONFIG 0xB1680020
1353 #define SSI1_ADATA 0xB1680024
1354 #define SSI1_CLKDIV 0xB1680028
1355 #define SSI1_ENABLE 0xB1680100
1356
1357 /*
1358 * Register content definitions
1359 */
1360 #define SSI_STATUS_BF (1<<4)
1361 #define SSI_STATUS_OF (1<<3)
1362 #define SSI_STATUS_UF (1<<2)
1363 #define SSI_STATUS_D (1<<1)
1364 #define SSI_STATUS_B (1<<0)
1365
1366 /* SSI_INT */
1367 #define SSI_INT_OI (1<<3)
1368 #define SSI_INT_UI (1<<2)
1369 #define SSI_INT_DI (1<<1)
1370
1371 /* SSI_INTEN */
1372 #define SSI_INTEN_OIE (1<<3)
1373 #define SSI_INTEN_UIE (1<<2)
1374 #define SSI_INTEN_DIE (1<<1)
1375
1376 #define SSI_CONFIG_AO (1<<24)
1377 #define SSI_CONFIG_DO (1<<23)
1378 #define SSI_CONFIG_ALEN (7<<20)
1379 #define SSI_CONFIG_DLEN (15<<16)
1380 #define SSI_CONFIG_DD (1<<11)
1381 #define SSI_CONFIG_AD (1<<10)
1382 #define SSI_CONFIG_BM (3<<8)
1383 #define SSI_CONFIG_CE (1<<7)
1384 #define SSI_CONFIG_DP (1<<6)
1385 #define SSI_CONFIG_DL (1<<5)
1386 #define SSI_CONFIG_EP (1<<4)
1387 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
1388 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
1389 #define SSI_CONFIG_BM_HI (0<<8)
1390 #define SSI_CONFIG_BM_LO (1<<8)
1391 #define SSI_CONFIG_BM_CY (2<<8)
1392
1393 #define SSI_ADATA_D (1<<24)
1394 #define SSI_ADATA_ADDR (0xFF<<16)
1395 #define SSI_ADATA_DATA (0x0FFF)
1396 #define SSI_ADATA_ADDR_N(N) (N<<16)
1397
1398 #define SSI_ENABLE_CD (1<<1)
1399 #define SSI_ENABLE_E (1<<0)
1400
1401
1402 /* IrDA Controller */
1403 #define IRDA_BASE 0xB0300000
1404 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
1405 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
1406 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
1407 #define IR_RING_SIZE (IRDA_BASE+0x0C)
1408 #define IR_RING_PROMPT (IRDA_BASE+0x10)
1409 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1410 #define IR_INT_CLEAR (IRDA_BASE+0x18)
1411 #define IR_CONFIG_1 (IRDA_BASE+0x20)
1412 # define IR_RX_INVERT_LED (1<<0)
1413 # define IR_TX_INVERT_LED (1<<1)
1414 # define IR_ST (1<<2)
1415 # define IR_SF (1<<3)
1416 # define IR_SIR (1<<4)
1417 # define IR_MIR (1<<5)
1418 # define IR_FIR (1<<6)
1419 # define IR_16CRC (1<<7)
1420 # define IR_TD (1<<8)
1421 # define IR_RX_ALL (1<<9)
1422 # define IR_DMA_ENABLE (1<<10)
1423 # define IR_RX_ENABLE (1<<11)
1424 # define IR_TX_ENABLE (1<<12)
1425 # define IR_LOOPBACK (1<<14)
1426 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1427 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1428 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
1429 #define IR_ENABLE (IRDA_BASE+0x28)
1430 # define IR_RX_STATUS (1<<9)
1431 # define IR_TX_STATUS (1<<10)
1432 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1433 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1434 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1435 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1436 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
1437 # define IR_MODE_INV (1<<0)
1438 # define IR_ONE_PIN (1<<1)
1439 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1440
1441 /* GPIO */
1442 #define SYS_PINFUNC 0xB190002C
1443 # define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1444 # define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1445 # define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1446 # define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1447 # define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1448 # define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1449 # define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1450 # define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1451 # define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1452 # define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1453 # define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1454 # define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1455 # define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1456 # define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1457 # define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1458 # define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1459
1460 /* Au1100 Only */
1461 # define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1462 # define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1463 # define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1464 # define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1465
1466 /* Au1550 Only. Redefines lots of pins */
1467 # define SYS_PF_PSC2_MASK (7 << 17)
1468 # define SYS_PF_PSC2_AC97 (0)
1469 # define SYS_PF_PSC2_SPI (0)
1470 # define SYS_PF_PSC2_I2S (1 << 17)
1471 # define SYS_PF_PSC2_SMBUS (3 << 17)
1472 # define SYS_PF_PSC2_GPIO (7 << 17)
1473 # define SYS_PF_PSC3_MASK (7 << 20)
1474 # define SYS_PF_PSC3_AC97 (0)
1475 # define SYS_PF_PSC3_SPI (0)
1476 # define SYS_PF_PSC3_I2S (1 << 20)
1477 # define SYS_PF_PSC3_SMBUS (3 << 20)
1478 # define SYS_PF_PSC3_GPIO (7 << 20)
1479 # define SYS_PF_PSC1_S1 (1 << 1)
1480 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1481
1482 /* Au1200 Only */
1483 #ifdef CONFIG_SOC_AU1200
1484 #define SYS_PINFUNC_DMA (1<<31)
1485 #define SYS_PINFUNC_S0A (1<<30)
1486 #define SYS_PINFUNC_S1A (1<<29)
1487 #define SYS_PINFUNC_LP0 (1<<28)
1488 #define SYS_PINFUNC_LP1 (1<<27)
1489 #define SYS_PINFUNC_LD16 (1<<26)
1490 #define SYS_PINFUNC_LD8 (1<<25)
1491 #define SYS_PINFUNC_LD1 (1<<24)
1492 #define SYS_PINFUNC_LD0 (1<<23)
1493 #define SYS_PINFUNC_P1A (3<<21)
1494 #define SYS_PINFUNC_P1B (1<<20)
1495 #define SYS_PINFUNC_FS3 (1<<19)
1496 #define SYS_PINFUNC_P0A (3<<17)
1497 #define SYS_PINFUNC_CS (1<<16)
1498 #define SYS_PINFUNC_CIM (1<<15)
1499 #define SYS_PINFUNC_P1C (1<<14)
1500 #define SYS_PINFUNC_U1T (1<<12)
1501 #define SYS_PINFUNC_U1R (1<<11)
1502 #define SYS_PINFUNC_EX1 (1<<10)
1503 #define SYS_PINFUNC_EX0 (1<<9)
1504 #define SYS_PINFUNC_U0R (1<<8)
1505 #define SYS_PINFUNC_MC (1<<7)
1506 #define SYS_PINFUNC_S0B (1<<6)
1507 #define SYS_PINFUNC_S0C (1<<5)
1508 #define SYS_PINFUNC_P0B (1<<4)
1509 #define SYS_PINFUNC_U0T (1<<3)
1510 #define SYS_PINFUNC_S1B (1<<2)
1511 #endif
1512
1513 #define SYS_TRIOUTRD 0xB1900100
1514 #define SYS_TRIOUTCLR 0xB1900100
1515 #define SYS_OUTPUTRD 0xB1900108
1516 #define SYS_OUTPUTSET 0xB1900108
1517 #define SYS_OUTPUTCLR 0xB190010C
1518 #define SYS_PINSTATERD 0xB1900110
1519 #define SYS_PININPUTEN 0xB1900110
1520
1521 /* GPIO2, Au1500, Au1550 only */
1522 #define GPIO2_BASE 0xB1700000
1523 #define GPIO2_DIR (GPIO2_BASE + 0)
1524 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1525 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1526 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1527 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1528
1529 /* Power Management */
1530 #define SYS_SCRATCH0 0xB1900018
1531 #define SYS_SCRATCH1 0xB190001C
1532 #define SYS_WAKEMSK 0xB1900034
1533 #define SYS_ENDIAN 0xB1900038
1534 #define SYS_POWERCTRL 0xB190003C
1535 #define SYS_WAKESRC 0xB190005C
1536 #define SYS_SLPPWR 0xB1900078
1537 #define SYS_SLEEP 0xB190007C
1538
1539 /* Clock Controller */
1540 #define SYS_FREQCTRL0 0xB1900020
1541 # define SYS_FC_FRDIV2_BIT 22
1542 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1543 # define SYS_FC_FE2 (1<<21)
1544 # define SYS_FC_FS2 (1<<20)
1545 # define SYS_FC_FRDIV1_BIT 12
1546 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1547 # define SYS_FC_FE1 (1<<11)
1548 # define SYS_FC_FS1 (1<<10)
1549 # define SYS_FC_FRDIV0_BIT 2
1550 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1551 # define SYS_FC_FE0 (1<<1)
1552 # define SYS_FC_FS0 (1<<0)
1553 #define SYS_FREQCTRL1 0xB1900024
1554 # define SYS_FC_FRDIV5_BIT 22
1555 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1556 # define SYS_FC_FE5 (1<<21)
1557 # define SYS_FC_FS5 (1<<20)
1558 # define SYS_FC_FRDIV4_BIT 12
1559 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1560 # define SYS_FC_FE4 (1<<11)
1561 # define SYS_FC_FS4 (1<<10)
1562 # define SYS_FC_FRDIV3_BIT 2
1563 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1564 # define SYS_FC_FE3 (1<<1)
1565 # define SYS_FC_FS3 (1<<0)
1566 #define SYS_CLKSRC 0xB1900028
1567 # define SYS_CS_ME1_BIT 27
1568 # define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1569 # define SYS_CS_DE1 (1<<26)
1570 # define SYS_CS_CE1 (1<<25)
1571 # define SYS_CS_ME0_BIT 22
1572 # define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1573 # define SYS_CS_DE0 (1<<21)
1574 # define SYS_CS_CE0 (1<<20)
1575 # define SYS_CS_MI2_BIT 17
1576 # define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1577 # define SYS_CS_DI2 (1<<16)
1578 # define SYS_CS_CI2 (1<<15)
1579 #ifdef CONFIG_SOC_AU1100
1580 # define SYS_CS_ML_BIT 7
1581 # define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1582 # define SYS_CS_DL (1<<6)
1583 # define SYS_CS_CL (1<<5)
1584 #else
1585 # define SYS_CS_MUH_BIT 12
1586 # define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1587 # define SYS_CS_DUH (1<<11)
1588 # define SYS_CS_CUH (1<<10)
1589 # define SYS_CS_MUD_BIT 7
1590 # define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1591 # define SYS_CS_DUD (1<<6)
1592 # define SYS_CS_CUD (1<<5)
1593 #endif
1594 # define SYS_CS_MIR_BIT 2
1595 # define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1596 # define SYS_CS_DIR (1<<1)
1597 # define SYS_CS_CIR (1<<0)
1598
1599 # define SYS_CS_MUX_AUX 0x1
1600 # define SYS_CS_MUX_FQ0 0x2
1601 # define SYS_CS_MUX_FQ1 0x3
1602 # define SYS_CS_MUX_FQ2 0x4
1603 # define SYS_CS_MUX_FQ3 0x5
1604 # define SYS_CS_MUX_FQ4 0x6
1605 # define SYS_CS_MUX_FQ5 0x7
1606 #define SYS_CPUPLL 0xB1900060
1607 #define SYS_AUXPLL 0xB1900064
1608
1609 /* AC97 Controller */
1610 #define AC97C_CONFIG 0xB0000000
1611 # define AC97C_RECV_SLOTS_BIT 13
1612 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1613 # define AC97C_XMIT_SLOTS_BIT 3
1614 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1615 # define AC97C_SG (1<<2)
1616 # define AC97C_SYNC (1<<1)
1617 # define AC97C_RESET (1<<0)
1618 #define AC97C_STATUS 0xB0000004
1619 # define AC97C_XU (1<<11)
1620 # define AC97C_XO (1<<10)
1621 # define AC97C_RU (1<<9)
1622 # define AC97C_RO (1<<8)
1623 # define AC97C_READY (1<<7)
1624 # define AC97C_CP (1<<6)
1625 # define AC97C_TR (1<<5)
1626 # define AC97C_TE (1<<4)
1627 # define AC97C_TF (1<<3)
1628 # define AC97C_RR (1<<2)
1629 # define AC97C_RE (1<<1)
1630 # define AC97C_RF (1<<0)
1631 #define AC97C_DATA 0xB0000008
1632 #define AC97C_CMD 0xB000000C
1633 # define AC97C_WD_BIT 16
1634 # define AC97C_READ (1<<7)
1635 # define AC97C_INDEX_MASK 0x7f
1636 #define AC97C_CNTRL 0xB0000010
1637 # define AC97C_RS (1<<1)
1638 # define AC97C_CE (1<<0)
1639
1640
1641 /* Secure Digital (SD) Controller */
1642 #define SD0_XMIT_FIFO 0xB0600000
1643 #define SD0_RECV_FIFO 0xB0600004
1644 #define SD1_XMIT_FIFO 0xB0680000
1645 #define SD1_RECV_FIFO 0xB0680004
1646
1647 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1648 /* Au1500 PCI Controller */
1649 #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1650 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1651 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1652 # define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1653 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1654 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1655 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1656 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1657 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1658 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1659 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1660 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1661 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1662 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1663 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1664 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1665
1666 #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1667
1668 /* All of our structures, like pci resource, have 32 bit members.
1669 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1670 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1671 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1672 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1673 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1674 * ourselves and then adjust the device's resources.
1675 */
1676 #define Au1500_EXT_CFG 0x600000000ULL
1677 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1678 #define Au1500_PCI_IO_START 0x500000000ULL
1679 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1680 #define Au1500_PCI_MEM_START 0x440000000ULL
1681 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1682
1683 #define PCI_IO_START 0x00001000
1684 #define PCI_IO_END 0x000FFFFF
1685 #define PCI_MEM_START 0x40000000
1686 #define PCI_MEM_END 0x4FFFFFFF
1687
1688 #define PCI_FIRST_DEVFN (0<<3)
1689 #define PCI_LAST_DEVFN (19<<3)
1690
1691 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1692 #define IOPORT_RESOURCE_END 0xffffffff
1693 #define IOMEM_RESOURCE_START 0x10000000
1694 #define IOMEM_RESOURCE_END 0xffffffff
1695
1696 /*
1697 * Borrowed from the PPC arch:
1698 * The following macro is used to lookup irqs in a standard table
1699 * format for those PPC systems that do not already have PCI
1700 * interrupts properly routed.
1701 */
1702 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1703 #define PCI_IRQ_TABLE_LOOKUP \
1704 ({ long _ctl_ = -1; \
1705 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1706 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1707 _ctl_; })
1708
1709
1710 #else /* Au1000 and Au1100 and Au1200 */
1711
1712 /* don't allow any legacy ports probing */
1713 #define IOPORT_RESOURCE_START 0x10000000
1714 #define IOPORT_RESOURCE_END 0xffffffff
1715 #define IOMEM_RESOURCE_START 0x10000000
1716 #define IOMEM_RESOURCE_END 0xffffffff
1717
1718 #define PCI_IO_START 0
1719 #define PCI_IO_END 0
1720 #define PCI_MEM_START 0
1721 #define PCI_MEM_END 0
1722 #define PCI_FIRST_DEVFN 0
1723 #define PCI_LAST_DEVFN 0
1724
1725 #endif
1726
1727 #ifndef _LANGUAGE_ASSEMBLY
1728 typedef volatile struct
1729 {
1730 /* 0x0000 */ u32 toytrim;
1731 /* 0x0004 */ u32 toywrite;
1732 /* 0x0008 */ u32 toymatch0;
1733 /* 0x000C */ u32 toymatch1;
1734 /* 0x0010 */ u32 toymatch2;
1735 /* 0x0014 */ u32 cntrctrl;
1736 /* 0x0018 */ u32 scratch0;
1737 /* 0x001C */ u32 scratch1;
1738 /* 0x0020 */ u32 freqctrl0;
1739 /* 0x0024 */ u32 freqctrl1;
1740 /* 0x0028 */ u32 clksrc;
1741 /* 0x002C */ u32 pinfunc;
1742 /* 0x0030 */ u32 reserved0;
1743 /* 0x0034 */ u32 wakemsk;
1744 /* 0x0038 */ u32 endian;
1745 /* 0x003C */ u32 powerctrl;
1746 /* 0x0040 */ u32 toyread;
1747 /* 0x0044 */ u32 rtctrim;
1748 /* 0x0048 */ u32 rtcwrite;
1749 /* 0x004C */ u32 rtcmatch0;
1750 /* 0x0050 */ u32 rtcmatch1;
1751 /* 0x0054 */ u32 rtcmatch2;
1752 /* 0x0058 */ u32 rtcread;
1753 /* 0x005C */ u32 wakesrc;
1754 /* 0x0060 */ u32 cpupll;
1755 /* 0x0064 */ u32 auxpll;
1756 /* 0x0068 */ u32 reserved1;
1757 /* 0x006C */ u32 reserved2;
1758 /* 0x0070 */ u32 reserved3;
1759 /* 0x0074 */ u32 reserved4;
1760 /* 0x0078 */ u32 slppwr;
1761 /* 0x007C */ u32 sleep;
1762 /* 0x0080 */ u32 reserved5[32];
1763 /* 0x0100 */ u32 trioutrd;
1764 #define trioutclr trioutrd
1765 /* 0x0104 */ u32 reserved6;
1766 /* 0x0108 */ u32 outputrd;
1767 #define outputset outputrd
1768 /* 0x010C */ u32 outputclr;
1769 /* 0x0110 */ u32 pinstaterd;
1770 #define pininputen pinstaterd
1771
1772 } AU1X00_SYS;
1773
1774 static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1775
1776 #endif
1777 /* Processor information base on prid.
1778 * Copied from PowerPC.
1779 */
1780 #ifndef _LANGUAGE_ASSEMBLY
1781 struct cpu_spec {
1782 /* CPU is matched via (PRID & prid_mask) == prid_value */
1783 unsigned int prid_mask;
1784 unsigned int prid_value;
1785
1786 char *cpu_name;
1787 unsigned char cpu_od; /* Set Config[OD] */
1788 unsigned char cpu_bclk; /* Enable BCLK switching */
1789 };
1790
1791 extern struct cpu_spec cpu_specs[];
1792 extern struct cpu_spec *cur_cpu_spec[];
1793 #endif
1794
1795 #endif
1796
WRT350N Kernel Patches