include/asm-mips/mach-au1x00/au1xxx_ide.h

   1 /*
   2  * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   6  *
   7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   8  *
   9  * This program is free software; you can redistribute it and/or modify it under
  10  * the terms of the GNU General Public License as published by the Free Software
  11  * Foundation; either version 2 of the License, or (at your option) any later
  12  * version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  23  * POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the GNU General Public License along with
  26  * this program; if not, write to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  30  *       Interface and Linux Device Driver" Application Note.
  31  */
  32
  33 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
  34         #define DMA_WAIT_TIMEOUT        100
  35         #define NUM_DESCRIPTORS         PRD_ENTRIES
  36 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
  37         #define NUM_DESCRIPTORS         2
  38 #endif
  39
  40 #ifndef AU1XXX_ATA_RQSIZE
  41         #define AU1XXX_ATA_RQSIZE       128
  42 #endif
  43
  44 /* Disable Burstable-Support for DBDMA */
  45 #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
  46         #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
  47 #endif
  48
  49 #ifdef CONFIG_PM
  50 /*
  51 * This will enable the device to be powered up when write() or read()
  52 * is called. If this is not defined, the driver will return -EBUSY.
  53 */
  54 #define WAKE_ON_ACCESS 1
  55
  56 typedef struct
  57 {
  58         spinlock_t         lock;       /* Used to block on state transitions */
  59         au1xxx_power_dev_t *dev;       /* Power Managers device structure */
  60         unsigned           stopped;    /* USed to signaling device is stopped */
  61 } pm_state;
  62 #endif
  63
  64
  65 typedef struct
  66 {
  67         u32                     tx_dev_id, rx_dev_id, target_dev_id;
  68         u32                     tx_chan, rx_chan;
  69         void                    *tx_desc_head, *rx_desc_head;
  70         ide_hwif_t              *hwif;
  71 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
  72         ide_drive_t             *drive;
  73         u8                      white_list, black_list;
  74         struct dbdma_cmd        *dma_table_cpu;
  75         dma_addr_t              dma_table_dma;
  76 #endif
  77         int                     irq;
  78         u32                     regbase;
  79 #ifdef CONFIG_PM
  80         pm_state                pm;
  81 #endif
  82 } _auide_hwif;
  83
  84 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
  85 /* HD white list */
  86 static const struct drive_list_entry dma_white_list [] = {
  87 /*
  88  * Hitachi
  89  */
  90         { "HITACHI_DK14FA-20"    ,       NULL            },
  91         { "HTS726060M9AT00"      ,       NULL            },
  92 /*
  93  * Maxtor
  94  */
  95         { "Maxtor 6E040L0"      ,       NULL            },
  96         { "Maxtor 6Y080P0"      ,       NULL            },
  97         { "Maxtor 6Y160P0"      ,       NULL            },
  98 /*
  99  * Seagate
 100  */
 101         { "ST3120026A"          ,       NULL            },
 102         { "ST320014A"           ,       NULL            },
 103         { "ST94011A"            ,       NULL            },
 104         { "ST340016A"           ,       NULL            },
 105 /*
 106  * Western Digital
 107  */
 108         { "WDC WD400UE-00HCT0"  ,       NULL            },
 109         { "WDC WD400JB-00JJC0"  ,       NULL            },
 110         { NULL                  ,       NULL            }
 111 };
 112
 113 /* HD black list */
 114 static const struct drive_list_entry dma_black_list [] = {
 115 /*
 116  * Western Digital
 117  */
 118         { "WDC WD100EB-00CGH0"  ,       NULL            },
 119         { "WDC WD200BB-00AUA1"  ,       NULL            },
 120         { "WDC AC24300L"        ,       NULL            },
 121         { NULL                  ,       NULL            }
 122 };
 123 #endif
 124
 125 /* function prototyping */
 126 u8 auide_inb(unsigned long port);
 127 u16 auide_inw(unsigned long port);
 128 u32 auide_inl(unsigned long port);
 129 void auide_insw(unsigned long port, void *addr, u32 count);
 130 void auide_insl(unsigned long port, void *addr, u32 count);
 131 void auide_outb(u8 addr, unsigned long port);
 132 void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
 133 void auide_outw(u16 addr, unsigned long port);
 134 void auide_outl(u32 addr, unsigned long port);
 135 void auide_outsw(unsigned long port, void *addr, u32 count);
 136 void auide_outsl(unsigned long port, void *addr, u32 count);
 137 static void auide_tune_drive(ide_drive_t *drive, byte pio);
 138 static int auide_tune_chipset(ide_drive_t *drive, u8 speed);
 139 static int auide_ddma_init( _auide_hwif *auide );
 140 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
 141 int __init auide_probe(void);
 142
 143 /*******************************************************************************
 144 * PIO Mode timing calculation :                                                *
 145 *                                                                              *
 146 * Static Bus Spec   ATA Spec                                                   *
 147 *      Tcsoe      =   t1                                                       *
 148 *      Toecs      =   t9                                                       *
 149 *      Twcs       =   t9                                                       *
 150 *      Tcsh       =   t2i | t2                                                 *
 151 *      Tcsoff     =   t2i | t2                                                 *
 152 *      Twp        =   t2                                                       *
 153 *      Tcsw       =   t1                                                       *
 154 *      Tpm        =   0                                                        *
 155 *      Ta         =   t1+t2                                                    *
 156 *******************************************************************************/
 157
 158 #define TCSOE_MASK            (0x07<<29)
 159 #define TOECS_MASK            (0x07<<26)
 160 #define TWCS_MASK             (0x07<<28)
 161 #define TCSH_MASK             (0x0F<<24)
 162 #define TCSOFF_MASK           (0x07<<20)
 163 #define TWP_MASK              (0x3F<<14)
 164 #define TCSW_MASK             (0x0F<<10)
 165 #define TPM_MASK              (0x0F<<6)
 166 #define TA_MASK               (0x3F<<0)
 167 #define TS_MASK               (1<<8)
 168
 169 /* Timing parameters PIO mode 0 */
 170 #define SBC_IDE_PIO0_TCSOE    (0x04<<29)
 171 #define SBC_IDE_PIO0_TOECS    (0x01<<26)
 172 #define SBC_IDE_PIO0_TWCS     (0x02<<28)
 173 #define SBC_IDE_PIO0_TCSH     (0x08<<24)
 174 #define SBC_IDE_PIO0_TCSOFF   (0x07<<20)
 175 #define SBC_IDE_PIO0_TWP      (0x10<<14)
 176 #define SBC_IDE_PIO0_TCSW     (0x04<<10)
 177 #define SBC_IDE_PIO0_TPM      (0x0<<6)
 178 #define SBC_IDE_PIO0_TA       (0x15<<0)
 179 /* Timing parameters PIO mode 1 */
 180 #define SBC_IDE_PIO1_TCSOE    (0x03<<29)
 181 #define SBC_IDE_PIO1_TOECS    (0x01<<26)
 182 #define SBC_IDE_PIO1_TWCS     (0x01<<28)
 183 #define SBC_IDE_PIO1_TCSH     (0x06<<24)
 184 #define SBC_IDE_PIO1_TCSOFF   (0x06<<20)
 185 #define SBC_IDE_PIO1_TWP      (0x08<<14)
 186 #define SBC_IDE_PIO1_TCSW     (0x03<<10)
 187 #define SBC_IDE_PIO1_TPM      (0x00<<6)
 188 #define SBC_IDE_PIO1_TA       (0x0B<<0)
 189 /* Timing parameters PIO mode 2 */
 190 #define SBC_IDE_PIO2_TCSOE    (0x05<<29)
 191 #define SBC_IDE_PIO2_TOECS    (0x01<<26)
 192 #define SBC_IDE_PIO2_TWCS     (0x01<<28)
 193 #define SBC_IDE_PIO2_TCSH     (0x07<<24)
 194 #define SBC_IDE_PIO2_TCSOFF   (0x07<<20)
 195 #define SBC_IDE_PIO2_TWP      (0x1F<<14)
 196 #define SBC_IDE_PIO2_TCSW     (0x05<<10)
 197 #define SBC_IDE_PIO2_TPM      (0x00<<6)
 198 #define SBC_IDE_PIO2_TA       (0x22<<0)
 199 /* Timing parameters PIO mode 3 */
 200 #define SBC_IDE_PIO3_TCSOE    (0x05<<29)
 201 #define SBC_IDE_PIO3_TOECS    (0x01<<26)
 202 #define SBC_IDE_PIO3_TWCS     (0x01<<28)
 203 #define SBC_IDE_PIO3_TCSH     (0x0D<<24)
 204 #define SBC_IDE_PIO3_TCSOFF   (0x0D<<20)
 205 #define SBC_IDE_PIO3_TWP      (0x15<<14)
 206 #define SBC_IDE_PIO3_TCSW     (0x05<<10)
 207 #define SBC_IDE_PIO3_TPM      (0x00<<6)
 208 #define SBC_IDE_PIO3_TA       (0x1A<<0)
 209 /* Timing parameters PIO mode 4 */
 210 #define SBC_IDE_PIO4_TCSOE    (0x04<<29)
 211 #define SBC_IDE_PIO4_TOECS    (0x01<<26)
 212 #define SBC_IDE_PIO4_TWCS     (0x01<<28)
 213 #define SBC_IDE_PIO4_TCSH     (0x04<<24)
 214 #define SBC_IDE_PIO4_TCSOFF   (0x04<<20)
 215 #define SBC_IDE_PIO4_TWP      (0x0D<<14)
 216 #define SBC_IDE_PIO4_TCSW     (0x03<<10)
 217 #define SBC_IDE_PIO4_TPM      (0x00<<6)
 218 #define SBC_IDE_PIO4_TA       (0x12<<0)
 219 /* Timing parameters MDMA mode 0 */
 220 #define SBC_IDE_MDMA0_TCSOE   (0x03<<29)
 221 #define SBC_IDE_MDMA0_TOECS   (0x01<<26)
 222 #define SBC_IDE_MDMA0_TWCS    (0x01<<28)
 223 #define SBC_IDE_MDMA0_TCSH    (0x07<<24)
 224 #define SBC_IDE_MDMA0_TCSOFF  (0x07<<20)
 225 #define SBC_IDE_MDMA0_TWP     (0x0C<<14)
 226 #define SBC_IDE_MDMA0_TCSW    (0x03<<10)
 227 #define SBC_IDE_MDMA0_TPM     (0x00<<6)
 228 #define SBC_IDE_MDMA0_TA      (0x0F<<0)
 229 /* Timing parameters MDMA mode 1 */
 230 #define SBC_IDE_MDMA1_TCSOE   (0x05<<29)
 231 #define SBC_IDE_MDMA1_TOECS   (0x01<<26)
 232 #define SBC_IDE_MDMA1_TWCS    (0x01<<28)
 233 #define SBC_IDE_MDMA1_TCSH    (0x05<<24)
 234 #define SBC_IDE_MDMA1_TCSOFF  (0x05<<20)
 235 #define SBC_IDE_MDMA1_TWP     (0x0F<<14)
 236 #define SBC_IDE_MDMA1_TCSW    (0x05<<10)
 237 #define SBC_IDE_MDMA1_TPM     (0x00<<6)
 238 #define SBC_IDE_MDMA1_TA      (0x15<<0)
 239 /* Timing parameters MDMA mode 2 */
 240 #define SBC_IDE_MDMA2_TCSOE   (0x04<<29)
 241 #define SBC_IDE_MDMA2_TOECS   (0x01<<26)
 242 #define SBC_IDE_MDMA2_TWCS    (0x01<<28)
 243 #define SBC_IDE_MDMA2_TCSH    (0x04<<24)
 244 #define SBC_IDE_MDMA2_TCSOFF  (0x04<<20)
 245 #define SBC_IDE_MDMA2_TWP     (0x0D<<14)
 246 #define SBC_IDE_MDMA2_TCSW    (0x04<<10)
 247 #define SBC_IDE_MDMA2_TPM     (0x00<<6)
 248 #define SBC_IDE_MDMA2_TA      (0x12<<0)
 249
 250 #define SBC_IDE_TIMING(mode) \
 251          SBC_IDE_##mode##_TWCS | \
 252          SBC_IDE_##mode##_TCSH | \
 253          SBC_IDE_##mode##_TCSOFF | \
 254          SBC_IDE_##mode##_TWP | \
 255          SBC_IDE_##mode##_TCSW | \
 256          SBC_IDE_##mode##_TPM | \
 257          SBC_IDE_##mode##_TA