| blob | 1bd4e27caf6b70ee4ecbc1b2df29846e124e9969 |
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2004 Embedded Edge, LLC
7 * dan@embeddededge.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
30 /* Specifics for the Au1xxx Programmable Serial Controllers, first
31 * seen in the AU1550 part.
32 */
33 #ifndef _AU1000_PSC_H_
34 #define _AU1000_PSC_H_
37 /* The PSC base addresses. */
38 #ifdef CONFIG_SOC_AU1550
39 #define PSC0_BASE_ADDR 0xb1a00000
40 #define PSC1_BASE_ADDR 0xb1b00000
41 #define PSC2_BASE_ADDR 0xb0a00000
42 #define PSC3_BASE_ADDR 0xb0b00000
43 #endif
45 #ifdef CONFIG_SOC_AU1200
46 #define PSC0_BASE_ADDR 0xb1a00000
47 #define PSC1_BASE_ADDR 0xb1b00000
48 #endif
50 /* The PSC select and control registers are common to
51 * all protocols.
52 */
53 #define PSC_SEL_OFFSET 0x00000000
54 #define PSC_CTRL_OFFSET 0x00000004
56 #define PSC_SEL_CLK_MASK (3 << 4)
57 #define PSC_SEL_CLK_INTCLK (0 << 4)
58 #define PSC_SEL_CLK_EXTCLK (1 << 4)
59 #define PSC_SEL_CLK_SERCLK (2 << 4)
61 #define PSC_SEL_PS_MASK 0x00000007
62 #define PSC_SEL_PS_DISABLED (0)
63 #define PSC_SEL_PS_SPIMODE (2)
64 #define PSC_SEL_PS_I2SMODE (3)
65 #define PSC_SEL_PS_AC97MODE (4)
66 #define PSC_SEL_PS_SMBUSMODE (5)
68 #define PSC_CTRL_DISABLE (0)
69 #define PSC_CTRL_SUSPEND (2)
70 #define PSC_CTRL_ENABLE (3)
72 /* AC97 Registers.
73 */
74 #define PSC_AC97CFG_OFFSET 0x00000008
75 #define PSC_AC97MSK_OFFSET 0x0000000c
76 #define PSC_AC97PCR_OFFSET 0x00000010
77 #define PSC_AC97STAT_OFFSET 0x00000014
78 #define PSC_AC97EVNT_OFFSET 0x00000018
79 #define PSC_AC97TXRX_OFFSET 0x0000001c
80 #define PSC_AC97CDC_OFFSET 0x00000020
81 #define PSC_AC97RST_OFFSET 0x00000024
82 #define PSC_AC97GPO_OFFSET 0x00000028
83 #define PSC_AC97GPI_OFFSET 0x0000002c
85 #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
86 #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
87 #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
88 #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
89 #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
90 #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
91 #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
92 #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
93 #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
94 #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
95 #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
96 #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
98 /* AC97 Config Register.
99 */
100 #define PSC_AC97CFG_RT_MASK (3 << 30)
101 #define PSC_AC97CFG_RT_FIFO1 (0 << 30)
102 #define PSC_AC97CFG_RT_FIFO2 (1 << 30)
103 #define PSC_AC97CFG_RT_FIFO4 (2 << 30)
104 #define PSC_AC97CFG_RT_FIFO8 (3 << 30)
106 #define PSC_AC97CFG_TT_MASK (3 << 28)
107 #define PSC_AC97CFG_TT_FIFO1 (0 << 28)
108 #define PSC_AC97CFG_TT_FIFO2 (1 << 28)
109 #define PSC_AC97CFG_TT_FIFO4 (2 << 28)
110 #define PSC_AC97CFG_TT_FIFO8 (3 << 28)
112 #define PSC_AC97CFG_DD_DISABLE (1 << 27)
113 #define PSC_AC97CFG_DE_ENABLE (1 << 26)
114 #define PSC_AC97CFG_SE_ENABLE (1 << 25)
116 #define PSC_AC97CFG_LEN_MASK (0xf << 21)
117 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
118 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
119 #define PSC_AC97CFG_GE_ENABLE (1)
121 /* Enable slots 3-12.
122 */
123 #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
124 #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
126 /* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
127 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
128 * arithmetic in the macro.
129 */
130 #define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
131 #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
133 /* AC97 Mask Register.
134 */
135 #define PSC_AC97MSK_GR (1 << 25)
136 #define PSC_AC97MSK_CD (1 << 24)
137 #define PSC_AC97MSK_RR (1 << 13)
138 #define PSC_AC97MSK_RO (1 << 12)
139 #define PSC_AC97MSK_RU (1 << 11)
140 #define PSC_AC97MSK_TR (1 << 10)
141 #define PSC_AC97MSK_TO (1 << 9)
142 #define PSC_AC97MSK_TU (1 << 8)
143 #define PSC_AC97MSK_RD (1 << 5)
144 #define PSC_AC97MSK_TD (1 << 4)
145 #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
146 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
147 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
148 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
149 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
151 /* AC97 Protocol Control Register.
152 */
153 #define PSC_AC97PCR_RC (1 << 6)
154 #define PSC_AC97PCR_RP (1 << 5)
155 #define PSC_AC97PCR_RS (1 << 4)
156 #define PSC_AC97PCR_TC (1 << 2)
157 #define PSC_AC97PCR_TP (1 << 1)
158 #define PSC_AC97PCR_TS (1 << 0)
160 /* AC97 Status register (read only).
161 */
162 #define PSC_AC97STAT_CB (1 << 26)
163 #define PSC_AC97STAT_CP (1 << 25)
164 #define PSC_AC97STAT_CR (1 << 24)
165 #define PSC_AC97STAT_RF (1 << 13)
166 #define PSC_AC97STAT_RE (1 << 12)
167 #define PSC_AC97STAT_RR (1 << 11)
168 #define PSC_AC97STAT_TF (1 << 10)
169 #define PSC_AC97STAT_TE (1 << 9)
170 #define PSC_AC97STAT_TR (1 << 8)
171 #define PSC_AC97STAT_RB (1 << 5)
172 #define PSC_AC97STAT_TB (1 << 4)
173 #define PSC_AC97STAT_DI (1 << 2)
174 #define PSC_AC97STAT_DR (1 << 1)
175 #define PSC_AC97STAT_SR (1 << 0)
177 /* AC97 Event Register.
178 */
179 #define PSC_AC97EVNT_GR (1 << 25)
180 #define PSC_AC97EVNT_CD (1 << 24)
181 #define PSC_AC97EVNT_RR (1 << 13)
182 #define PSC_AC97EVNT_RO (1 << 12)
183 #define PSC_AC97EVNT_RU (1 << 11)
184 #define PSC_AC97EVNT_TR (1 << 10)
185 #define PSC_AC97EVNT_TO (1 << 9)
186 #define PSC_AC97EVNT_TU (1 << 8)
187 #define PSC_AC97EVNT_RD (1 << 5)
188 #define PSC_AC97EVNT_TD (1 << 4)
190 /* CODEC Command Register.
191 */
192 #define PSC_AC97CDC_RD (1 << 25)
193 #define PSC_AC97CDC_ID_MASK (3 << 23)
194 #define PSC_AC97CDC_INDX_MASK (0x7f << 16)
195 #define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
196 #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
198 /* AC97 Reset Control Register.
199 */
200 #define PSC_AC97RST_RST (1 << 1)
201 #define PSC_AC97RST_SNC (1 << 0)
204 /* PSC in I2S Mode.
205 */
207 u32 psc_sel;
208 u32 psc_ctrl;
209 u32 psc_i2scfg;
210 u32 psc_i2smsk;
211 u32 psc_i2spcr;
212 u32 psc_i2sstat;
213 u32 psc_i2sevent;
214 u32 psc_i2stxrx;
215 u32 psc_i2sudf;
218 /* I2S Config Register.
219 */
220 #define PSC_I2SCFG_RT_MASK (3 << 30)
221 #define PSC_I2SCFG_RT_FIFO1 (0 << 30)
222 #define PSC_I2SCFG_RT_FIFO2 (1 << 30)
223 #define PSC_I2SCFG_RT_FIFO4 (2 << 30)
224 #define PSC_I2SCFG_RT_FIFO8 (3 << 30)
226 #define PSC_I2SCFG_TT_MASK (3 << 28)
227 #define PSC_I2SCFG_TT_FIFO1 (0 << 28)
228 #define PSC_I2SCFG_TT_FIFO2 (1 << 28)
229 #define PSC_I2SCFG_TT_FIFO4 (2 << 28)
230 #define PSC_I2SCFG_TT_FIFO8 (3 << 28)
232 #define PSC_I2SCFG_DD_DISABLE (1 << 27)
233 #define PSC_I2SCFG_DE_ENABLE (1 << 26)
234 #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
235 #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16)
236 #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F))
237 #define PSC_I2SCFG_WI (1 << 15)
239 #define PSC_I2SCFG_DIV_MASK (3 << 13)
240 #define PSC_I2SCFG_DIV2 (0 << 13)
241 #define PSC_I2SCFG_DIV4 (1 << 13)
242 #define PSC_I2SCFG_DIV8 (2 << 13)
243 #define PSC_I2SCFG_DIV16 (3 << 13)
245 #define PSC_I2SCFG_BI (1 << 12)
246 #define PSC_I2SCFG_BUF (1 << 11)
247 #define PSC_I2SCFG_MLJ (1 << 10)
248 #define PSC_I2SCFG_XM (1 << 9)
250 /* The word length equation is simply LEN+1.
251 */
252 #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
253 #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
255 #define PSC_I2SCFG_LB (1 << 2)
256 #define PSC_I2SCFG_MLF (1 << 1)
257 #define PSC_I2SCFG_MS (1 << 0)
259 /* I2S Mask Register.
260 */
261 #define PSC_I2SMSK_RR (1 << 13)
262 #define PSC_I2SMSK_RO (1 << 12)
263 #define PSC_I2SMSK_RU (1 << 11)
264 #define PSC_I2SMSK_TR (1 << 10)
265 #define PSC_I2SMSK_TO (1 << 9)
266 #define PSC_I2SMSK_TU (1 << 8)
267 #define PSC_I2SMSK_RD (1 << 5)
268 #define PSC_I2SMSK_TD (1 << 4)
269 #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
270 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
271 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
272 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
274 /* I2S Protocol Control Register.
275 */
276 #define PSC_I2SPCR_RC (1 << 6)
277 #define PSC_I2SPCR_RP (1 << 5)
278 #define PSC_I2SPCR_RS (1 << 4)
279 #define PSC_I2SPCR_TC (1 << 2)
280 #define PSC_I2SPCR_TP (1 << 1)
281 #define PSC_I2SPCR_TS (1 << 0)
283 /* I2S Status register (read only).
284 */
285 #define PSC_I2SSTAT_RF (1 << 13)
286 #define PSC_I2SSTAT_RE (1 << 12)
287 #define PSC_I2SSTAT_RR (1 << 11)
288 #define PSC_I2SSTAT_TF (1 << 10)
289 #define PSC_I2SSTAT_TE (1 << 9)
290 #define PSC_I2SSTAT_TR (1 << 8)
291 #define PSC_I2SSTAT_RB (1 << 5)
292 #define PSC_I2SSTAT_TB (1 << 4)
293 #define PSC_I2SSTAT_DI (1 << 2)
294 #define PSC_I2SSTAT_DR (1 << 1)
295 #define PSC_I2SSTAT_SR (1 << 0)
297 /* I2S Event Register.
298 */
299 #define PSC_I2SEVNT_RR (1 << 13)
300 #define PSC_I2SEVNT_RO (1 << 12)
301 #define PSC_I2SEVNT_RU (1 << 11)
302 #define PSC_I2SEVNT_TR (1 << 10)
303 #define PSC_I2SEVNT_TO (1 << 9)
304 #define PSC_I2SEVNT_TU (1 << 8)
305 #define PSC_I2SEVNT_RD (1 << 5)
306 #define PSC_I2SEVNT_TD (1 << 4)
308 /* PSC in SPI Mode.
309 */
311 u32 psc_sel;
312 u32 psc_ctrl;
313 u32 psc_spicfg;
314 u32 psc_spimsk;
315 u32 psc_spipcr;
316 u32 psc_spistat;
317 u32 psc_spievent;
318 u32 psc_spitxrx;
321 /* SPI Config Register.
322 */
323 #define PSC_SPICFG_RT_MASK (3 << 30)
324 #define PSC_SPICFG_RT_FIFO1 (0 << 30)
325 #define PSC_SPICFG_RT_FIFO2 (1 << 30)
326 #define PSC_SPICFG_RT_FIFO4 (2 << 30)
327 #define PSC_SPICFG_RT_FIFO8 (3 << 30)
329 #define PSC_SPICFG_TT_MASK (3 << 28)
330 #define PSC_SPICFG_TT_FIFO1 (0 << 28)
331 #define PSC_SPICFG_TT_FIFO2 (1 << 28)
332 #define PSC_SPICFG_TT_FIFO4 (2 << 28)
333 #define PSC_SPICFG_TT_FIFO8 (3 << 28)
335 #define PSC_SPICFG_DD_DISABLE (1 << 27)
336 #define PSC_SPICFG_DE_ENABLE (1 << 26)
337 #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
338 #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
340 #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)
341 #define PSC_SPICFG_DIV2 0
342 #define PSC_SPICFG_DIV4 1
343 #define PSC_SPICFG_DIV8 2
344 #define PSC_SPICFG_DIV16 3
346 #define PSC_SPICFG_BI (1 << 12)
347 #define PSC_SPICFG_PSE (1 << 11)
348 #define PSC_SPICFG_CGE (1 << 10)
349 #define PSC_SPICFG_CDE (1 << 9)
351 #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))
352 #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)
354 #define PSC_SPICFG_LB (1 << 3)
355 #define PSC_SPICFG_MLF (1 << 1)
356 #define PSC_SPICFG_MO (1 << 0)
358 /* SPI Mask Register.
359 */
360 #define PSC_SPIMSK_MM (1 << 16)
361 #define PSC_SPIMSK_RR (1 << 13)
362 #define PSC_SPIMSK_RO (1 << 12)
363 #define PSC_SPIMSK_RU (1 << 11)
364 #define PSC_SPIMSK_TR (1 << 10)
365 #define PSC_SPIMSK_TO (1 << 9)
366 #define PSC_SPIMSK_TU (1 << 8)
367 #define PSC_SPIMSK_SD (1 << 5)
368 #define PSC_SPIMSK_MD (1 << 4)
369 #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
370 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
371 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
372 PSC_SPIMSK_MD)
374 /* SPI Protocol Control Register.
375 */
376 #define PSC_SPIPCR_RC (1 << 6)
377 #define PSC_SPIPCR_SP (1 << 5)
378 #define PSC_SPIPCR_SS (1 << 4)
379 #define PSC_SPIPCR_TC (1 << 2)
380 #define PSC_SPIPCR_MS (1 << 0)
382 /* SPI Status register (read only).
383 */
384 #define PSC_SPISTAT_RF (1 << 13)
385 #define PSC_SPISTAT_RE (1 << 12)
386 #define PSC_SPISTAT_RR (1 << 11)
387 #define PSC_SPISTAT_TF (1 << 10)
388 #define PSC_SPISTAT_TE (1 << 9)
389 #define PSC_SPISTAT_TR (1 << 8)
390 #define PSC_SPISTAT_SB (1 << 5)
391 #define PSC_SPISTAT_MB (1 << 4)
392 #define PSC_SPISTAT_DI (1 << 2)
393 #define PSC_SPISTAT_DR (1 << 1)
394 #define PSC_SPISTAT_SR (1 << 0)
396 /* SPI Event Register.
397 */
398 #define PSC_SPIEVNT_MM (1 << 16)
399 #define PSC_SPIEVNT_RR (1 << 13)
400 #define PSC_SPIEVNT_RO (1 << 12)
401 #define PSC_SPIEVNT_RU (1 << 11)
402 #define PSC_SPIEVNT_TR (1 << 10)
403 #define PSC_SPIEVNT_TO (1 << 9)
404 #define PSC_SPIEVNT_TU (1 << 8)
405 #define PSC_SPIEVNT_SD (1 << 5)
406 #define PSC_SPIEVNT_MD (1 << 4)
408 /* Transmit register control.
409 */
410 #define PSC_SPITXRX_LC (1 << 29)
411 #define PSC_SPITXRX_SR (1 << 28)
413 /* PSC in SMBus (I2C) Mode.
414 */
416 u32 psc_sel;
417 u32 psc_ctrl;
418 u32 psc_smbcfg;
419 u32 psc_smbmsk;
420 u32 psc_smbpcr;
421 u32 psc_smbstat;
422 u32 psc_smbevnt;
423 u32 psc_smbtxrx;
424 u32 psc_smbtmr;
427 /* SMBus Config Register.
428 */
429 #define PSC_SMBCFG_RT_MASK (3 << 30)
430 #define PSC_SMBCFG_RT_FIFO1 (0 << 30)
431 #define PSC_SMBCFG_RT_FIFO2 (1 << 30)
432 #define PSC_SMBCFG_RT_FIFO4 (2 << 30)
433 #define PSC_SMBCFG_RT_FIFO8 (3 << 30)
435 #define PSC_SMBCFG_TT_MASK (3 << 28)
436 #define PSC_SMBCFG_TT_FIFO1 (0 << 28)
437 #define PSC_SMBCFG_TT_FIFO2 (1 << 28)
438 #define PSC_SMBCFG_TT_FIFO4 (2 << 28)
439 #define PSC_SMBCFG_TT_FIFO8 (3 << 28)
441 #define PSC_SMBCFG_DD_DISABLE (1 << 27)
442 #define PSC_SMBCFG_DE_ENABLE (1 << 26)
444 #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)
445 #define PSC_SMBCFG_DIV2 0
446 #define PSC_SMBCFG_DIV4 1
447 #define PSC_SMBCFG_DIV8 2
448 #define PSC_SMBCFG_DIV16 3
450 #define PSC_SMBCFG_GCE (1 << 9)
451 #define PSC_SMBCFG_SFM (1 << 8)
453 #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
455 /* SMBus Mask Register.
456 */
457 #define PSC_SMBMSK_DN (1 << 30)
458 #define PSC_SMBMSK_AN (1 << 29)
459 #define PSC_SMBMSK_AL (1 << 28)
460 #define PSC_SMBMSK_RR (1 << 13)
461 #define PSC_SMBMSK_RO (1 << 12)
462 #define PSC_SMBMSK_RU (1 << 11)
463 #define PSC_SMBMSK_TR (1 << 10)
464 #define PSC_SMBMSK_TO (1 << 9)
465 #define PSC_SMBMSK_TU (1 << 8)
466 #define PSC_SMBMSK_SD (1 << 5)
467 #define PSC_SMBMSK_MD (1 << 4)
468 #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
469 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
470 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
471 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
472 PSC_SMBMSK_MD)
474 /* SMBus Protocol Control Register.
475 */
476 #define PSC_SMBPCR_DC (1 << 2)
477 #define PSC_SMBPCR_MS (1 << 0)
479 /* SMBus Status register (read only).
480 */
481 #define PSC_SMBSTAT_BB (1 << 28)
482 #define PSC_SMBSTAT_RF (1 << 13)
483 #define PSC_SMBSTAT_RE (1 << 12)
484 #define PSC_SMBSTAT_RR (1 << 11)
485 #define PSC_SMBSTAT_TF (1 << 10)
486 #define PSC_SMBSTAT_TE (1 << 9)
487 #define PSC_SMBSTAT_TR (1 << 8)
488 #define PSC_SMBSTAT_SB (1 << 5)
489 #define PSC_SMBSTAT_MB (1 << 4)
490 #define PSC_SMBSTAT_DI (1 << 2)
491 #define PSC_SMBSTAT_DR (1 << 1)
492 #define PSC_SMBSTAT_SR (1 << 0)
494 /* SMBus Event Register.
495 */
496 #define PSC_SMBEVNT_DN (1 << 30)
497 #define PSC_SMBEVNT_AN (1 << 29)
498 #define PSC_SMBEVNT_AL (1 << 28)
499 #define PSC_SMBEVNT_RR (1 << 13)
500 #define PSC_SMBEVNT_RO (1 << 12)
501 #define PSC_SMBEVNT_RU (1 << 11)
502 #define PSC_SMBEVNT_TR (1 << 10)
503 #define PSC_SMBEVNT_TO (1 << 9)
504 #define PSC_SMBEVNT_TU (1 << 8)
505 #define PSC_SMBEVNT_SD (1 << 5)
506 #define PSC_SMBEVNT_MD (1 << 4)
507 #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
508 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
509 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
510 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
511 PSC_SMBEVNT_MD)
513 /* Transmit register control.
514 */
515 #define PSC_SMBTXRX_RSR (1 << 28)
516 #define PSC_SMBTXRX_STP (1 << 29)
517 #define PSC_SMBTXRX_DATAMASK (0xff)
519 /* SMBus protocol timers register.
520 */
521 #define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
522 #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
523 #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
524 #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
525 #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)
526 #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
527 #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)