include/asm-powerpc/reg_fsl_emb.h

   1 /*
   2  * Contains register definitions for the Freescale Embedded Performance
   3  * Monitor.
   4  */
   5 #ifdef __KERNEL__
   6 #ifndef __ASM_POWERPC_REG_FSL_EMB_H__
   7 #define __ASM_POWERPC_REG_FSL_EMB_H__
   8
   9 #ifndef __ASSEMBLY__
  10 /* Performance Monitor Registers */
  11 #define mfpmr(rn)       ({unsigned int rval; \
  12                         asm volatile("mfpmr %0," __stringify(rn) \
  13                                      : "=r" (rval)); rval;})
  14 #define mtpmr(rn, v)    asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
  15 #endif /* __ASSEMBLY__ */
  16
  17 /* Freescale Book E Performance Monitor APU Registers */
  18 #define PMRN_PMC0       0x010   /* Performance Monitor Counter 0 */
  19 #define PMRN_PMC1       0x011   /* Performance Monitor Counter 1 */
  20 #define PMRN_PMC2       0x012   /* Performance Monitor Counter 1 */
  21 #define PMRN_PMC3       0x013   /* Performance Monitor Counter 1 */
  22 #define PMRN_PMLCA0     0x090   /* PM Local Control A0 */
  23 #define PMRN_PMLCA1     0x091   /* PM Local Control A1 */
  24 #define PMRN_PMLCA2     0x092   /* PM Local Control A2 */
  25 #define PMRN_PMLCA3     0x093   /* PM Local Control A3 */
  26
  27 #define PMLCA_FC        0x80000000      /* Freeze Counter */
  28 #define PMLCA_FCS       0x40000000      /* Freeze in Supervisor */
  29 #define PMLCA_FCU       0x20000000      /* Freeze in User */
  30 #define PMLCA_FCM1      0x10000000      /* Freeze when PMM==1 */
  31 #define PMLCA_FCM0      0x08000000      /* Freeze when PMM==0 */
  32 #define PMLCA_CE        0x04000000      /* Condition Enable */
  33
  34 #define PMLCA_EVENT_MASK 0x007f0000     /* Event field */
  35 #define PMLCA_EVENT_SHIFT       16
  36
  37 #define PMRN_PMLCB0     0x110   /* PM Local Control B0 */
  38 #define PMRN_PMLCB1     0x111   /* PM Local Control B1 */
  39 #define PMRN_PMLCB2     0x112   /* PM Local Control B2 */
  40 #define PMRN_PMLCB3     0x113   /* PM Local Control B3 */
  41
  42 #define PMLCB_THRESHMUL_MASK    0x0700  /* Threshhold Multiple Field */
  43 #define PMLCB_THRESHMUL_SHIFT   8
  44
  45 #define PMLCB_THRESHOLD_MASK    0x003f  /* Threshold Field */
  46 #define PMLCB_THRESHOLD_SHIFT   0
  47
  48 #define PMRN_PMGC0      0x190   /* PM Global Control 0 */
  49
  50 #define PMGC0_FAC       0x80000000      /* Freeze all Counters */
  51 #define PMGC0_PMIE      0x40000000      /* Interrupt Enable */
  52 #define PMGC0_FCECE     0x20000000      /* Freeze countes on
  53                                            Enabled Condition or
  54                                            Event */
  55
  56 #define PMRN_UPMC0      0x000   /* User Performance Monitor Counter 0 */
  57 #define PMRN_UPMC1      0x001   /* User Performance Monitor Counter 1 */
  58 #define PMRN_UPMC2      0x002   /* User Performance Monitor Counter 1 */
  59 #define PMRN_UPMC3      0x003   /* User Performance Monitor Counter 1 */
  60 #define PMRN_UPMLCA0    0x080   /* User PM Local Control A0 */
  61 #define PMRN_UPMLCA1    0x081   /* User PM Local Control A1 */
  62 #define PMRN_UPMLCA2    0x082   /* User PM Local Control A2 */
  63 #define PMRN_UPMLCA3    0x083   /* User PM Local Control A3 */
  64 #define PMRN_UPMLCB0    0x100   /* User PM Local Control B0 */
  65 #define PMRN_UPMLCB1    0x101   /* User PM Local Control B1 */
  66 #define PMRN_UPMLCB2    0x102   /* User PM Local Control B2 */
  67 #define PMRN_UPMLCB3    0x103   /* User PM Local Control B3 */
  68 #define PMRN_UPMGC0     0x180   /* User PM Global Control 0 */
  69
  70
  71 #endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
  72 #endif /* __KERNEL__ */