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[PATCH] hrtimers: fix HRTIMER_CB_IRQSAFE_NO_SOFTIRQ description
[wrt350n-kernel.git] / drivers / char / synclink_gt.c
blob0a367cd4121ffc0ab127bcc64e4838da82d98c79
1 /*
2 * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #include "linux/synclink.h"
85
86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
87 #define SYNCLINK_GENERIC_HDLC 1
88 #else
89 #define SYNCLINK_GENERIC_HDLC 0
90 #endif
91
92 /*
93 * module identification
94 */
95 static char *driver_name = "SyncLink GT";
96 static char *driver_version = "$Revision: 4.36 $";
97 static char *tty_driver_name = "synclink_gt";
98 static char *tty_dev_prefix = "ttySLG";
99 MODULE_LICENSE("GPL");
100 #define MGSL_MAGIC 0x5401
101 #define MAX_DEVICES 32
102
103 static struct pci_device_id pci_table[] = {
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
108 {0,}, /* terminate list */
109 };
110 MODULE_DEVICE_TABLE(pci, pci_table);
111
112 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
113 static void remove_one(struct pci_dev *dev);
114 static struct pci_driver pci_driver = {
115 .name = "synclink_gt",
116 .id_table = pci_table,
117 .probe = init_one,
118 .remove = __devexit_p(remove_one),
119 };
120
121 static int pci_registered;
122
123 /*
124 * module configuration and status
125 */
126 static struct slgt_info *slgt_device_list;
127 static int slgt_device_count;
128
129 static int ttymajor;
130 static int debug_level;
131 static int maxframe[MAX_DEVICES];
132 static int dosyncppp[MAX_DEVICES];
133
134 module_param(ttymajor, int, 0);
135 module_param(debug_level, int, 0);
136 module_param_array(maxframe, int, NULL, 0);
137 module_param_array(dosyncppp, int, NULL, 0);
138
139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
143
144 /*
145 * tty support and callbacks
146 */
147 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
148
149 static struct tty_driver *serial_driver;
150
151 static int open(struct tty_struct *tty, struct file * filp);
152 static void close(struct tty_struct *tty, struct file * filp);
153 static void hangup(struct tty_struct *tty);
154 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
155
156 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
157 static void put_char(struct tty_struct *tty, unsigned char ch);
158 static void send_xchar(struct tty_struct *tty, char ch);
159 static void wait_until_sent(struct tty_struct *tty, int timeout);
160 static int write_room(struct tty_struct *tty);
161 static void flush_chars(struct tty_struct *tty);
162 static void flush_buffer(struct tty_struct *tty);
163 static void tx_hold(struct tty_struct *tty);
164 static void tx_release(struct tty_struct *tty);
165
166 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
167 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
168 static int chars_in_buffer(struct tty_struct *tty);
169 static void throttle(struct tty_struct * tty);
170 static void unthrottle(struct tty_struct * tty);
171 static void set_break(struct tty_struct *tty, int break_state);
172
173 /*
174 * generic HDLC support and callbacks
175 */
176 #if SYNCLINK_GENERIC_HDLC
177 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
178 static void hdlcdev_tx_done(struct slgt_info *info);
179 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
180 static int hdlcdev_init(struct slgt_info *info);
181 static void hdlcdev_exit(struct slgt_info *info);
182 #endif
183
184
185 /*
186 * device specific structures, macros and functions
187 */
188
189 #define SLGT_MAX_PORTS 4
190 #define SLGT_REG_SIZE 256
191
192 /*
193 * conditional wait facility
194 */
195 struct cond_wait {
196 struct cond_wait *next;
197 wait_queue_head_t q;
198 wait_queue_t wait;
199 unsigned int data;
200 };
201 static void init_cond_wait(struct cond_wait *w, unsigned int data);
202 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
203 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
204 static void flush_cond_wait(struct cond_wait **head);
205
206 /*
207 * DMA buffer descriptor and access macros
208 */
209 struct slgt_desc
210 {
211 unsigned short count;
212 unsigned short status;
213 unsigned int pbuf; /* physical address of data buffer */
214 unsigned int next; /* physical address of next descriptor */
215
216 /* driver book keeping */
217 char *buf; /* virtual address of data buffer */
218 unsigned int pdesc; /* physical address of this descriptor */
219 dma_addr_t buf_dma_addr;
220 };
221
222 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
223 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
224 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
225 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
226 #define desc_count(a) (le16_to_cpu((a).count))
227 #define desc_status(a) (le16_to_cpu((a).status))
228 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
229 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
230 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
231 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
232 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
233
234 struct _input_signal_events {
235 int ri_up;
236 int ri_down;
237 int dsr_up;
238 int dsr_down;
239 int dcd_up;
240 int dcd_down;
241 int cts_up;
242 int cts_down;
243 };
244
245 /*
246 * device instance data structure
247 */
248 struct slgt_info {
249 void *if_ptr; /* General purpose pointer (used by SPPP) */
250
251 struct slgt_info *next_device; /* device list link */
252
253 int magic;
254 int flags;
255
256 char device_name[25];
257 struct pci_dev *pdev;
258
259 int port_count; /* count of ports on adapter */
260 int adapter_num; /* adapter instance number */
261 int port_num; /* port instance number */
262
263 /* array of pointers to port contexts on this adapter */
264 struct slgt_info *port_array[SLGT_MAX_PORTS];
265
266 int count; /* count of opens */
267 int line; /* tty line instance number */
268 unsigned short close_delay;
269 unsigned short closing_wait; /* time to wait before closing */
270
271 struct mgsl_icount icount;
272
273 struct tty_struct *tty;
274 int timeout;
275 int x_char; /* xon/xoff character */
276 int blocked_open; /* # of blocked opens */
277 unsigned int read_status_mask;
278 unsigned int ignore_status_mask;
279
280 wait_queue_head_t open_wait;
281 wait_queue_head_t close_wait;
282
283 wait_queue_head_t status_event_wait_q;
284 wait_queue_head_t event_wait_q;
285 struct timer_list tx_timer;
286 struct timer_list rx_timer;
287
288 unsigned int gpio_present;
289 struct cond_wait *gpio_wait_q;
290
291 spinlock_t lock; /* spinlock for synchronizing with ISR */
292
293 struct work_struct task;
294 u32 pending_bh;
295 int bh_requested;
296 int bh_running;
297
298 int isr_overflow;
299 int irq_requested; /* nonzero if IRQ requested */
300 int irq_occurred; /* for diagnostics use */
301
302 /* device configuration */
303
304 unsigned int bus_type;
305 unsigned int irq_level;
306 unsigned long irq_flags;
307
308 unsigned char __iomem * reg_addr; /* memory mapped registers address */
309 u32 phys_reg_addr;
310 int reg_addr_requested;
311
312 MGSL_PARAMS params; /* communications parameters */
313 u32 idle_mode;
314 u32 max_frame_size; /* as set by device config */
315
316 unsigned int raw_rx_size;
317 unsigned int if_mode;
318
319 /* device status */
320
321 int rx_enabled;
322 int rx_restart;
323
324 int tx_enabled;
325 int tx_active;
326
327 unsigned char signals; /* serial signal states */
328 int init_error; /* initialization error */
329
330 unsigned char *tx_buf;
331 int tx_count;
332
333 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
334 char char_buf[MAX_ASYNC_BUFFER_SIZE];
335 BOOLEAN drop_rts_on_tx_done;
336 struct _input_signal_events input_signal_events;
337
338 int dcd_chkcount; /* check counts to prevent */
339 int cts_chkcount; /* too many IRQs if a signal */
340 int dsr_chkcount; /* is floating */
341 int ri_chkcount;
342
343 char *bufs; /* virtual address of DMA buffer lists */
344 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
345
346 unsigned int rbuf_count;
347 struct slgt_desc *rbufs;
348 unsigned int rbuf_current;
349 unsigned int rbuf_index;
350
351 unsigned int tbuf_count;
352 struct slgt_desc *tbufs;
353 unsigned int tbuf_current;
354 unsigned int tbuf_start;
355
356 unsigned char *tmp_rbuf;
357 unsigned int tmp_rbuf_count;
358
359 /* SPPP/Cisco HDLC device parts */
360
361 int netcount;
362 int dosyncppp;
363 spinlock_t netlock;
364 #if SYNCLINK_GENERIC_HDLC
365 struct net_device *netdev;
366 #endif
367
368 };
369
370 static MGSL_PARAMS default_params = {
371 .mode = MGSL_MODE_HDLC,
372 .loopback = 0,
373 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
374 .encoding = HDLC_ENCODING_NRZI_SPACE,
375 .clock_speed = 0,
376 .addr_filter = 0xff,
377 .crc_type = HDLC_CRC_16_CCITT,
378 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
379 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
380 .data_rate = 9600,
381 .data_bits = 8,
382 .stop_bits = 1,
383 .parity = ASYNC_PARITY_NONE
384 };
385
386
387 #define BH_RECEIVE 1
388 #define BH_TRANSMIT 2
389 #define BH_STATUS 4
390 #define IO_PIN_SHUTDOWN_LIMIT 100
391
392 #define DMABUFSIZE 256
393 #define DESC_LIST_SIZE 4096
394
395 #define MASK_PARITY BIT1
396 #define MASK_FRAMING BIT0
397 #define MASK_BREAK BIT14
398 #define MASK_OVERRUN BIT4
399
400 #define GSR 0x00 /* global status */
401 #define JCR 0x04 /* JTAG control */
402 #define IODR 0x08 /* GPIO direction */
403 #define IOER 0x0c /* GPIO interrupt enable */
404 #define IOVR 0x10 /* GPIO value */
405 #define IOSR 0x14 /* GPIO interrupt status */
406 #define TDR 0x80 /* tx data */
407 #define RDR 0x80 /* rx data */
408 #define TCR 0x82 /* tx control */
409 #define TIR 0x84 /* tx idle */
410 #define TPR 0x85 /* tx preamble */
411 #define RCR 0x86 /* rx control */
412 #define VCR 0x88 /* V.24 control */
413 #define CCR 0x89 /* clock control */
414 #define BDR 0x8a /* baud divisor */
415 #define SCR 0x8c /* serial control */
416 #define SSR 0x8e /* serial status */
417 #define RDCSR 0x90 /* rx DMA control/status */
418 #define TDCSR 0x94 /* tx DMA control/status */
419 #define RDDAR 0x98 /* rx DMA descriptor address */
420 #define TDDAR 0x9c /* tx DMA descriptor address */
421
422 #define RXIDLE BIT14
423 #define RXBREAK BIT14
424 #define IRQ_TXDATA BIT13
425 #define IRQ_TXIDLE BIT12
426 #define IRQ_TXUNDER BIT11 /* HDLC */
427 #define IRQ_RXDATA BIT10
428 #define IRQ_RXIDLE BIT9 /* HDLC */
429 #define IRQ_RXBREAK BIT9 /* async */
430 #define IRQ_RXOVER BIT8
431 #define IRQ_DSR BIT7
432 #define IRQ_CTS BIT6
433 #define IRQ_DCD BIT5
434 #define IRQ_RI BIT4
435 #define IRQ_ALL 0x3ff0
436 #define IRQ_MASTER BIT0
437
438 #define slgt_irq_on(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
440 #define slgt_irq_off(info, mask) \
441 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
442
443 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
444 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
445 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
446 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
447 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
448 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
449
450 static void msc_set_vcr(struct slgt_info *info);
451
452 static int startup(struct slgt_info *info);
453 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
454 static void shutdown(struct slgt_info *info);
455 static void program_hw(struct slgt_info *info);
456 static void change_params(struct slgt_info *info);
457
458 static int register_test(struct slgt_info *info);
459 static int irq_test(struct slgt_info *info);
460 static int loopback_test(struct slgt_info *info);
461 static int adapter_test(struct slgt_info *info);
462
463 static void reset_adapter(struct slgt_info *info);
464 static void reset_port(struct slgt_info *info);
465 static void async_mode(struct slgt_info *info);
466 static void sync_mode(struct slgt_info *info);
467
468 static void rx_stop(struct slgt_info *info);
469 static void rx_start(struct slgt_info *info);
470 static void reset_rbufs(struct slgt_info *info);
471 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
472 static void rdma_reset(struct slgt_info *info);
473 static int rx_get_frame(struct slgt_info *info);
474 static int rx_get_buf(struct slgt_info *info);
475
476 static void tx_start(struct slgt_info *info);
477 static void tx_stop(struct slgt_info *info);
478 static void tx_set_idle(struct slgt_info *info);
479 static unsigned int free_tbuf_count(struct slgt_info *info);
480 static void reset_tbufs(struct slgt_info *info);
481 static void tdma_reset(struct slgt_info *info);
482 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
483
484 static void get_signals(struct slgt_info *info);
485 static void set_signals(struct slgt_info *info);
486 static void enable_loopback(struct slgt_info *info);
487 static void set_rate(struct slgt_info *info, u32 data_rate);
488
489 static int bh_action(struct slgt_info *info);
490 static void bh_handler(struct work_struct *work);
491 static void bh_transmit(struct slgt_info *info);
492 static void isr_serial(struct slgt_info *info);
493 static void isr_rdma(struct slgt_info *info);
494 static void isr_txeom(struct slgt_info *info, unsigned short status);
495 static void isr_tdma(struct slgt_info *info);
496 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
497
498 static int alloc_dma_bufs(struct slgt_info *info);
499 static void free_dma_bufs(struct slgt_info *info);
500 static int alloc_desc(struct slgt_info *info);
501 static void free_desc(struct slgt_info *info);
502 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
503 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
504
505 static int alloc_tmp_rbuf(struct slgt_info *info);
506 static void free_tmp_rbuf(struct slgt_info *info);
507
508 static void tx_timeout(unsigned long context);
509 static void rx_timeout(unsigned long context);
510
511 /*
512 * ioctl handlers
513 */
514 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
515 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
516 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
517 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
518 static int set_txidle(struct slgt_info *info, int idle_mode);
519 static int tx_enable(struct slgt_info *info, int enable);
520 static int tx_abort(struct slgt_info *info);
521 static int rx_enable(struct slgt_info *info, int enable);
522 static int modem_input_wait(struct slgt_info *info,int arg);
523 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
524 static int tiocmget(struct tty_struct *tty, struct file *file);
525 static int tiocmset(struct tty_struct *tty, struct file *file,
526 unsigned int set, unsigned int clear);
527 static void set_break(struct tty_struct *tty, int break_state);
528 static int get_interface(struct slgt_info *info, int __user *if_mode);
529 static int set_interface(struct slgt_info *info, int if_mode);
530 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
531 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
532 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
533
534 /*
535 * driver functions
536 */
537 static void add_device(struct slgt_info *info);
538 static void device_init(int adapter_num, struct pci_dev *pdev);
539 static int claim_resources(struct slgt_info *info);
540 static void release_resources(struct slgt_info *info);
541
542 /*
543 * DEBUG OUTPUT CODE
544 */
545 #ifndef DBGINFO
546 #define DBGINFO(fmt)
547 #endif
548 #ifndef DBGERR
549 #define DBGERR(fmt)
550 #endif
551 #ifndef DBGBH
552 #define DBGBH(fmt)
553 #endif
554 #ifndef DBGISR
555 #define DBGISR(fmt)
556 #endif
557
558 #ifdef DBGDATA
559 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
560 {
561 int i;
562 int linecount;
563 printk("%s %s data:\n",info->device_name, label);
564 while(count) {
565 linecount = (count > 16) ? 16 : count;
566 for(i=0; i < linecount; i++)
567 printk("%02X ",(unsigned char)data[i]);
568 for(;i<17;i++)
569 printk(" ");
570 for(i=0;i<linecount;i++) {
571 if (data[i]>=040 && data[i]<=0176)
572 printk("%c",data[i]);
573 else
574 printk(".");
575 }
576 printk("\n");
577 data += linecount;
578 count -= linecount;
579 }
580 }
581 #else
582 #define DBGDATA(info, buf, size, label)
583 #endif
584
585 #ifdef DBGTBUF
586 static void dump_tbufs(struct slgt_info *info)
587 {
588 int i;
589 printk("tbuf_current=%d\n", info->tbuf_current);
590 for (i=0 ; i < info->tbuf_count ; i++) {
591 printk("%d: count=%04X status=%04X\n",
592 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
593 }
594 }
595 #else
596 #define DBGTBUF(info)
597 #endif
598
599 #ifdef DBGRBUF
600 static void dump_rbufs(struct slgt_info *info)
601 {
602 int i;
603 printk("rbuf_current=%d\n", info->rbuf_current);
604 for (i=0 ; i < info->rbuf_count ; i++) {
605 printk("%d: count=%04X status=%04X\n",
606 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
607 }
608 }
609 #else
610 #define DBGRBUF(info)
611 #endif
612
613 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
614 {
615 #ifdef SANITY_CHECK
616 if (!info) {
617 printk("null struct slgt_info for (%s) in %s\n", devname, name);
618 return 1;
619 }
620 if (info->magic != MGSL_MAGIC) {
621 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
622 return 1;
623 }
624 #else
625 if (!info)
626 return 1;
627 #endif
628 return 0;
629 }
630
631 /**
632 * line discipline callback wrappers
633 *
634 * The wrappers maintain line discipline references
635 * while calling into the line discipline.
636 *
637 * ldisc_receive_buf - pass receive data to line discipline
638 */
639 static void ldisc_receive_buf(struct tty_struct *tty,
640 const __u8 *data, char *flags, int count)
641 {
642 struct tty_ldisc *ld;
643 if (!tty)
644 return;
645 ld = tty_ldisc_ref(tty);
646 if (ld) {
647 if (ld->receive_buf)
648 ld->receive_buf(tty, data, flags, count);
649 tty_ldisc_deref(ld);
650 }
651 }
652
653 /* tty callbacks */
654
655 static int open(struct tty_struct *tty, struct file *filp)
656 {
657 struct slgt_info *info;
658 int retval, line;
659 unsigned long flags;
660
661 line = tty->index;
662 if ((line < 0) || (line >= slgt_device_count)) {
663 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
664 return -ENODEV;
665 }
666
667 info = slgt_device_list;
668 while(info && info->line != line)
669 info = info->next_device;
670 if (sanity_check(info, tty->name, "open"))
671 return -ENODEV;
672 if (info->init_error) {
673 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
674 return -ENODEV;
675 }
676
677 tty->driver_data = info;
678 info->tty = tty;
679
680 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
681
682 /* If port is closing, signal caller to try again */
683 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
684 if (info->flags & ASYNC_CLOSING)
685 interruptible_sleep_on(&info->close_wait);
686 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
687 -EAGAIN : -ERESTARTSYS);
688 goto cleanup;
689 }
690
691 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
692
693 spin_lock_irqsave(&info->netlock, flags);
694 if (info->netcount) {
695 retval = -EBUSY;
696 spin_unlock_irqrestore(&info->netlock, flags);
697 goto cleanup;
698 }
699 info->count++;
700 spin_unlock_irqrestore(&info->netlock, flags);
701
702 if (info->count == 1) {
703 /* 1st open on this device, init hardware */
704 retval = startup(info);
705 if (retval < 0)
706 goto cleanup;
707 }
708
709 retval = block_til_ready(tty, filp, info);
710 if (retval) {
711 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
712 goto cleanup;
713 }
714
715 retval = 0;
716
717 cleanup:
718 if (retval) {
719 if (tty->count == 1)
720 info->tty = NULL; /* tty layer will release tty struct */
721 if(info->count)
722 info->count--;
723 }
724
725 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
726 return retval;
727 }
728
729 static void close(struct tty_struct *tty, struct file *filp)
730 {
731 struct slgt_info *info = tty->driver_data;
732
733 if (sanity_check(info, tty->name, "close"))
734 return;
735 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
736
737 if (!info->count)
738 return;
739
740 if (tty_hung_up_p(filp))
741 goto cleanup;
742
743 if ((tty->count == 1) && (info->count != 1)) {
744 /*
745 * tty->count is 1 and the tty structure will be freed.
746 * info->count should be one in this case.
747 * if it's not, correct it so that the port is shutdown.
748 */
749 DBGERR(("%s close: bad refcount; tty->count=1, "
750 "info->count=%d\n", info->device_name, info->count));
751 info->count = 1;
752 }
753
754 info->count--;
755
756 /* if at least one open remaining, leave hardware active */
757 if (info->count)
758 goto cleanup;
759
760 info->flags |= ASYNC_CLOSING;
761
762 /* set tty->closing to notify line discipline to
763 * only process XON/XOFF characters. Only the N_TTY
764 * discipline appears to use this (ppp does not).
765 */
766 tty->closing = 1;
767
768 /* wait for transmit data to clear all layers */
769
770 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
771 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
772 tty_wait_until_sent(tty, info->closing_wait);
773 }
774
775 if (info->flags & ASYNC_INITIALIZED)
776 wait_until_sent(tty, info->timeout);
777 if (tty->driver->flush_buffer)
778 tty->driver->flush_buffer(tty);
779 tty_ldisc_flush(tty);
780
781 shutdown(info);
782
783 tty->closing = 0;
784 info->tty = NULL;
785
786 if (info->blocked_open) {
787 if (info->close_delay) {
788 msleep_interruptible(jiffies_to_msecs(info->close_delay));
789 }
790 wake_up_interruptible(&info->open_wait);
791 }
792
793 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
794
795 wake_up_interruptible(&info->close_wait);
796
797 cleanup:
798 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
799 }
800
801 static void hangup(struct tty_struct *tty)
802 {
803 struct slgt_info *info = tty->driver_data;
804
805 if (sanity_check(info, tty->name, "hangup"))
806 return;
807 DBGINFO(("%s hangup\n", info->device_name));
808
809 flush_buffer(tty);
810 shutdown(info);
811
812 info->count = 0;
813 info->flags &= ~ASYNC_NORMAL_ACTIVE;
814 info->tty = NULL;
815
816 wake_up_interruptible(&info->open_wait);
817 }
818
819 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
820 {
821 struct slgt_info *info = tty->driver_data;
822 unsigned long flags;
823
824 DBGINFO(("%s set_termios\n", tty->driver->name));
825
826 /* just return if nothing has changed */
827 if ((tty->termios->c_cflag == old_termios->c_cflag)
828 && (RELEVANT_IFLAG(tty->termios->c_iflag)
829 == RELEVANT_IFLAG(old_termios->c_iflag)))
830 return;
831
832 change_params(info);
833
834 /* Handle transition to B0 status */
835 if (old_termios->c_cflag & CBAUD &&
836 !(tty->termios->c_cflag & CBAUD)) {
837 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
838 spin_lock_irqsave(&info->lock,flags);
839 set_signals(info);
840 spin_unlock_irqrestore(&info->lock,flags);
841 }
842
843 /* Handle transition away from B0 status */
844 if (!(old_termios->c_cflag & CBAUD) &&
845 tty->termios->c_cflag & CBAUD) {
846 info->signals |= SerialSignal_DTR;
847 if (!(tty->termios->c_cflag & CRTSCTS) ||
848 !test_bit(TTY_THROTTLED, &tty->flags)) {
849 info->signals |= SerialSignal_RTS;
850 }
851 spin_lock_irqsave(&info->lock,flags);
852 set_signals(info);
853 spin_unlock_irqrestore(&info->lock,flags);
854 }
855
856 /* Handle turning off CRTSCTS */
857 if (old_termios->c_cflag & CRTSCTS &&
858 !(tty->termios->c_cflag & CRTSCTS)) {
859 tty->hw_stopped = 0;
860 tx_release(tty);
861 }
862 }
863
864 static int write(struct tty_struct *tty,
865 const unsigned char *buf, int count)
866 {
867 int ret = 0;
868 struct slgt_info *info = tty->driver_data;
869 unsigned long flags;
870
871 if (sanity_check(info, tty->name, "write"))
872 goto cleanup;
873 DBGINFO(("%s write count=%d\n", info->device_name, count));
874
875 if (!info->tx_buf)
876 goto cleanup;
877
878 if (count > info->max_frame_size) {
879 ret = -EIO;
880 goto cleanup;
881 }
882
883 if (!count)
884 goto cleanup;
885
886 if (info->params.mode == MGSL_MODE_RAW ||
887 info->params.mode == MGSL_MODE_MONOSYNC ||
888 info->params.mode == MGSL_MODE_BISYNC) {
889 unsigned int bufs_needed = (count/DMABUFSIZE);
890 unsigned int bufs_free = free_tbuf_count(info);
891 if (count % DMABUFSIZE)
892 ++bufs_needed;
893 if (bufs_needed > bufs_free)
894 goto cleanup;
895 } else {
896 if (info->tx_active)
897 goto cleanup;
898 if (info->tx_count) {
899 /* send accumulated data from send_char() calls */
900 /* as frame and wait before accepting more data. */
901 tx_load(info, info->tx_buf, info->tx_count);
902 goto start;
903 }
904 }
905
906 ret = info->tx_count = count;
907 tx_load(info, buf, count);
908 goto start;
909
910 start:
911 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
912 spin_lock_irqsave(&info->lock,flags);
913 if (!info->tx_active)
914 tx_start(info);
915 spin_unlock_irqrestore(&info->lock,flags);
916 }
917
918 cleanup:
919 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
920 return ret;
921 }
922
923 static void put_char(struct tty_struct *tty, unsigned char ch)
924 {
925 struct slgt_info *info = tty->driver_data;
926 unsigned long flags;
927
928 if (sanity_check(info, tty->name, "put_char"))
929 return;
930 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
931 if (!info->tx_buf)
932 return;
933 spin_lock_irqsave(&info->lock,flags);
934 if (!info->tx_active && (info->tx_count < info->max_frame_size))
935 info->tx_buf[info->tx_count++] = ch;
936 spin_unlock_irqrestore(&info->lock,flags);
937 }
938
939 static void send_xchar(struct tty_struct *tty, char ch)
940 {
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "send_xchar"))
945 return;
946 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
947 info->x_char = ch;
948 if (ch) {
949 spin_lock_irqsave(&info->lock,flags);
950 if (!info->tx_enabled)
951 tx_start(info);
952 spin_unlock_irqrestore(&info->lock,flags);
953 }
954 }
955
956 static void wait_until_sent(struct tty_struct *tty, int timeout)
957 {
958 struct slgt_info *info = tty->driver_data;
959 unsigned long orig_jiffies, char_time;
960
961 if (!info )
962 return;
963 if (sanity_check(info, tty->name, "wait_until_sent"))
964 return;
965 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
966 if (!(info->flags & ASYNC_INITIALIZED))
967 goto exit;
968
969 orig_jiffies = jiffies;
970
971 /* Set check interval to 1/5 of estimated time to
972 * send a character, and make it at least 1. The check
973 * interval should also be less than the timeout.
974 * Note: use tight timings here to satisfy the NIST-PCTS.
975 */
976
977 if (info->params.data_rate) {
978 char_time = info->timeout/(32 * 5);
979 if (!char_time)
980 char_time++;
981 } else
982 char_time = 1;
983
984 if (timeout)
985 char_time = min_t(unsigned long, char_time, timeout);
986
987 while (info->tx_active) {
988 msleep_interruptible(jiffies_to_msecs(char_time));
989 if (signal_pending(current))
990 break;
991 if (timeout && time_after(jiffies, orig_jiffies + timeout))
992 break;
993 }
994
995 exit:
996 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
997 }
998
999 static int write_room(struct tty_struct *tty)
1000 {
1001 struct slgt_info *info = tty->driver_data;
1002 int ret;
1003
1004 if (sanity_check(info, tty->name, "write_room"))
1005 return 0;
1006 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1007 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1008 return ret;
1009 }
1010
1011 static void flush_chars(struct tty_struct *tty)
1012 {
1013 struct slgt_info *info = tty->driver_data;
1014 unsigned long flags;
1015
1016 if (sanity_check(info, tty->name, "flush_chars"))
1017 return;
1018 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1019
1020 if (info->tx_count <= 0 || tty->stopped ||
1021 tty->hw_stopped || !info->tx_buf)
1022 return;
1023
1024 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1025
1026 spin_lock_irqsave(&info->lock,flags);
1027 if (!info->tx_active && info->tx_count) {
1028 tx_load(info, info->tx_buf,info->tx_count);
1029 tx_start(info);
1030 }
1031 spin_unlock_irqrestore(&info->lock,flags);
1032 }
1033
1034 static void flush_buffer(struct tty_struct *tty)
1035 {
1036 struct slgt_info *info = tty->driver_data;
1037 unsigned long flags;
1038
1039 if (sanity_check(info, tty->name, "flush_buffer"))
1040 return;
1041 DBGINFO(("%s flush_buffer\n", info->device_name));
1042
1043 spin_lock_irqsave(&info->lock,flags);
1044 if (!info->tx_active)
1045 info->tx_count = 0;
1046 spin_unlock_irqrestore(&info->lock,flags);
1047
1048 tty_wakeup(tty);
1049 }
1050
1051 /*
1052 * throttle (stop) transmitter
1053 */
1054 static void tx_hold(struct tty_struct *tty)
1055 {
1056 struct slgt_info *info = tty->driver_data;
1057 unsigned long flags;
1058
1059 if (sanity_check(info, tty->name, "tx_hold"))
1060 return;
1061 DBGINFO(("%s tx_hold\n", info->device_name));
1062 spin_lock_irqsave(&info->lock,flags);
1063 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1064 tx_stop(info);
1065 spin_unlock_irqrestore(&info->lock,flags);
1066 }
1067
1068 /*
1069 * release (start) transmitter
1070 */
1071 static void tx_release(struct tty_struct *tty)
1072 {
1073 struct slgt_info *info = tty->driver_data;
1074 unsigned long flags;
1075
1076 if (sanity_check(info, tty->name, "tx_release"))
1077 return;
1078 DBGINFO(("%s tx_release\n", info->device_name));
1079 spin_lock_irqsave(&info->lock,flags);
1080 if (!info->tx_active && info->tx_count) {
1081 tx_load(info, info->tx_buf, info->tx_count);
1082 tx_start(info);
1083 }
1084 spin_unlock_irqrestore(&info->lock,flags);
1085 }
1086
1087 /*
1088 * Service an IOCTL request
1089 *
1090 * Arguments
1091 *
1092 * tty pointer to tty instance data
1093 * file pointer to associated file object for device
1094 * cmd IOCTL command code
1095 * arg command argument/context
1096 *
1097 * Return 0 if success, otherwise error code
1098 */
1099 static int ioctl(struct tty_struct *tty, struct file *file,
1100 unsigned int cmd, unsigned long arg)
1101 {
1102 struct slgt_info *info = tty->driver_data;
1103 struct mgsl_icount cnow; /* kernel counter temps */
1104 struct serial_icounter_struct __user *p_cuser; /* user space */
1105 unsigned long flags;
1106 void __user *argp = (void __user *)arg;
1107
1108 if (sanity_check(info, tty->name, "ioctl"))
1109 return -ENODEV;
1110 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1111
1112 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1113 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1114 if (tty->flags & (1 << TTY_IO_ERROR))
1115 return -EIO;
1116 }
1117
1118 switch (cmd) {
1119 case MGSL_IOCGPARAMS:
1120 return get_params(info, argp);
1121 case MGSL_IOCSPARAMS:
1122 return set_params(info, argp);
1123 case MGSL_IOCGTXIDLE:
1124 return get_txidle(info, argp);
1125 case MGSL_IOCSTXIDLE:
1126 return set_txidle(info, (int)arg);
1127 case MGSL_IOCTXENABLE:
1128 return tx_enable(info, (int)arg);
1129 case MGSL_IOCRXENABLE:
1130 return rx_enable(info, (int)arg);
1131 case MGSL_IOCTXABORT:
1132 return tx_abort(info);
1133 case MGSL_IOCGSTATS:
1134 return get_stats(info, argp);
1135 case MGSL_IOCWAITEVENT:
1136 return wait_mgsl_event(info, argp);
1137 case TIOCMIWAIT:
1138 return modem_input_wait(info,(int)arg);
1139 case MGSL_IOCGIF:
1140 return get_interface(info, argp);
1141 case MGSL_IOCSIF:
1142 return set_interface(info,(int)arg);
1143 case MGSL_IOCSGPIO:
1144 return set_gpio(info, argp);
1145 case MGSL_IOCGGPIO:
1146 return get_gpio(info, argp);
1147 case MGSL_IOCWAITGPIO:
1148 return wait_gpio(info, argp);
1149 case TIOCGICOUNT:
1150 spin_lock_irqsave(&info->lock,flags);
1151 cnow = info->icount;
1152 spin_unlock_irqrestore(&info->lock,flags);
1153 p_cuser = argp;
1154 if (put_user(cnow.cts, &p_cuser->cts) ||
1155 put_user(cnow.dsr, &p_cuser->dsr) ||
1156 put_user(cnow.rng, &p_cuser->rng) ||
1157 put_user(cnow.dcd, &p_cuser->dcd) ||
1158 put_user(cnow.rx, &p_cuser->rx) ||
1159 put_user(cnow.tx, &p_cuser->tx) ||
1160 put_user(cnow.frame, &p_cuser->frame) ||
1161 put_user(cnow.overrun, &p_cuser->overrun) ||
1162 put_user(cnow.parity, &p_cuser->parity) ||
1163 put_user(cnow.brk, &p_cuser->brk) ||
1164 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1165 return -EFAULT;
1166 return 0;
1167 default:
1168 return -ENOIOCTLCMD;
1169 }
1170 return 0;
1171 }
1172
1173 /*
1174 * proc fs support
1175 */
1176 static inline int line_info(char *buf, struct slgt_info *info)
1177 {
1178 char stat_buf[30];
1179 int ret;
1180 unsigned long flags;
1181
1182 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1183 info->device_name, info->phys_reg_addr,
1184 info->irq_level, info->max_frame_size);
1185
1186 /* output current serial signal states */
1187 spin_lock_irqsave(&info->lock,flags);
1188 get_signals(info);
1189 spin_unlock_irqrestore(&info->lock,flags);
1190
1191 stat_buf[0] = 0;
1192 stat_buf[1] = 0;
1193 if (info->signals & SerialSignal_RTS)
1194 strcat(stat_buf, "|RTS");
1195 if (info->signals & SerialSignal_CTS)
1196 strcat(stat_buf, "|CTS");
1197 if (info->signals & SerialSignal_DTR)
1198 strcat(stat_buf, "|DTR");
1199 if (info->signals & SerialSignal_DSR)
1200 strcat(stat_buf, "|DSR");
1201 if (info->signals & SerialSignal_DCD)
1202 strcat(stat_buf, "|CD");
1203 if (info->signals & SerialSignal_RI)
1204 strcat(stat_buf, "|RI");
1205
1206 if (info->params.mode != MGSL_MODE_ASYNC) {
1207 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1208 info->icount.txok, info->icount.rxok);
1209 if (info->icount.txunder)
1210 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1211 if (info->icount.txabort)
1212 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1213 if (info->icount.rxshort)
1214 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1215 if (info->icount.rxlong)
1216 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1217 if (info->icount.rxover)
1218 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1219 if (info->icount.rxcrc)
1220 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1221 } else {
1222 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1223 info->icount.tx, info->icount.rx);
1224 if (info->icount.frame)
1225 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1226 if (info->icount.parity)
1227 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1228 if (info->icount.brk)
1229 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1230 if (info->icount.overrun)
1231 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1232 }
1233
1234 /* Append serial signal status to end */
1235 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1236
1237 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1238 info->tx_active,info->bh_requested,info->bh_running,
1239 info->pending_bh);
1240
1241 return ret;
1242 }
1243
1244 /* Called to print information about devices
1245 */
1246 static int read_proc(char *page, char **start, off_t off, int count,
1247 int *eof, void *data)
1248 {
1249 int len = 0, l;
1250 off_t begin = 0;
1251 struct slgt_info *info;
1252
1253 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1254
1255 info = slgt_device_list;
1256 while( info ) {
1257 l = line_info(page + len, info);
1258 len += l;
1259 if (len+begin > off+count)
1260 goto done;
1261 if (len+begin < off) {
1262 begin += len;
1263 len = 0;
1264 }
1265 info = info->next_device;
1266 }
1267
1268 *eof = 1;
1269 done:
1270 if (off >= len+begin)
1271 return 0;
1272 *start = page + (off-begin);
1273 return ((count < begin+len-off) ? count : begin+len-off);
1274 }
1275
1276 /*
1277 * return count of bytes in transmit buffer
1278 */
1279 static int chars_in_buffer(struct tty_struct *tty)
1280 {
1281 struct slgt_info *info = tty->driver_data;
1282 if (sanity_check(info, tty->name, "chars_in_buffer"))
1283 return 0;
1284 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1285 return info->tx_count;
1286 }
1287
1288 /*
1289 * signal remote device to throttle send data (our receive data)
1290 */
1291 static void throttle(struct tty_struct * tty)
1292 {
1293 struct slgt_info *info = tty->driver_data;
1294 unsigned long flags;
1295
1296 if (sanity_check(info, tty->name, "throttle"))
1297 return;
1298 DBGINFO(("%s throttle\n", info->device_name));
1299 if (I_IXOFF(tty))
1300 send_xchar(tty, STOP_CHAR(tty));
1301 if (tty->termios->c_cflag & CRTSCTS) {
1302 spin_lock_irqsave(&info->lock,flags);
1303 info->signals &= ~SerialSignal_RTS;
1304 set_signals(info);
1305 spin_unlock_irqrestore(&info->lock,flags);
1306 }
1307 }
1308
1309 /*
1310 * signal remote device to stop throttling send data (our receive data)
1311 */
1312 static void unthrottle(struct tty_struct * tty)
1313 {
1314 struct slgt_info *info = tty->driver_data;
1315 unsigned long flags;
1316
1317 if (sanity_check(info, tty->name, "unthrottle"))
1318 return;
1319 DBGINFO(("%s unthrottle\n", info->device_name));
1320 if (I_IXOFF(tty)) {
1321 if (info->x_char)
1322 info->x_char = 0;
1323 else
1324 send_xchar(tty, START_CHAR(tty));
1325 }
1326 if (tty->termios->c_cflag & CRTSCTS) {
1327 spin_lock_irqsave(&info->lock,flags);
1328 info->signals |= SerialSignal_RTS;
1329 set_signals(info);
1330 spin_unlock_irqrestore(&info->lock,flags);
1331 }
1332 }
1333
1334 /*
1335 * set or clear transmit break condition
1336 * break_state -1=set break condition, 0=clear
1337 */
1338 static void set_break(struct tty_struct *tty, int break_state)
1339 {
1340 struct slgt_info *info = tty->driver_data;
1341 unsigned short value;
1342 unsigned long flags;
1343
1344 if (sanity_check(info, tty->name, "set_break"))
1345 return;
1346 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1347
1348 spin_lock_irqsave(&info->lock,flags);
1349 value = rd_reg16(info, TCR);
1350 if (break_state == -1)
1351 value |= BIT6;
1352 else
1353 value &= ~BIT6;
1354 wr_reg16(info, TCR, value);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356 }
1357
1358 #if SYNCLINK_GENERIC_HDLC
1359
1360 /**
1361 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1362 * set encoding and frame check sequence (FCS) options
1363 *
1364 * dev pointer to network device structure
1365 * encoding serial encoding setting
1366 * parity FCS setting
1367 *
1368 * returns 0 if success, otherwise error code
1369 */
1370 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1371 unsigned short parity)
1372 {
1373 struct slgt_info *info = dev_to_port(dev);
1374 unsigned char new_encoding;
1375 unsigned short new_crctype;
1376
1377 /* return error if TTY interface open */
1378 if (info->count)
1379 return -EBUSY;
1380
1381 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1382
1383 switch (encoding)
1384 {
1385 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1386 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1387 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1388 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1389 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1390 default: return -EINVAL;
1391 }
1392
1393 switch (parity)
1394 {
1395 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1396 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1397 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1398 default: return -EINVAL;
1399 }
1400
1401 info->params.encoding = new_encoding;
1402 info->params.crc_type = new_crctype;
1403
1404 /* if network interface up, reprogram hardware */
1405 if (info->netcount)
1406 program_hw(info);
1407
1408 return 0;
1409 }
1410
1411 /**
1412 * called by generic HDLC layer to send frame
1413 *
1414 * skb socket buffer containing HDLC frame
1415 * dev pointer to network device structure
1416 *
1417 * returns 0 if success, otherwise error code
1418 */
1419 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1420 {
1421 struct slgt_info *info = dev_to_port(dev);
1422 struct net_device_stats *stats = hdlc_stats(dev);
1423 unsigned long flags;
1424
1425 DBGINFO(("%s hdlc_xmit\n", dev->name));
1426
1427 /* stop sending until this frame completes */
1428 netif_stop_queue(dev);
1429
1430 /* copy data to device buffers */
1431 info->tx_count = skb->len;
1432 tx_load(info, skb->data, skb->len);
1433
1434 /* update network statistics */
1435 stats->tx_packets++;
1436 stats->tx_bytes += skb->len;
1437
1438 /* done with socket buffer, so free it */
1439 dev_kfree_skb(skb);
1440
1441 /* save start time for transmit timeout detection */
1442 dev->trans_start = jiffies;
1443
1444 /* start hardware transmitter if necessary */
1445 spin_lock_irqsave(&info->lock,flags);
1446 if (!info->tx_active)
1447 tx_start(info);
1448 spin_unlock_irqrestore(&info->lock,flags);
1449
1450 return 0;
1451 }
1452
1453 /**
1454 * called by network layer when interface enabled
1455 * claim resources and initialize hardware
1456 *
1457 * dev pointer to network device structure
1458 *
1459 * returns 0 if success, otherwise error code
1460 */
1461 static int hdlcdev_open(struct net_device *dev)
1462 {
1463 struct slgt_info *info = dev_to_port(dev);
1464 int rc;
1465 unsigned long flags;
1466
1467 DBGINFO(("%s hdlcdev_open\n", dev->name));
1468
1469 /* generic HDLC layer open processing */
1470 if ((rc = hdlc_open(dev)))
1471 return rc;
1472
1473 /* arbitrate between network and tty opens */
1474 spin_lock_irqsave(&info->netlock, flags);
1475 if (info->count != 0 || info->netcount != 0) {
1476 DBGINFO(("%s hdlc_open busy\n", dev->name));
1477 spin_unlock_irqrestore(&info->netlock, flags);
1478 return -EBUSY;
1479 }
1480 info->netcount=1;
1481 spin_unlock_irqrestore(&info->netlock, flags);
1482
1483 /* claim resources and init adapter */
1484 if ((rc = startup(info)) != 0) {
1485 spin_lock_irqsave(&info->netlock, flags);
1486 info->netcount=0;
1487 spin_unlock_irqrestore(&info->netlock, flags);
1488 return rc;
1489 }
1490
1491 /* assert DTR and RTS, apply hardware settings */
1492 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1493 program_hw(info);
1494
1495 /* enable network layer transmit */
1496 dev->trans_start = jiffies;
1497 netif_start_queue(dev);
1498
1499 /* inform generic HDLC layer of current DCD status */
1500 spin_lock_irqsave(&info->lock, flags);
1501 get_signals(info);
1502 spin_unlock_irqrestore(&info->lock, flags);
1503 if (info->signals & SerialSignal_DCD)
1504 netif_carrier_on(dev);
1505 else
1506 netif_carrier_off(dev);
1507 return 0;
1508 }
1509
1510 /**
1511 * called by network layer when interface is disabled
1512 * shutdown hardware and release resources
1513 *
1514 * dev pointer to network device structure
1515 *
1516 * returns 0 if success, otherwise error code
1517 */
1518 static int hdlcdev_close(struct net_device *dev)
1519 {
1520 struct slgt_info *info = dev_to_port(dev);
1521 unsigned long flags;
1522
1523 DBGINFO(("%s hdlcdev_close\n", dev->name));
1524
1525 netif_stop_queue(dev);
1526
1527 /* shutdown adapter and release resources */
1528 shutdown(info);
1529
1530 hdlc_close(dev);
1531
1532 spin_lock_irqsave(&info->netlock, flags);
1533 info->netcount=0;
1534 spin_unlock_irqrestore(&info->netlock, flags);
1535
1536 return 0;
1537 }
1538
1539 /**
1540 * called by network layer to process IOCTL call to network device
1541 *
1542 * dev pointer to network device structure
1543 * ifr pointer to network interface request structure
1544 * cmd IOCTL command code
1545 *
1546 * returns 0 if success, otherwise error code
1547 */
1548 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1549 {
1550 const size_t size = sizeof(sync_serial_settings);
1551 sync_serial_settings new_line;
1552 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1553 struct slgt_info *info = dev_to_port(dev);
1554 unsigned int flags;
1555
1556 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1557
1558 /* return error if TTY interface open */
1559 if (info->count)
1560 return -EBUSY;
1561
1562 if (cmd != SIOCWANDEV)
1563 return hdlc_ioctl(dev, ifr, cmd);
1564
1565 switch(ifr->ifr_settings.type) {
1566 case IF_GET_IFACE: /* return current sync_serial_settings */
1567
1568 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1569 if (ifr->ifr_settings.size < size) {
1570 ifr->ifr_settings.size = size; /* data size wanted */
1571 return -ENOBUFS;
1572 }
1573
1574 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1575 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1576 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1577 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1578
1579 switch (flags){
1580 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1581 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1582 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1583 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1584 default: new_line.clock_type = CLOCK_DEFAULT;
1585 }
1586
1587 new_line.clock_rate = info->params.clock_speed;
1588 new_line.loopback = info->params.loopback ? 1:0;
1589
1590 if (copy_to_user(line, &new_line, size))
1591 return -EFAULT;
1592 return 0;
1593
1594 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1595
1596 if(!capable(CAP_NET_ADMIN))
1597 return -EPERM;
1598 if (copy_from_user(&new_line, line, size))
1599 return -EFAULT;
1600
1601 switch (new_line.clock_type)
1602 {
1603 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1604 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1605 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1606 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1607 case CLOCK_DEFAULT: flags = info->params.flags &
1608 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1609 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1610 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1611 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1612 default: return -EINVAL;
1613 }
1614
1615 if (new_line.loopback != 0 && new_line.loopback != 1)
1616 return -EINVAL;
1617
1618 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1619 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1620 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1621 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1622 info->params.flags |= flags;
1623
1624 info->params.loopback = new_line.loopback;
1625
1626 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1627 info->params.clock_speed = new_line.clock_rate;
1628 else
1629 info->params.clock_speed = 0;
1630
1631 /* if network interface up, reprogram hardware */
1632 if (info->netcount)
1633 program_hw(info);
1634 return 0;
1635
1636 default:
1637 return hdlc_ioctl(dev, ifr, cmd);
1638 }
1639 }
1640
1641 /**
1642 * called by network layer when transmit timeout is detected
1643 *
1644 * dev pointer to network device structure
1645 */
1646 static void hdlcdev_tx_timeout(struct net_device *dev)
1647 {
1648 struct slgt_info *info = dev_to_port(dev);
1649 struct net_device_stats *stats = hdlc_stats(dev);
1650 unsigned long flags;
1651
1652 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1653
1654 stats->tx_errors++;
1655 stats->tx_aborted_errors++;
1656
1657 spin_lock_irqsave(&info->lock,flags);
1658 tx_stop(info);
1659 spin_unlock_irqrestore(&info->lock,flags);
1660
1661 netif_wake_queue(dev);
1662 }
1663
1664 /**
1665 * called by device driver when transmit completes
1666 * reenable network layer transmit if stopped
1667 *
1668 * info pointer to device instance information
1669 */
1670 static void hdlcdev_tx_done(struct slgt_info *info)
1671 {
1672 if (netif_queue_stopped(info->netdev))
1673 netif_wake_queue(info->netdev);
1674 }
1675
1676 /**
1677 * called by device driver when frame received
1678 * pass frame to network layer
1679 *
1680 * info pointer to device instance information
1681 * buf pointer to buffer contianing frame data
1682 * size count of data bytes in buf
1683 */
1684 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1685 {
1686 struct sk_buff *skb = dev_alloc_skb(size);
1687 struct net_device *dev = info->netdev;
1688 struct net_device_stats *stats = hdlc_stats(dev);
1689
1690 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1691
1692 if (skb == NULL) {
1693 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1694 stats->rx_dropped++;
1695 return;
1696 }
1697
1698 memcpy(skb_put(skb, size),buf,size);
1699
1700 skb->protocol = hdlc_type_trans(skb, info->netdev);
1701
1702 stats->rx_packets++;
1703 stats->rx_bytes += size;
1704
1705 netif_rx(skb);
1706
1707 info->netdev->last_rx = jiffies;
1708 }
1709
1710 /**
1711 * called by device driver when adding device instance
1712 * do generic HDLC initialization
1713 *
1714 * info pointer to device instance information
1715 *
1716 * returns 0 if success, otherwise error code
1717 */
1718 static int hdlcdev_init(struct slgt_info *info)
1719 {
1720 int rc;
1721 struct net_device *dev;
1722 hdlc_device *hdlc;
1723
1724 /* allocate and initialize network and HDLC layer objects */
1725
1726 if (!(dev = alloc_hdlcdev(info))) {
1727 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1728 return -ENOMEM;
1729 }
1730
1731 /* for network layer reporting purposes only */
1732 dev->mem_start = info->phys_reg_addr;
1733 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1734 dev->irq = info->irq_level;
1735
1736 /* network layer callbacks and settings */
1737 dev->do_ioctl = hdlcdev_ioctl;
1738 dev->open = hdlcdev_open;
1739 dev->stop = hdlcdev_close;
1740 dev->tx_timeout = hdlcdev_tx_timeout;
1741 dev->watchdog_timeo = 10*HZ;
1742 dev->tx_queue_len = 50;
1743
1744 /* generic HDLC layer callbacks and settings */
1745 hdlc = dev_to_hdlc(dev);
1746 hdlc->attach = hdlcdev_attach;
1747 hdlc->xmit = hdlcdev_xmit;
1748
1749 /* register objects with HDLC layer */
1750 if ((rc = register_hdlc_device(dev))) {
1751 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1752 free_netdev(dev);
1753 return rc;
1754 }
1755
1756 info->netdev = dev;
1757 return 0;
1758 }
1759
1760 /**
1761 * called by device driver when removing device instance
1762 * do generic HDLC cleanup
1763 *
1764 * info pointer to device instance information
1765 */
1766 static void hdlcdev_exit(struct slgt_info *info)
1767 {
1768 unregister_hdlc_device(info->netdev);
1769 free_netdev(info->netdev);
1770 info->netdev = NULL;
1771 }
1772
1773 #endif /* ifdef CONFIG_HDLC */
1774
1775 /*
1776 * get async data from rx DMA buffers
1777 */
1778 static void rx_async(struct slgt_info *info)
1779 {
1780 struct tty_struct *tty = info->tty;
1781 struct mgsl_icount *icount = &info->icount;
1782 unsigned int start, end;
1783 unsigned char *p;
1784 unsigned char status;
1785 struct slgt_desc *bufs = info->rbufs;
1786 int i, count;
1787 int chars = 0;
1788 int stat;
1789 unsigned char ch;
1790
1791 start = end = info->rbuf_current;
1792
1793 while(desc_complete(bufs[end])) {
1794 count = desc_count(bufs[end]) - info->rbuf_index;
1795 p = bufs[end].buf + info->rbuf_index;
1796
1797 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1798 DBGDATA(info, p, count, "rx");
1799
1800 for(i=0 ; i < count; i+=2, p+=2) {
1801 ch = *p;
1802 icount->rx++;
1803
1804 stat = 0;
1805
1806 if ((status = *(p+1) & (BIT1 + BIT0))) {
1807 if (status & BIT1)
1808 icount->parity++;
1809 else if (status & BIT0)
1810 icount->frame++;
1811 /* discard char if tty control flags say so */
1812 if (status & info->ignore_status_mask)
1813 continue;
1814 if (status & BIT1)
1815 stat = TTY_PARITY;
1816 else if (status & BIT0)
1817 stat = TTY_FRAME;
1818 }
1819 if (tty) {
1820 tty_insert_flip_char(tty, ch, stat);
1821 chars++;
1822 }
1823 }
1824
1825 if (i < count) {
1826 /* receive buffer not completed */
1827 info->rbuf_index += i;
1828 mod_timer(&info->rx_timer, jiffies + 1);
1829 break;
1830 }
1831
1832 info->rbuf_index = 0;
1833 free_rbufs(info, end, end);
1834
1835 if (++end == info->rbuf_count)
1836 end = 0;
1837
1838 /* if entire list searched then no frame available */
1839 if (end == start)
1840 break;
1841 }
1842
1843 if (tty && chars)
1844 tty_flip_buffer_push(tty);
1845 }
1846
1847 /*
1848 * return next bottom half action to perform
1849 */
1850 static int bh_action(struct slgt_info *info)
1851 {
1852 unsigned long flags;
1853 int rc;
1854
1855 spin_lock_irqsave(&info->lock,flags);
1856
1857 if (info->pending_bh & BH_RECEIVE) {
1858 info->pending_bh &= ~BH_RECEIVE;
1859 rc = BH_RECEIVE;
1860 } else if (info->pending_bh & BH_TRANSMIT) {
1861 info->pending_bh &= ~BH_TRANSMIT;
1862 rc = BH_TRANSMIT;
1863 } else if (info->pending_bh & BH_STATUS) {
1864 info->pending_bh &= ~BH_STATUS;
1865 rc = BH_STATUS;
1866 } else {
1867 /* Mark BH routine as complete */
1868 info->bh_running = 0;
1869 info->bh_requested = 0;
1870 rc = 0;
1871 }
1872
1873 spin_unlock_irqrestore(&info->lock,flags);
1874
1875 return rc;
1876 }
1877
1878 /*
1879 * perform bottom half processing
1880 */
1881 static void bh_handler(struct work_struct *work)
1882 {
1883 struct slgt_info *info = container_of(work, struct slgt_info, task);
1884 int action;
1885
1886 if (!info)
1887 return;
1888 info->bh_running = 1;
1889
1890 while((action = bh_action(info))) {
1891 switch (action) {
1892 case BH_RECEIVE:
1893 DBGBH(("%s bh receive\n", info->device_name));
1894 switch(info->params.mode) {
1895 case MGSL_MODE_ASYNC:
1896 rx_async(info);
1897 break;
1898 case MGSL_MODE_HDLC:
1899 while(rx_get_frame(info));
1900 break;
1901 case MGSL_MODE_RAW:
1902 case MGSL_MODE_MONOSYNC:
1903 case MGSL_MODE_BISYNC:
1904 while(rx_get_buf(info));
1905 break;
1906 }
1907 /* restart receiver if rx DMA buffers exhausted */
1908 if (info->rx_restart)
1909 rx_start(info);
1910 break;
1911 case BH_TRANSMIT:
1912 bh_transmit(info);
1913 break;
1914 case BH_STATUS:
1915 DBGBH(("%s bh status\n", info->device_name));
1916 info->ri_chkcount = 0;
1917 info->dsr_chkcount = 0;
1918 info->dcd_chkcount = 0;
1919 info->cts_chkcount = 0;
1920 break;
1921 default:
1922 DBGBH(("%s unknown action\n", info->device_name));
1923 break;
1924 }
1925 }
1926 DBGBH(("%s bh_handler exit\n", info->device_name));
1927 }
1928
1929 static void bh_transmit(struct slgt_info *info)
1930 {
1931 struct tty_struct *tty = info->tty;
1932
1933 DBGBH(("%s bh_transmit\n", info->device_name));
1934 if (tty)
1935 tty_wakeup(tty);
1936 }
1937
1938 static void dsr_change(struct slgt_info *info)
1939 {
1940 get_signals(info);
1941 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1942 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1943 slgt_irq_off(info, IRQ_DSR);
1944 return;
1945 }
1946 info->icount.dsr++;
1947 if (info->signals & SerialSignal_DSR)
1948 info->input_signal_events.dsr_up++;
1949 else
1950 info->input_signal_events.dsr_down++;
1951 wake_up_interruptible(&info->status_event_wait_q);
1952 wake_up_interruptible(&info->event_wait_q);
1953 info->pending_bh |= BH_STATUS;
1954 }
1955
1956 static void cts_change(struct slgt_info *info)
1957 {
1958 get_signals(info);
1959 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1960 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1961 slgt_irq_off(info, IRQ_CTS);
1962 return;
1963 }
1964 info->icount.cts++;
1965 if (info->signals & SerialSignal_CTS)
1966 info->input_signal_events.cts_up++;
1967 else
1968 info->input_signal_events.cts_down++;
1969 wake_up_interruptible(&info->status_event_wait_q);
1970 wake_up_interruptible(&info->event_wait_q);
1971 info->pending_bh |= BH_STATUS;
1972
1973 if (info->flags & ASYNC_CTS_FLOW) {
1974 if (info->tty) {
1975 if (info->tty->hw_stopped) {
1976 if (info->signals & SerialSignal_CTS) {
1977 info->tty->hw_stopped = 0;
1978 info->pending_bh |= BH_TRANSMIT;
1979 return;
1980 }
1981 } else {
1982 if (!(info->signals & SerialSignal_CTS))
1983 info->tty->hw_stopped = 1;
1984 }
1985 }
1986 }
1987 }
1988
1989 static void dcd_change(struct slgt_info *info)
1990 {
1991 get_signals(info);
1992 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1993 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1994 slgt_irq_off(info, IRQ_DCD);
1995 return;
1996 }
1997 info->icount.dcd++;
1998 if (info->signals & SerialSignal_DCD) {
1999 info->input_signal_events.dcd_up++;
2000 } else {
2001 info->input_signal_events.dcd_down++;
2002 }
2003 #if SYNCLINK_GENERIC_HDLC
2004 if (info->netcount) {
2005 if (info->signals & SerialSignal_DCD)
2006 netif_carrier_on(info->netdev);
2007 else
2008 netif_carrier_off(info->netdev);
2009 }
2010 #endif
2011 wake_up_interruptible(&info->status_event_wait_q);
2012 wake_up_interruptible(&info->event_wait_q);
2013 info->pending_bh |= BH_STATUS;
2014
2015 if (info->flags & ASYNC_CHECK_CD) {
2016 if (info->signals & SerialSignal_DCD)
2017 wake_up_interruptible(&info->open_wait);
2018 else {
2019 if (info->tty)
2020 tty_hangup(info->tty);
2021 }
2022 }
2023 }
2024
2025 static void ri_change(struct slgt_info *info)
2026 {
2027 get_signals(info);
2028 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2029 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2030 slgt_irq_off(info, IRQ_RI);
2031 return;
2032 }
2033 info->icount.dcd++;
2034 if (info->signals & SerialSignal_RI) {
2035 info->input_signal_events.ri_up++;
2036 } else {
2037 info->input_signal_events.ri_down++;
2038 }
2039 wake_up_interruptible(&info->status_event_wait_q);
2040 wake_up_interruptible(&info->event_wait_q);
2041 info->pending_bh |= BH_STATUS;
2042 }
2043
2044 static void isr_serial(struct slgt_info *info)
2045 {
2046 unsigned short status = rd_reg16(info, SSR);
2047
2048 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2049
2050 wr_reg16(info, SSR, status); /* clear pending */
2051
2052 info->irq_occurred = 1;
2053
2054 if (info->params.mode == MGSL_MODE_ASYNC) {
2055 if (status & IRQ_TXIDLE) {
2056 if (info->tx_count)
2057 isr_txeom(info, status);
2058 }
2059 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2060 info->icount.brk++;
2061 /* process break detection if tty control allows */
2062 if (info->tty) {
2063 if (!(status & info->ignore_status_mask)) {
2064 if (info->read_status_mask & MASK_BREAK) {
2065 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2066 if (info->flags & ASYNC_SAK)
2067 do_SAK(info->tty);
2068 }
2069 }
2070 }
2071 }
2072 } else {
2073 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2074 isr_txeom(info, status);
2075
2076 if (status & IRQ_RXIDLE) {
2077 if (status & RXIDLE)
2078 info->icount.rxidle++;
2079 else
2080 info->icount.exithunt++;
2081 wake_up_interruptible(&info->event_wait_q);
2082 }
2083
2084 if (status & IRQ_RXOVER)
2085 rx_start(info);
2086 }
2087
2088 if (status & IRQ_DSR)
2089 dsr_change(info);
2090 if (status & IRQ_CTS)
2091 cts_change(info);
2092 if (status & IRQ_DCD)
2093 dcd_change(info);
2094 if (status & IRQ_RI)
2095 ri_change(info);
2096 }
2097
2098 static void isr_rdma(struct slgt_info *info)
2099 {
2100 unsigned int status = rd_reg32(info, RDCSR);
2101
2102 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2103
2104 /* RDCSR (rx DMA control/status)
2105 *
2106 * 31..07 reserved
2107 * 06 save status byte to DMA buffer
2108 * 05 error
2109 * 04 eol (end of list)
2110 * 03 eob (end of buffer)
2111 * 02 IRQ enable
2112 * 01 reset
2113 * 00 enable
2114 */
2115 wr_reg32(info, RDCSR, status); /* clear pending */
2116
2117 if (status & (BIT5 + BIT4)) {
2118 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2119 info->rx_restart = 1;
2120 }
2121 info->pending_bh |= BH_RECEIVE;
2122 }
2123
2124 static void isr_tdma(struct slgt_info *info)
2125 {
2126 unsigned int status = rd_reg32(info, TDCSR);
2127
2128 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2129
2130 /* TDCSR (tx DMA control/status)
2131 *
2132 * 31..06 reserved
2133 * 05 error
2134 * 04 eol (end of list)
2135 * 03 eob (end of buffer)
2136 * 02 IRQ enable
2137 * 01 reset
2138 * 00 enable
2139 */
2140 wr_reg32(info, TDCSR, status); /* clear pending */
2141
2142 if (status & (BIT5 + BIT4 + BIT3)) {
2143 // another transmit buffer has completed
2144 // run bottom half to get more send data from user
2145 info->pending_bh |= BH_TRANSMIT;
2146 }
2147 }
2148
2149 static void isr_txeom(struct slgt_info *info, unsigned short status)
2150 {
2151 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2152
2153 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2154 tdma_reset(info);
2155 reset_tbufs(info);
2156 if (status & IRQ_TXUNDER) {
2157 unsigned short val = rd_reg16(info, TCR);
2158 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2159 wr_reg16(info, TCR, val); /* clear reset bit */
2160 }
2161
2162 if (info->tx_active) {
2163 if (info->params.mode != MGSL_MODE_ASYNC) {
2164 if (status & IRQ_TXUNDER)
2165 info->icount.txunder++;
2166 else if (status & IRQ_TXIDLE)
2167 info->icount.txok++;
2168 }
2169
2170 info->tx_active = 0;
2171 info->tx_count = 0;
2172
2173 del_timer(&info->tx_timer);
2174
2175 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2176 info->signals &= ~SerialSignal_RTS;
2177 info->drop_rts_on_tx_done = 0;
2178 set_signals(info);
2179 }
2180
2181 #if SYNCLINK_GENERIC_HDLC
2182 if (info->netcount)
2183 hdlcdev_tx_done(info);
2184 else
2185 #endif
2186 {
2187 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2188 tx_stop(info);
2189 return;
2190 }
2191 info->pending_bh |= BH_TRANSMIT;
2192 }
2193 }
2194 }
2195
2196 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2197 {
2198 struct cond_wait *w, *prev;
2199
2200 /* wake processes waiting for specific transitions */
2201 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2202 if (w->data & changed) {
2203 w->data = state;
2204 wake_up_interruptible(&w->q);
2205 if (prev != NULL)
2206 prev->next = w->next;
2207 else
2208 info->gpio_wait_q = w->next;
2209 } else
2210 prev = w;
2211 }
2212 }
2213
2214 /* interrupt service routine
2215 *
2216 * irq interrupt number
2217 * dev_id device ID supplied during interrupt registration
2218 */
2219 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2220 {
2221 struct slgt_info *info;
2222 unsigned int gsr;
2223 unsigned int i;
2224
2225 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2226
2227 info = dev_id;
2228 if (!info)
2229 return IRQ_NONE;
2230
2231 spin_lock(&info->lock);
2232
2233 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2234 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2235 info->irq_occurred = 1;
2236 for(i=0; i < info->port_count ; i++) {
2237 if (info->port_array[i] == NULL)
2238 continue;
2239 if (gsr & (BIT8 << i))
2240 isr_serial(info->port_array[i]);
2241 if (gsr & (BIT16 << (i*2)))
2242 isr_rdma(info->port_array[i]);
2243 if (gsr & (BIT17 << (i*2)))
2244 isr_tdma(info->port_array[i]);
2245 }
2246 }
2247
2248 if (info->gpio_present) {
2249 unsigned int state;
2250 unsigned int changed;
2251 while ((changed = rd_reg32(info, IOSR)) != 0) {
2252 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2253 /* read latched state of GPIO signals */
2254 state = rd_reg32(info, IOVR);
2255 /* clear pending GPIO interrupt bits */
2256 wr_reg32(info, IOSR, changed);
2257 for (i=0 ; i < info->port_count ; i++) {
2258 if (info->port_array[i] != NULL)
2259 isr_gpio(info->port_array[i], changed, state);
2260 }
2261 }
2262 }
2263
2264 for(i=0; i < info->port_count ; i++) {
2265 struct slgt_info *port = info->port_array[i];
2266
2267 if (port && (port->count || port->netcount) &&
2268 port->pending_bh && !port->bh_running &&
2269 !port->bh_requested) {
2270 DBGISR(("%s bh queued\n", port->device_name));
2271 schedule_work(&port->task);
2272 port->bh_requested = 1;
2273 }
2274 }
2275
2276 spin_unlock(&info->lock);
2277
2278 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2279 return IRQ_HANDLED;
2280 }
2281
2282 static int startup(struct slgt_info *info)
2283 {
2284 DBGINFO(("%s startup\n", info->device_name));
2285
2286 if (info->flags & ASYNC_INITIALIZED)
2287 return 0;
2288
2289 if (!info->tx_buf) {
2290 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2291 if (!info->tx_buf) {
2292 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2293 return -ENOMEM;
2294 }
2295 }
2296
2297 info->pending_bh = 0;
2298
2299 memset(&info->icount, 0, sizeof(info->icount));
2300
2301 /* program hardware for current parameters */
2302 change_params(info);
2303
2304 if (info->tty)
2305 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2306
2307 info->flags |= ASYNC_INITIALIZED;
2308
2309 return 0;
2310 }
2311
2312 /*
2313 * called by close() and hangup() to shutdown hardware
2314 */
2315 static void shutdown(struct slgt_info *info)
2316 {
2317 unsigned long flags;
2318
2319 if (!(info->flags & ASYNC_INITIALIZED))
2320 return;
2321
2322 DBGINFO(("%s shutdown\n", info->device_name));
2323
2324 /* clear status wait queue because status changes */
2325 /* can't happen after shutting down the hardware */
2326 wake_up_interruptible(&info->status_event_wait_q);
2327 wake_up_interruptible(&info->event_wait_q);
2328
2329 del_timer_sync(&info->tx_timer);
2330 del_timer_sync(&info->rx_timer);
2331
2332 kfree(info->tx_buf);
2333 info->tx_buf = NULL;
2334
2335 spin_lock_irqsave(&info->lock,flags);
2336
2337 tx_stop(info);
2338 rx_stop(info);
2339
2340 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2341
2342 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2343 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2344 set_signals(info);
2345 }
2346
2347 flush_cond_wait(&info->gpio_wait_q);
2348
2349 spin_unlock_irqrestore(&info->lock,flags);
2350
2351 if (info->tty)
2352 set_bit(TTY_IO_ERROR, &info->tty->flags);
2353
2354 info->flags &= ~ASYNC_INITIALIZED;
2355 }
2356
2357 static void program_hw(struct slgt_info *info)
2358 {
2359 unsigned long flags;
2360
2361 spin_lock_irqsave(&info->lock,flags);
2362
2363 rx_stop(info);
2364 tx_stop(info);
2365
2366 if (info->params.mode != MGSL_MODE_ASYNC ||
2367 info->netcount)
2368 sync_mode(info);
2369 else
2370 async_mode(info);
2371
2372 set_signals(info);
2373
2374 info->dcd_chkcount = 0;
2375 info->cts_chkcount = 0;
2376 info->ri_chkcount = 0;
2377 info->dsr_chkcount = 0;
2378
2379 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2380 get_signals(info);
2381
2382 if (info->netcount ||
2383 (info->tty && info->tty->termios->c_cflag & CREAD))
2384 rx_start(info);
2385
2386 spin_unlock_irqrestore(&info->lock,flags);
2387 }
2388
2389 /*
2390 * reconfigure adapter based on new parameters
2391 */
2392 static void change_params(struct slgt_info *info)
2393 {
2394 unsigned cflag;
2395 int bits_per_char;
2396
2397 if (!info->tty || !info->tty->termios)
2398 return;
2399 DBGINFO(("%s change_params\n", info->device_name));
2400
2401 cflag = info->tty->termios->c_cflag;
2402
2403 /* if B0 rate (hangup) specified then negate DTR and RTS */
2404 /* otherwise assert DTR and RTS */
2405 if (cflag & CBAUD)
2406 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2407 else
2408 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2409
2410 /* byte size and parity */
2411
2412 switch (cflag & CSIZE) {
2413 case CS5: info->params.data_bits = 5; break;
2414 case CS6: info->params.data_bits = 6; break;
2415 case CS7: info->params.data_bits = 7; break;
2416 case CS8: info->params.data_bits = 8; break;
2417 default: info->params.data_bits = 7; break;
2418 }
2419
2420 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2421
2422 if (cflag & PARENB)
2423 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2424 else
2425 info->params.parity = ASYNC_PARITY_NONE;
2426
2427 /* calculate number of jiffies to transmit a full
2428 * FIFO (32 bytes) at specified data rate
2429 */
2430 bits_per_char = info->params.data_bits +
2431 info->params.stop_bits + 1;
2432
2433 info->params.data_rate = tty_get_baud_rate(info->tty);
2434
2435 if (info->params.data_rate) {
2436 info->timeout = (32*HZ*bits_per_char) /
2437 info->params.data_rate;
2438 }
2439 info->timeout += HZ/50; /* Add .02 seconds of slop */
2440
2441 if (cflag & CRTSCTS)
2442 info->flags |= ASYNC_CTS_FLOW;
2443 else
2444 info->flags &= ~ASYNC_CTS_FLOW;
2445
2446 if (cflag & CLOCAL)
2447 info->flags &= ~ASYNC_CHECK_CD;
2448 else
2449 info->flags |= ASYNC_CHECK_CD;
2450
2451 /* process tty input control flags */
2452
2453 info->read_status_mask = IRQ_RXOVER;
2454 if (I_INPCK(info->tty))
2455 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2456 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2457 info->read_status_mask |= MASK_BREAK;
2458 if (I_IGNPAR(info->tty))
2459 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2460 if (I_IGNBRK(info->tty)) {
2461 info->ignore_status_mask |= MASK_BREAK;
2462 /* If ignoring parity and break indicators, ignore
2463 * overruns too. (For real raw support).
2464 */
2465 if (I_IGNPAR(info->tty))
2466 info->ignore_status_mask |= MASK_OVERRUN;
2467 }
2468
2469 program_hw(info);
2470 }
2471
2472 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2473 {
2474 DBGINFO(("%s get_stats\n", info->device_name));
2475 if (!user_icount) {
2476 memset(&info->icount, 0, sizeof(info->icount));
2477 } else {
2478 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2479 return -EFAULT;
2480 }
2481 return 0;
2482 }
2483
2484 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2485 {
2486 DBGINFO(("%s get_params\n", info->device_name));
2487 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2488 return -EFAULT;
2489 return 0;
2490 }
2491
2492 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2493 {
2494 unsigned long flags;
2495 MGSL_PARAMS tmp_params;
2496
2497 DBGINFO(("%s set_params\n", info->device_name));
2498 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2499 return -EFAULT;
2500
2501 spin_lock_irqsave(&info->lock, flags);
2502 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2503 spin_unlock_irqrestore(&info->lock, flags);
2504
2505 change_params(info);
2506
2507 return 0;
2508 }
2509
2510 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2511 {
2512 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2513 if (put_user(info->idle_mode, idle_mode))
2514 return -EFAULT;
2515 return 0;
2516 }
2517
2518 static int set_txidle(struct slgt_info *info, int idle_mode)
2519 {
2520 unsigned long flags;
2521 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2522 spin_lock_irqsave(&info->lock,flags);
2523 info->idle_mode = idle_mode;
2524 if (info->params.mode != MGSL_MODE_ASYNC)
2525 tx_set_idle(info);
2526 spin_unlock_irqrestore(&info->lock,flags);
2527 return 0;
2528 }
2529
2530 static int tx_enable(struct slgt_info *info, int enable)
2531 {
2532 unsigned long flags;
2533 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2534 spin_lock_irqsave(&info->lock,flags);
2535 if (enable) {
2536 if (!info->tx_enabled)
2537 tx_start(info);
2538 } else {
2539 if (info->tx_enabled)
2540 tx_stop(info);
2541 }
2542 spin_unlock_irqrestore(&info->lock,flags);
2543 return 0;
2544 }
2545
2546 /*
2547 * abort transmit HDLC frame
2548 */
2549 static int tx_abort(struct slgt_info *info)
2550 {
2551 unsigned long flags;
2552 DBGINFO(("%s tx_abort\n", info->device_name));
2553 spin_lock_irqsave(&info->lock,flags);
2554 tdma_reset(info);
2555 spin_unlock_irqrestore(&info->lock,flags);
2556 return 0;
2557 }
2558
2559 static int rx_enable(struct slgt_info *info, int enable)
2560 {
2561 unsigned long flags;
2562 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2563 spin_lock_irqsave(&info->lock,flags);
2564 if (enable) {
2565 if (!info->rx_enabled)
2566 rx_start(info);
2567 else if (enable == 2) {
2568 /* force hunt mode (write 1 to RCR[3]) */
2569 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2570 }
2571 } else {
2572 if (info->rx_enabled)
2573 rx_stop(info);
2574 }
2575 spin_unlock_irqrestore(&info->lock,flags);
2576 return 0;
2577 }
2578
2579 /*
2580 * wait for specified event to occur
2581 */
2582 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2583 {
2584 unsigned long flags;
2585 int s;
2586 int rc=0;
2587 struct mgsl_icount cprev, cnow;
2588 int events;
2589 int mask;
2590 struct _input_signal_events oldsigs, newsigs;
2591 DECLARE_WAITQUEUE(wait, current);
2592
2593 if (get_user(mask, mask_ptr))
2594 return -EFAULT;
2595
2596 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2597
2598 spin_lock_irqsave(&info->lock,flags);
2599
2600 /* return immediately if state matches requested events */
2601 get_signals(info);
2602 s = info->signals;
2603
2604 events = mask &
2605 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2606 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2607 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2608 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2609 if (events) {
2610 spin_unlock_irqrestore(&info->lock,flags);
2611 goto exit;
2612 }
2613
2614 /* save current irq counts */
2615 cprev = info->icount;
2616 oldsigs = info->input_signal_events;
2617
2618 /* enable hunt and idle irqs if needed */
2619 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2620 unsigned short val = rd_reg16(info, SCR);
2621 if (!(val & IRQ_RXIDLE))
2622 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2623 }
2624
2625 set_current_state(TASK_INTERRUPTIBLE);
2626 add_wait_queue(&info->event_wait_q, &wait);
2627
2628 spin_unlock_irqrestore(&info->lock,flags);
2629
2630 for(;;) {
2631 schedule();
2632 if (signal_pending(current)) {
2633 rc = -ERESTARTSYS;
2634 break;
2635 }
2636
2637 /* get current irq counts */
2638 spin_lock_irqsave(&info->lock,flags);
2639 cnow = info->icount;
2640 newsigs = info->input_signal_events;
2641 set_current_state(TASK_INTERRUPTIBLE);
2642 spin_unlock_irqrestore(&info->lock,flags);
2643
2644 /* if no change, wait aborted for some reason */
2645 if (newsigs.dsr_up == oldsigs.dsr_up &&
2646 newsigs.dsr_down == oldsigs.dsr_down &&
2647 newsigs.dcd_up == oldsigs.dcd_up &&
2648 newsigs.dcd_down == oldsigs.dcd_down &&
2649 newsigs.cts_up == oldsigs.cts_up &&
2650 newsigs.cts_down == oldsigs.cts_down &&
2651 newsigs.ri_up == oldsigs.ri_up &&
2652 newsigs.ri_down == oldsigs.ri_down &&
2653 cnow.exithunt == cprev.exithunt &&
2654 cnow.rxidle == cprev.rxidle) {
2655 rc = -EIO;
2656 break;
2657 }
2658
2659 events = mask &
2660 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2661 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2662 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2663 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2664 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2665 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2666 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2667 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2668 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2669 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2670 if (events)
2671 break;
2672
2673 cprev = cnow;
2674 oldsigs = newsigs;
2675 }
2676
2677 remove_wait_queue(&info->event_wait_q, &wait);
2678 set_current_state(TASK_RUNNING);
2679
2680
2681 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2682 spin_lock_irqsave(&info->lock,flags);
2683 if (!waitqueue_active(&info->event_wait_q)) {
2684 /* disable enable exit hunt mode/idle rcvd IRQs */
2685 wr_reg16(info, SCR,
2686 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2687 }
2688 spin_unlock_irqrestore(&info->lock,flags);
2689 }
2690 exit:
2691 if (rc == 0)
2692 rc = put_user(events, mask_ptr);
2693 return rc;
2694 }
2695
2696 static int get_interface(struct slgt_info *info, int __user *if_mode)
2697 {
2698 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2699 if (put_user(info->if_mode, if_mode))
2700 return -EFAULT;
2701 return 0;
2702 }
2703
2704 static int set_interface(struct slgt_info *info, int if_mode)
2705 {
2706 unsigned long flags;
2707 unsigned short val;
2708
2709 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2710 spin_lock_irqsave(&info->lock,flags);
2711 info->if_mode = if_mode;
2712
2713 msc_set_vcr(info);
2714
2715 /* TCR (tx control) 07 1=RTS driver control */
2716 val = rd_reg16(info, TCR);
2717 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2718 val |= BIT7;
2719 else
2720 val &= ~BIT7;
2721 wr_reg16(info, TCR, val);
2722
2723 spin_unlock_irqrestore(&info->lock,flags);
2724 return 0;
2725 }
2726
2727 /*
2728 * set general purpose IO pin state and direction
2729 *
2730 * user_gpio fields:
2731 * state each bit indicates a pin state
2732 * smask set bit indicates pin state to set
2733 * dir each bit indicates a pin direction (0=input, 1=output)
2734 * dmask set bit indicates pin direction to set
2735 */
2736 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2737 {
2738 unsigned long flags;
2739 struct gpio_desc gpio;
2740 __u32 data;
2741
2742 if (!info->gpio_present)
2743 return -EINVAL;
2744 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2745 return -EFAULT;
2746 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2747 info->device_name, gpio.state, gpio.smask,
2748 gpio.dir, gpio.dmask));
2749
2750 spin_lock_irqsave(&info->lock,flags);
2751 if (gpio.dmask) {
2752 data = rd_reg32(info, IODR);
2753 data |= gpio.dmask & gpio.dir;
2754 data &= ~(gpio.dmask & ~gpio.dir);
2755 wr_reg32(info, IODR, data);
2756 }
2757 if (gpio.smask) {
2758 data = rd_reg32(info, IOVR);
2759 data |= gpio.smask & gpio.state;
2760 data &= ~(gpio.smask & ~gpio.state);
2761 wr_reg32(info, IOVR, data);
2762 }
2763 spin_unlock_irqrestore(&info->lock,flags);
2764
2765 return 0;
2766 }
2767
2768 /*
2769 * get general purpose IO pin state and direction
2770 */
2771 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2772 {
2773 struct gpio_desc gpio;
2774 if (!info->gpio_present)
2775 return -EINVAL;
2776 gpio.state = rd_reg32(info, IOVR);
2777 gpio.smask = 0xffffffff;
2778 gpio.dir = rd_reg32(info, IODR);
2779 gpio.dmask = 0xffffffff;
2780 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2781 return -EFAULT;
2782 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2783 info->device_name, gpio.state, gpio.dir));
2784 return 0;
2785 }
2786
2787 /*
2788 * conditional wait facility
2789 */
2790 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2791 {
2792 init_waitqueue_head(&w->q);
2793 init_waitqueue_entry(&w->wait, current);
2794 w->data = data;
2795 }
2796
2797 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2798 {
2799 set_current_state(TASK_INTERRUPTIBLE);
2800 add_wait_queue(&w->q, &w->wait);
2801 w->next = *head;
2802 *head = w;
2803 }
2804
2805 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2806 {
2807 struct cond_wait *w, *prev;
2808 remove_wait_queue(&cw->q, &cw->wait);
2809 set_current_state(TASK_RUNNING);
2810 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2811 if (w == cw) {
2812 if (prev != NULL)
2813 prev->next = w->next;
2814 else
2815 *head = w->next;
2816 break;
2817 }
2818 }
2819 }
2820
2821 static void flush_cond_wait(struct cond_wait **head)
2822 {
2823 while (*head != NULL) {
2824 wake_up_interruptible(&(*head)->q);
2825 *head = (*head)->next;
2826 }
2827 }
2828
2829 /*
2830 * wait for general purpose I/O pin(s) to enter specified state
2831 *
2832 * user_gpio fields:
2833 * state - bit indicates target pin state
2834 * smask - set bit indicates watched pin
2835 *
2836 * The wait ends when at least one watched pin enters the specified
2837 * state. When 0 (no error) is returned, user_gpio->state is set to the
2838 * state of all GPIO pins when the wait ends.
2839 *
2840 * Note: Each pin may be a dedicated input, dedicated output, or
2841 * configurable input/output. The number and configuration of pins
2842 * varies with the specific adapter model. Only input pins (dedicated
2843 * or configured) can be monitored with this function.
2844 */
2845 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2846 {
2847 unsigned long flags;
2848 int rc = 0;
2849 struct gpio_desc gpio;
2850 struct cond_wait wait;
2851 u32 state;
2852
2853 if (!info->gpio_present)
2854 return -EINVAL;
2855 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2856 return -EFAULT;
2857 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2858 info->device_name, gpio.state, gpio.smask));
2859 /* ignore output pins identified by set IODR bit */
2860 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2861 return -EINVAL;
2862 init_cond_wait(&wait, gpio.smask);
2863
2864 spin_lock_irqsave(&info->lock, flags);
2865 /* enable interrupts for watched pins */
2866 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2867 /* get current pin states */
2868 state = rd_reg32(info, IOVR);
2869
2870 if (gpio.smask & ~(state ^ gpio.state)) {
2871 /* already in target state */
2872 gpio.state = state;
2873 } else {
2874 /* wait for target state */
2875 add_cond_wait(&info->gpio_wait_q, &wait);
2876 spin_unlock_irqrestore(&info->lock, flags);
2877 schedule();
2878 if (signal_pending(current))
2879 rc = -ERESTARTSYS;
2880 else
2881 gpio.state = wait.data;
2882 spin_lock_irqsave(&info->lock, flags);
2883 remove_cond_wait(&info->gpio_wait_q, &wait);
2884 }
2885
2886 /* disable all GPIO interrupts if no waiting processes */
2887 if (info->gpio_wait_q == NULL)
2888 wr_reg32(info, IOER, 0);
2889 spin_unlock_irqrestore(&info->lock,flags);
2890
2891 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2892 rc = -EFAULT;
2893 return rc;
2894 }
2895
2896 static int modem_input_wait(struct slgt_info *info,int arg)
2897 {
2898 unsigned long flags;
2899 int rc;
2900 struct mgsl_icount cprev, cnow;
2901 DECLARE_WAITQUEUE(wait, current);
2902
2903 /* save current irq counts */
2904 spin_lock_irqsave(&info->lock,flags);
2905 cprev = info->icount;
2906 add_wait_queue(&info->status_event_wait_q, &wait);
2907 set_current_state(TASK_INTERRUPTIBLE);
2908 spin_unlock_irqrestore(&info->lock,flags);
2909
2910 for(;;) {
2911 schedule();
2912 if (signal_pending(current)) {
2913 rc = -ERESTARTSYS;
2914 break;
2915 }
2916
2917 /* get new irq counts */
2918 spin_lock_irqsave(&info->lock,flags);
2919 cnow = info->icount;
2920 set_current_state(TASK_INTERRUPTIBLE);
2921 spin_unlock_irqrestore(&info->lock,flags);
2922
2923 /* if no change, wait aborted for some reason */
2924 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2925 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2926 rc = -EIO;
2927 break;
2928 }
2929
2930 /* check for change in caller specified modem input */
2931 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2932 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2933 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2934 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2935 rc = 0;
2936 break;
2937 }
2938
2939 cprev = cnow;
2940 }
2941 remove_wait_queue(&info->status_event_wait_q, &wait);
2942 set_current_state(TASK_RUNNING);
2943 return rc;
2944 }
2945
2946 /*
2947 * return state of serial control and status signals
2948 */
2949 static int tiocmget(struct tty_struct *tty, struct file *file)
2950 {
2951 struct slgt_info *info = tty->driver_data;
2952 unsigned int result;
2953 unsigned long flags;
2954
2955 spin_lock_irqsave(&info->lock,flags);
2956 get_signals(info);
2957 spin_unlock_irqrestore(&info->lock,flags);
2958
2959 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2960 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2961 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2962 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2963 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2964 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2965
2966 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2967 return result;
2968 }
2969
2970 /*
2971 * set modem control signals (DTR/RTS)
2972 *
2973 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2974 * TIOCMSET = set/clear signal values
2975 * value bit mask for command
2976 */
2977 static int tiocmset(struct tty_struct *tty, struct file *file,
2978 unsigned int set, unsigned int clear)
2979 {
2980 struct slgt_info *info = tty->driver_data;
2981 unsigned long flags;
2982
2983 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2984
2985 if (set & TIOCM_RTS)
2986 info->signals |= SerialSignal_RTS;
2987 if (set & TIOCM_DTR)
2988 info->signals |= SerialSignal_DTR;
2989 if (clear & TIOCM_RTS)
2990 info->signals &= ~SerialSignal_RTS;
2991 if (clear & TIOCM_DTR)
2992 info->signals &= ~SerialSignal_DTR;
2993
2994 spin_lock_irqsave(&info->lock,flags);
2995 set_signals(info);
2996 spin_unlock_irqrestore(&info->lock,flags);
2997 return 0;
2998 }
2999
3000 /*
3001 * block current process until the device is ready to open
3002 */
3003 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3004 struct slgt_info *info)
3005 {
3006 DECLARE_WAITQUEUE(wait, current);
3007 int retval;
3008 int do_clocal = 0, extra_count = 0;
3009 unsigned long flags;
3010
3011 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3012
3013 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3014 /* nonblock mode is set or port is not enabled */
3015 info->flags |= ASYNC_NORMAL_ACTIVE;
3016 return 0;
3017 }
3018
3019 if (tty->termios->c_cflag & CLOCAL)
3020 do_clocal = 1;
3021
3022 /* Wait for carrier detect and the line to become
3023 * free (i.e., not in use by the callout). While we are in
3024 * this loop, info->count is dropped by one, so that
3025 * close() knows when to free things. We restore it upon
3026 * exit, either normal or abnormal.
3027 */
3028
3029 retval = 0;
3030 add_wait_queue(&info->open_wait, &wait);
3031
3032 spin_lock_irqsave(&info->lock, flags);
3033 if (!tty_hung_up_p(filp)) {
3034 extra_count = 1;
3035 info->count--;
3036 }
3037 spin_unlock_irqrestore(&info->lock, flags);
3038 info->blocked_open++;
3039
3040 while (1) {
3041 if ((tty->termios->c_cflag & CBAUD)) {
3042 spin_lock_irqsave(&info->lock,flags);
3043 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3044 set_signals(info);
3045 spin_unlock_irqrestore(&info->lock,flags);
3046 }
3047
3048 set_current_state(TASK_INTERRUPTIBLE);
3049
3050 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3051 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3052 -EAGAIN : -ERESTARTSYS;
3053 break;
3054 }
3055
3056 spin_lock_irqsave(&info->lock,flags);
3057 get_signals(info);
3058 spin_unlock_irqrestore(&info->lock,flags);
3059
3060 if (!(info->flags & ASYNC_CLOSING) &&
3061 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3062 break;
3063 }
3064
3065 if (signal_pending(current)) {
3066 retval = -ERESTARTSYS;
3067 break;
3068 }
3069
3070 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3071 schedule();
3072 }
3073
3074 set_current_state(TASK_RUNNING);
3075 remove_wait_queue(&info->open_wait, &wait);
3076
3077 if (extra_count)
3078 info->count++;
3079 info->blocked_open--;
3080
3081 if (!retval)
3082 info->flags |= ASYNC_NORMAL_ACTIVE;
3083
3084 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3085 return retval;
3086 }
3087
3088 static int alloc_tmp_rbuf(struct slgt_info *info)
3089 {
3090 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3091 if (info->tmp_rbuf == NULL)
3092 return -ENOMEM;
3093 return 0;
3094 }
3095
3096 static void free_tmp_rbuf(struct slgt_info *info)
3097 {
3098 kfree(info->tmp_rbuf);
3099 info->tmp_rbuf = NULL;
3100 }
3101
3102 /*
3103 * allocate DMA descriptor lists.
3104 */
3105 static int alloc_desc(struct slgt_info *info)
3106 {
3107 unsigned int i;
3108 unsigned int pbufs;
3109
3110 /* allocate memory to hold descriptor lists */
3111 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3112 if (info->bufs == NULL)
3113 return -ENOMEM;
3114
3115 memset(info->bufs, 0, DESC_LIST_SIZE);
3116
3117 info->rbufs = (struct slgt_desc*)info->bufs;
3118 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3119
3120 pbufs = (unsigned int)info->bufs_dma_addr;
3121
3122 /*
3123 * Build circular lists of descriptors
3124 */
3125
3126 for (i=0; i < info->rbuf_count; i++) {
3127 /* physical address of this descriptor */
3128 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3129
3130 /* physical address of next descriptor */
3131 if (i == info->rbuf_count - 1)
3132 info->rbufs[i].next = cpu_to_le32(pbufs);
3133 else
3134 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3135 set_desc_count(info->rbufs[i], DMABUFSIZE);
3136 }
3137
3138 for (i=0; i < info->tbuf_count; i++) {
3139 /* physical address of this descriptor */
3140 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3141
3142 /* physical address of next descriptor */
3143 if (i == info->tbuf_count - 1)
3144 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3145 else
3146 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3147 }
3148
3149 return 0;
3150 }
3151
3152 static void free_desc(struct slgt_info *info)
3153 {
3154 if (info->bufs != NULL) {
3155 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3156 info->bufs = NULL;
3157 info->rbufs = NULL;
3158 info->tbufs = NULL;
3159 }
3160 }
3161
3162 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3163 {
3164 int i;
3165 for (i=0; i < count; i++) {
3166 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3167 return -ENOMEM;
3168 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3169 }
3170 return 0;
3171 }
3172
3173 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3174 {
3175 int i;
3176 for (i=0; i < count; i++) {
3177 if (bufs[i].buf == NULL)
3178 continue;
3179 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3180 bufs[i].buf = NULL;
3181 }
3182 }
3183
3184 static int alloc_dma_bufs(struct slgt_info *info)
3185 {
3186 info->rbuf_count = 32;
3187 info->tbuf_count = 32;
3188
3189 if (alloc_desc(info) < 0 ||
3190 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3191 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3192 alloc_tmp_rbuf(info) < 0) {
3193 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3194 return -ENOMEM;
3195 }
3196 reset_rbufs(info);
3197 return 0;
3198 }
3199
3200 static void free_dma_bufs(struct slgt_info *info)
3201 {
3202 if (info->bufs) {
3203 free_bufs(info, info->rbufs, info->rbuf_count);
3204 free_bufs(info, info->tbufs, info->tbuf_count);
3205 free_desc(info);
3206 }
3207 free_tmp_rbuf(info);
3208 }
3209
3210 static int claim_resources(struct slgt_info *info)
3211 {
3212 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3213 DBGERR(("%s reg addr conflict, addr=%08X\n",
3214 info->device_name, info->phys_reg_addr));
3215 info->init_error = DiagStatus_AddressConflict;
3216 goto errout;
3217 }
3218 else
3219 info->reg_addr_requested = 1;
3220
3221 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3222 if (!info->reg_addr) {
3223 DBGERR(("%s cant map device registers, addr=%08X\n",
3224 info->device_name, info->phys_reg_addr));
3225 info->init_error = DiagStatus_CantAssignPciResources;
3226 goto errout;
3227 }
3228 return 0;
3229
3230 errout:
3231 release_resources(info);
3232 return -ENODEV;
3233 }
3234
3235 static void release_resources(struct slgt_info *info)
3236 {
3237 if (info->irq_requested) {
3238 free_irq(info->irq_level, info);
3239 info->irq_requested = 0;
3240 }
3241
3242 if (info->reg_addr_requested) {
3243 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3244 info->reg_addr_requested = 0;
3245 }
3246
3247 if (info->reg_addr) {
3248 iounmap(info->reg_addr);
3249 info->reg_addr = NULL;
3250 }
3251 }
3252
3253 /* Add the specified device instance data structure to the
3254 * global linked list of devices and increment the device count.
3255 */
3256 static void add_device(struct slgt_info *info)
3257 {
3258 char *devstr;
3259
3260 info->next_device = NULL;
3261 info->line = slgt_device_count;
3262 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3263
3264 if (info->line < MAX_DEVICES) {
3265 if (maxframe[info->line])
3266 info->max_frame_size = maxframe[info->line];
3267 info->dosyncppp = dosyncppp[info->line];
3268 }
3269
3270 slgt_device_count++;
3271
3272 if (!slgt_device_list)
3273 slgt_device_list = info;
3274 else {
3275 struct slgt_info *current_dev = slgt_device_list;
3276 while(current_dev->next_device)
3277 current_dev = current_dev->next_device;
3278 current_dev->next_device = info;
3279 }
3280
3281 if (info->max_frame_size < 4096)
3282 info->max_frame_size = 4096;
3283 else if (info->max_frame_size > 65535)
3284 info->max_frame_size = 65535;
3285
3286 switch(info->pdev->device) {
3287 case SYNCLINK_GT_DEVICE_ID:
3288 devstr = "GT";
3289 break;
3290 case SYNCLINK_GT2_DEVICE_ID:
3291 devstr = "GT2";
3292 break;
3293 case SYNCLINK_GT4_DEVICE_ID:
3294 devstr = "GT4";
3295 break;
3296 case SYNCLINK_AC_DEVICE_ID:
3297 devstr = "AC";
3298 info->params.mode = MGSL_MODE_ASYNC;
3299 break;
3300 default:
3301 devstr = "(unknown model)";
3302 }
3303 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3304 devstr, info->device_name, info->phys_reg_addr,
3305 info->irq_level, info->max_frame_size);
3306
3307 #if SYNCLINK_GENERIC_HDLC
3308 hdlcdev_init(info);
3309 #endif
3310 }
3311
3312 /*
3313 * allocate device instance structure, return NULL on failure
3314 */
3315 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3316 {
3317 struct slgt_info *info;
3318
3319 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3320
3321 if (!info) {
3322 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3323 driver_name, adapter_num, port_num));
3324 } else {
3325 memset(info, 0, sizeof(struct slgt_info));
3326 info->magic = MGSL_MAGIC;
3327 INIT_WORK(&info->task, bh_handler);
3328 info->max_frame_size = 4096;
3329 info->raw_rx_size = DMABUFSIZE;
3330 info->close_delay = 5*HZ/10;
3331 info->closing_wait = 30*HZ;
3332 init_waitqueue_head(&info->open_wait);
3333 init_waitqueue_head(&info->close_wait);
3334 init_waitqueue_head(&info->status_event_wait_q);
3335 init_waitqueue_head(&info->event_wait_q);
3336 spin_lock_init(&info->netlock);
3337 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3338 info->idle_mode = HDLC_TXIDLE_FLAGS;
3339 info->adapter_num = adapter_num;
3340 info->port_num = port_num;
3341
3342 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3343 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3344
3345 /* Copy configuration info to device instance data */
3346 info->pdev = pdev;
3347 info->irq_level = pdev->irq;
3348 info->phys_reg_addr = pci_resource_start(pdev,0);
3349
3350 info->bus_type = MGSL_BUS_TYPE_PCI;
3351 info->irq_flags = IRQF_SHARED;
3352
3353 info->init_error = -1; /* assume error, set to 0 on successful init */
3354 }
3355
3356 return info;
3357 }
3358
3359 static void device_init(int adapter_num, struct pci_dev *pdev)
3360 {
3361 struct slgt_info *port_array[SLGT_MAX_PORTS];
3362 int i;
3363 int port_count = 1;
3364
3365 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3366 port_count = 2;
3367 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3368 port_count = 4;
3369
3370 /* allocate device instances for all ports */
3371 for (i=0; i < port_count; ++i) {
3372 port_array[i] = alloc_dev(adapter_num, i, pdev);
3373 if (port_array[i] == NULL) {
3374 for (--i; i >= 0; --i)
3375 kfree(port_array[i]);
3376 return;
3377 }
3378 }
3379
3380 /* give copy of port_array to all ports and add to device list */
3381 for (i=0; i < port_count; ++i) {
3382 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3383 add_device(port_array[i]);
3384 port_array[i]->port_count = port_count;
3385 spin_lock_init(&port_array[i]->lock);
3386 }
3387
3388 /* Allocate and claim adapter resources */
3389 if (!claim_resources(port_array[0])) {
3390
3391 alloc_dma_bufs(port_array[0]);
3392
3393 /* copy resource information from first port to others */
3394 for (i = 1; i < port_count; ++i) {
3395 port_array[i]->lock = port_array[0]->lock;
3396 port_array[i]->irq_level = port_array[0]->irq_level;
3397 port_array[i]->reg_addr = port_array[0]->reg_addr;
3398 alloc_dma_bufs(port_array[i]);
3399 }
3400
3401 if (request_irq(port_array[0]->irq_level,
3402 slgt_interrupt,
3403 port_array[0]->irq_flags,
3404 port_array[0]->device_name,
3405 port_array[0]) < 0) {
3406 DBGERR(("%s request_irq failed IRQ=%d\n",
3407 port_array[0]->device_name,
3408 port_array[0]->irq_level));
3409 } else {
3410 port_array[0]->irq_requested = 1;
3411 adapter_test(port_array[0]);
3412 for (i=1 ; i < port_count ; i++) {
3413 port_array[i]->init_error = port_array[0]->init_error;
3414 port_array[i]->gpio_present = port_array[0]->gpio_present;
3415 }
3416 }
3417 }
3418 }
3419
3420 static int __devinit init_one(struct pci_dev *dev,
3421 const struct pci_device_id *ent)
3422 {
3423 if (pci_enable_device(dev)) {
3424 printk("error enabling pci device %p\n", dev);
3425 return -EIO;
3426 }
3427 pci_set_master(dev);
3428 device_init(slgt_device_count, dev);
3429 return 0;
3430 }
3431
3432 static void __devexit remove_one(struct pci_dev *dev)
3433 {
3434 }
3435
3436 static const struct tty_operations ops = {
3437 .open = open,
3438 .close = close,
3439 .write = write,
3440 .put_char = put_char,
3441 .flush_chars = flush_chars,
3442 .write_room = write_room,
3443 .chars_in_buffer = chars_in_buffer,
3444 .flush_buffer = flush_buffer,
3445 .ioctl = ioctl,
3446 .throttle = throttle,
3447 .unthrottle = unthrottle,
3448 .send_xchar = send_xchar,
3449 .break_ctl = set_break,
3450 .wait_until_sent = wait_until_sent,
3451 .read_proc = read_proc,
3452 .set_termios = set_termios,
3453 .stop = tx_hold,
3454 .start = tx_release,
3455 .hangup = hangup,
3456 .tiocmget = tiocmget,
3457 .tiocmset = tiocmset,
3458 };
3459
3460 static void slgt_cleanup(void)
3461 {
3462 int rc;
3463 struct slgt_info *info;
3464 struct slgt_info *tmp;
3465
3466 printk("unload %s %s\n", driver_name, driver_version);
3467
3468 if (serial_driver) {
3469 if ((rc = tty_unregister_driver(serial_driver)))
3470 DBGERR(("tty_unregister_driver error=%d\n", rc));
3471 put_tty_driver(serial_driver);
3472 }
3473
3474 /* reset devices */
3475 info = slgt_device_list;
3476 while(info) {
3477 reset_port(info);
3478 info = info->next_device;
3479 }
3480
3481 /* release devices */
3482 info = slgt_device_list;
3483 while(info) {
3484 #if SYNCLINK_GENERIC_HDLC
3485 hdlcdev_exit(info);
3486 #endif
3487 free_dma_bufs(info);
3488 free_tmp_rbuf(info);
3489 if (info->port_num == 0)
3490 release_resources(info);
3491 tmp = info;
3492 info = info->next_device;
3493 kfree(tmp);
3494 }
3495
3496 if (pci_registered)
3497 pci_unregister_driver(&pci_driver);
3498 }
3499
3500 /*
3501 * Driver initialization entry point.
3502 */
3503 static int __init slgt_init(void)
3504 {
3505 int rc;
3506
3507 printk("%s %s\n", driver_name, driver_version);
3508
3509 slgt_device_count = 0;
3510 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3511 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3512 return rc;
3513 }
3514 pci_registered = 1;
3515
3516 if (!slgt_device_list) {
3517 printk("%s no devices found\n",driver_name);
3518 pci_unregister_driver(&pci_driver);
3519 return -ENODEV;
3520 }
3521
3522 serial_driver = alloc_tty_driver(MAX_DEVICES);
3523 if (!serial_driver) {
3524 rc = -ENOMEM;
3525 goto error;
3526 }
3527
3528 /* Initialize the tty_driver structure */
3529
3530 serial_driver->owner = THIS_MODULE;
3531 serial_driver->driver_name = tty_driver_name;
3532 serial_driver->name = tty_dev_prefix;
3533 serial_driver->major = ttymajor;
3534 serial_driver->minor_start = 64;
3535 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3536 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3537 serial_driver->init_termios = tty_std_termios;
3538 serial_driver->init_termios.c_cflag =
3539 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3540 serial_driver->init_termios.c_ispeed = 9600;
3541 serial_driver->init_termios.c_ospeed = 9600;
3542 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3543 tty_set_operations(serial_driver, &ops);
3544 if ((rc = tty_register_driver(serial_driver)) < 0) {
3545 DBGERR(("%s can't register serial driver\n", driver_name));
3546 put_tty_driver(serial_driver);
3547 serial_driver = NULL;
3548 goto error;
3549 }
3550
3551 printk("%s %s, tty major#%d\n",
3552 driver_name, driver_version,
3553 serial_driver->major);
3554
3555 return 0;
3556
3557 error:
3558 slgt_cleanup();
3559 return rc;
3560 }
3561
3562 static void __exit slgt_exit(void)
3563 {
3564 slgt_cleanup();
3565 }
3566
3567 module_init(slgt_init);
3568 module_exit(slgt_exit);
3569
3570 /*
3571 * register access routines
3572 */
3573
3574 #define CALC_REGADDR() \
3575 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3576 if (addr >= 0x80) \
3577 reg_addr += (info->port_num) * 32;
3578
3579 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3580 {
3581 CALC_REGADDR();
3582 return readb((void __iomem *)reg_addr);
3583 }
3584
3585 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3586 {
3587 CALC_REGADDR();
3588 writeb(value, (void __iomem *)reg_addr);
3589 }
3590
3591 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3592 {
3593 CALC_REGADDR();
3594 return readw((void __iomem *)reg_addr);
3595 }
3596
3597 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3598 {
3599 CALC_REGADDR();
3600 writew(value, (void __iomem *)reg_addr);
3601 }
3602
3603 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3604 {
3605 CALC_REGADDR();
3606 return readl((void __iomem *)reg_addr);
3607 }
3608
3609 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3610 {
3611 CALC_REGADDR();
3612 writel(value, (void __iomem *)reg_addr);
3613 }
3614
3615 static void rdma_reset(struct slgt_info *info)
3616 {
3617 unsigned int i;
3618
3619 /* set reset bit */
3620 wr_reg32(info, RDCSR, BIT1);
3621
3622 /* wait for enable bit cleared */
3623 for(i=0 ; i < 1000 ; i++)
3624 if (!(rd_reg32(info, RDCSR) & BIT0))
3625 break;
3626 }
3627
3628 static void tdma_reset(struct slgt_info *info)
3629 {
3630 unsigned int i;
3631
3632 /* set reset bit */
3633 wr_reg32(info, TDCSR, BIT1);
3634
3635 /* wait for enable bit cleared */
3636 for(i=0 ; i < 1000 ; i++)
3637 if (!(rd_reg32(info, TDCSR) & BIT0))
3638 break;
3639 }
3640
3641 /*
3642 * enable internal loopback
3643 * TxCLK and RxCLK are generated from BRG
3644 * and TxD is looped back to RxD internally.
3645 */
3646 static void enable_loopback(struct slgt_info *info)
3647 {
3648 /* SCR (serial control) BIT2=looopback enable */
3649 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3650
3651 if (info->params.mode != MGSL_MODE_ASYNC) {
3652 /* CCR (clock control)
3653 * 07..05 tx clock source (010 = BRG)
3654 * 04..02 rx clock source (010 = BRG)
3655 * 01 auxclk enable (0 = disable)
3656 * 00 BRG enable (1 = enable)
3657 *
3658 * 0100 1001
3659 */
3660 wr_reg8(info, CCR, 0x49);
3661
3662 /* set speed if available, otherwise use default */
3663 if (info->params.clock_speed)
3664 set_rate(info, info->params.clock_speed);
3665 else
3666 set_rate(info, 3686400);
3667 }
3668 }
3669
3670 /*
3671 * set baud rate generator to specified rate
3672 */
3673 static void set_rate(struct slgt_info *info, u32 rate)
3674 {
3675 unsigned int div;
3676 static unsigned int osc = 14745600;
3677
3678 /* div = osc/rate - 1
3679 *
3680 * Round div up if osc/rate is not integer to
3681 * force to next slowest rate.
3682 */
3683
3684 if (rate) {
3685 div = osc/rate;
3686 if (!(osc % rate) && div)
3687 div--;
3688 wr_reg16(info, BDR, (unsigned short)div);
3689 }
3690 }
3691
3692 static void rx_stop(struct slgt_info *info)
3693 {
3694 unsigned short val;
3695
3696 /* disable and reset receiver */
3697 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3698 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3699 wr_reg16(info, RCR, val); /* clear reset bit */
3700
3701 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3702
3703 /* clear pending rx interrupts */
3704 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3705
3706 rdma_reset(info);
3707
3708 info->rx_enabled = 0;
3709 info->rx_restart = 0;
3710 }
3711
3712 static void rx_start(struct slgt_info *info)
3713 {
3714 unsigned short val;
3715
3716 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3717
3718 /* clear pending rx overrun IRQ */
3719 wr_reg16(info, SSR, IRQ_RXOVER);
3720
3721 /* reset and disable receiver */
3722 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3723 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3724 wr_reg16(info, RCR, val); /* clear reset bit */
3725
3726 rdma_reset(info);
3727 reset_rbufs(info);
3728
3729 /* set 1st descriptor address */
3730 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3731
3732 if (info->params.mode != MGSL_MODE_ASYNC) {
3733 /* enable rx DMA and DMA interrupt */
3734 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3735 } else {
3736 /* enable saving of rx status, rx DMA and DMA interrupt */
3737 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3738 }
3739
3740 slgt_irq_on(info, IRQ_RXOVER);
3741
3742 /* enable receiver */
3743 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3744
3745 info->rx_restart = 0;
3746 info->rx_enabled = 1;
3747 }
3748
3749 static void tx_start(struct slgt_info *info)
3750 {
3751 if (!info->tx_enabled) {
3752 wr_reg16(info, TCR,
3753 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3754 info->tx_enabled = TRUE;
3755 }
3756
3757 if (info->tx_count) {
3758 info->drop_rts_on_tx_done = 0;
3759
3760 if (info->params.mode != MGSL_MODE_ASYNC) {
3761 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3762 get_signals(info);
3763 if (!(info->signals & SerialSignal_RTS)) {
3764 info->signals |= SerialSignal_RTS;
3765 set_signals(info);
3766 info->drop_rts_on_tx_done = 1;
3767 }
3768 }
3769
3770 slgt_irq_off(info, IRQ_TXDATA);
3771 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3772 /* clear tx idle and underrun status bits */
3773 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3774
3775 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3776 /* tx DMA stopped, restart tx DMA */
3777 tdma_reset(info);
3778 /* set 1st descriptor address */
3779 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3780 switch(info->params.mode) {
3781 case MGSL_MODE_RAW:
3782 case MGSL_MODE_MONOSYNC:
3783 case MGSL_MODE_BISYNC:
3784 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3785 break;
3786 default:
3787 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3788 }
3789 }
3790
3791 if (info->params.mode == MGSL_MODE_HDLC)
3792 mod_timer(&info->tx_timer, jiffies +
3793 msecs_to_jiffies(5000));
3794 } else {
3795 tdma_reset(info);
3796 /* set 1st descriptor address */
3797 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3798
3799 slgt_irq_off(info, IRQ_TXDATA);
3800 slgt_irq_on(info, IRQ_TXIDLE);
3801 /* clear tx idle status bit */
3802 wr_reg16(info, SSR, IRQ_TXIDLE);
3803
3804 /* enable tx DMA */
3805 wr_reg32(info, TDCSR, BIT0);
3806 }
3807
3808 info->tx_active = 1;
3809 }
3810 }
3811
3812 static void tx_stop(struct slgt_info *info)
3813 {
3814 unsigned short val;
3815
3816 del_timer(&info->tx_timer);
3817
3818 tdma_reset(info);
3819
3820 /* reset and disable transmitter */
3821 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3822 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3823
3824 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3825
3826 /* clear tx idle and underrun status bit */
3827 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3828
3829 reset_tbufs(info);
3830
3831 info->tx_enabled = 0;
3832 info->tx_active = 0;
3833 }
3834
3835 static void reset_port(struct slgt_info *info)
3836 {
3837 if (!info->reg_addr)
3838 return;
3839
3840 tx_stop(info);
3841 rx_stop(info);
3842
3843 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3844 set_signals(info);
3845
3846 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3847 }
3848
3849 static void reset_adapter(struct slgt_info *info)
3850 {
3851 int i;
3852 for (i=0; i < info->port_count; ++i) {
3853 if (info->port_array[i])
3854 reset_port(info->port_array[i]);
3855 }
3856 }
3857
3858 static void async_mode(struct slgt_info *info)
3859 {
3860 unsigned short val;
3861
3862 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3863 tx_stop(info);
3864 rx_stop(info);
3865
3866 /* TCR (tx control)
3867 *
3868 * 15..13 mode, 010=async
3869 * 12..10 encoding, 000=NRZ
3870 * 09 parity enable
3871 * 08 1=odd parity, 0=even parity
3872 * 07 1=RTS driver control
3873 * 06 1=break enable
3874 * 05..04 character length
3875 * 00=5 bits
3876 * 01=6 bits
3877 * 10=7 bits
3878 * 11=8 bits
3879 * 03 0=1 stop bit, 1=2 stop bits
3880 * 02 reset
3881 * 01 enable
3882 * 00 auto-CTS enable
3883 */
3884 val = 0x4000;
3885
3886 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3887 val |= BIT7;
3888
3889 if (info->params.parity != ASYNC_PARITY_NONE) {
3890 val |= BIT9;
3891 if (info->params.parity == ASYNC_PARITY_ODD)
3892 val |= BIT8;
3893 }
3894
3895 switch (info->params.data_bits)
3896 {
3897 case 6: val |= BIT4; break;
3898 case 7: val |= BIT5; break;
3899 case 8: val |= BIT5 + BIT4; break;
3900 }
3901
3902 if (info->params.stop_bits != 1)
3903 val |= BIT3;
3904
3905 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3906 val |= BIT0;
3907
3908 wr_reg16(info, TCR, val);
3909
3910 /* RCR (rx control)
3911 *
3912 * 15..13 mode, 010=async
3913 * 12..10 encoding, 000=NRZ
3914 * 09 parity enable
3915 * 08 1=odd parity, 0=even parity
3916 * 07..06 reserved, must be 0
3917 * 05..04 character length
3918 * 00=5 bits
3919 * 01=6 bits
3920 * 10=7 bits
3921 * 11=8 bits
3922 * 03 reserved, must be zero
3923 * 02 reset
3924 * 01 enable
3925 * 00 auto-DCD enable
3926 */
3927 val = 0x4000;
3928
3929 if (info->params.parity != ASYNC_PARITY_NONE) {
3930 val |= BIT9;
3931 if (info->params.parity == ASYNC_PARITY_ODD)
3932 val |= BIT8;
3933 }
3934
3935 switch (info->params.data_bits)
3936 {
3937 case 6: val |= BIT4; break;
3938 case 7: val |= BIT5; break;
3939 case 8: val |= BIT5 + BIT4; break;
3940 }
3941
3942 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3943 val |= BIT0;
3944
3945 wr_reg16(info, RCR, val);
3946
3947 /* CCR (clock control)
3948 *
3949 * 07..05 011 = tx clock source is BRG/16
3950 * 04..02 010 = rx clock source is BRG
3951 * 01 0 = auxclk disabled
3952 * 00 1 = BRG enabled
3953 *
3954 * 0110 1001
3955 */
3956 wr_reg8(info, CCR, 0x69);
3957
3958 msc_set_vcr(info);
3959
3960 /* SCR (serial control)
3961 *
3962 * 15 1=tx req on FIFO half empty
3963 * 14 1=rx req on FIFO half full
3964 * 13 tx data IRQ enable
3965 * 12 tx idle IRQ enable
3966 * 11 rx break on IRQ enable
3967 * 10 rx data IRQ enable
3968 * 09 rx break off IRQ enable
3969 * 08 overrun IRQ enable
3970 * 07 DSR IRQ enable
3971 * 06 CTS IRQ enable
3972 * 05 DCD IRQ enable
3973 * 04 RI IRQ enable
3974 * 03 reserved, must be zero
3975 * 02 1=txd->rxd internal loopback enable
3976 * 01 reserved, must be zero
3977 * 00 1=master IRQ enable
3978 */
3979 val = BIT15 + BIT14 + BIT0;
3980 wr_reg16(info, SCR, val);
3981
3982 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3983
3984 set_rate(info, info->params.data_rate * 16);
3985
3986 if (info->params.loopback)
3987 enable_loopback(info);
3988 }
3989
3990 static void sync_mode(struct slgt_info *info)
3991 {
3992 unsigned short val;
3993
3994 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3995 tx_stop(info);
3996 rx_stop(info);
3997
3998 /* TCR (tx control)
3999 *
4000 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4001 * 12..10 encoding
4002 * 09 CRC enable
4003 * 08 CRC32
4004 * 07 1=RTS driver control
4005 * 06 preamble enable
4006 * 05..04 preamble length
4007 * 03 share open/close flag
4008 * 02 reset
4009 * 01 enable
4010 * 00 auto-CTS enable
4011 */
4012 val = 0;
4013
4014 switch(info->params.mode) {
4015 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4016 case MGSL_MODE_BISYNC: val |= BIT15; break;
4017 case MGSL_MODE_RAW: val |= BIT13; break;
4018 }
4019 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4020 val |= BIT7;
4021
4022 switch(info->params.encoding)
4023 {
4024 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4025 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4026 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4027 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4028 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4029 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4030 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4031 }
4032
4033 switch (info->params.crc_type & HDLC_CRC_MASK)
4034 {
4035 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4036 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4037 }
4038
4039 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4040 val |= BIT6;
4041
4042 switch (info->params.preamble_length)
4043 {
4044 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4045 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4046 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4047 }
4048
4049 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4050 val |= BIT0;
4051
4052 wr_reg16(info, TCR, val);
4053
4054 /* TPR (transmit preamble) */
4055
4056 switch (info->params.preamble)
4057 {
4058 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4059 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4060 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4061 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4062 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4063 default: val = 0x7e; break;
4064 }
4065 wr_reg8(info, TPR, (unsigned char)val);
4066
4067 /* RCR (rx control)
4068 *
4069 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4070 * 12..10 encoding
4071 * 09 CRC enable
4072 * 08 CRC32
4073 * 07..03 reserved, must be 0
4074 * 02 reset
4075 * 01 enable
4076 * 00 auto-DCD enable
4077 */
4078 val = 0;
4079
4080 switch(info->params.mode) {
4081 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4082 case MGSL_MODE_BISYNC: val |= BIT15; break;
4083 case MGSL_MODE_RAW: val |= BIT13; break;
4084 }
4085
4086 switch(info->params.encoding)
4087 {
4088 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4089 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4090 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4091 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4092 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4093 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4094 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4095 }
4096
4097 switch (info->params.crc_type & HDLC_CRC_MASK)
4098 {
4099 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4100 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4101 }
4102
4103 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4104 val |= BIT0;
4105
4106 wr_reg16(info, RCR, val);
4107
4108 /* CCR (clock control)
4109 *
4110 * 07..05 tx clock source
4111 * 04..02 rx clock source
4112 * 01 auxclk enable
4113 * 00 BRG enable
4114 */
4115 val = 0;
4116
4117 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4118 {
4119 // when RxC source is DPLL, BRG generates 16X DPLL
4120 // reference clock, so take TxC from BRG/16 to get
4121 // transmit clock at actual data rate
4122 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4123 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4124 else
4125 val |= BIT6; /* 010, txclk = BRG */
4126 }
4127 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4128 val |= BIT7; /* 100, txclk = DPLL Input */
4129 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4130 val |= BIT5; /* 001, txclk = RXC Input */
4131
4132 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4133 val |= BIT3; /* 010, rxclk = BRG */
4134 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4135 val |= BIT4; /* 100, rxclk = DPLL */
4136 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4137 val |= BIT2; /* 001, rxclk = TXC Input */
4138
4139 if (info->params.clock_speed)
4140 val |= BIT1 + BIT0;
4141
4142 wr_reg8(info, CCR, (unsigned char)val);
4143
4144 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4145 {
4146 // program DPLL mode
4147 switch(info->params.encoding)
4148 {
4149 case HDLC_ENCODING_BIPHASE_MARK:
4150 case HDLC_ENCODING_BIPHASE_SPACE:
4151 val = BIT7; break;
4152 case HDLC_ENCODING_BIPHASE_LEVEL:
4153 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4154 val = BIT7 + BIT6; break;
4155 default: val = BIT6; // NRZ encodings
4156 }
4157 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4158
4159 // DPLL requires a 16X reference clock from BRG
4160 set_rate(info, info->params.clock_speed * 16);
4161 }
4162 else
4163 set_rate(info, info->params.clock_speed);
4164
4165 tx_set_idle(info);
4166
4167 msc_set_vcr(info);
4168
4169 /* SCR (serial control)
4170 *
4171 * 15 1=tx req on FIFO half empty
4172 * 14 1=rx req on FIFO half full
4173 * 13 tx data IRQ enable
4174 * 12 tx idle IRQ enable
4175 * 11 underrun IRQ enable
4176 * 10 rx data IRQ enable
4177 * 09 rx idle IRQ enable
4178 * 08 overrun IRQ enable
4179 * 07 DSR IRQ enable
4180 * 06 CTS IRQ enable
4181 * 05 DCD IRQ enable
4182 * 04 RI IRQ enable
4183 * 03 reserved, must be zero
4184 * 02 1=txd->rxd internal loopback enable
4185 * 01 reserved, must be zero
4186 * 00 1=master IRQ enable
4187 */
4188 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4189
4190 if (info->params.loopback)
4191 enable_loopback(info);
4192 }
4193
4194 /*
4195 * set transmit idle mode
4196 */
4197 static void tx_set_idle(struct slgt_info *info)
4198 {
4199 unsigned char val;
4200 unsigned short tcr;
4201
4202 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4203 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4204 */
4205 tcr = rd_reg16(info, TCR);
4206 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4207 /* disable preamble, set idle size to 16 bits */
4208 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4209 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4210 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4211 } else if (!(tcr & BIT6)) {
4212 /* preamble is disabled, set idle size to 8 bits */
4213 tcr &= ~(BIT5 + BIT4);
4214 }
4215 wr_reg16(info, TCR, tcr);
4216
4217 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4218 /* LSB of custom tx idle specified in tx idle register */
4219 val = (unsigned char)(info->idle_mode & 0xff);
4220 } else {
4221 /* standard 8 bit idle patterns */
4222 switch(info->idle_mode)
4223 {
4224 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4225 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4226 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4227 case HDLC_TXIDLE_ZEROS:
4228 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4229 default: val = 0xff;
4230 }
4231 }
4232
4233 wr_reg8(info, TIR, val);
4234 }
4235
4236 /*
4237 * get state of V24 status (input) signals
4238 */
4239 static void get_signals(struct slgt_info *info)
4240 {
4241 unsigned short status = rd_reg16(info, SSR);
4242
4243 /* clear all serial signals except DTR and RTS */
4244 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4245
4246 if (status & BIT3)
4247 info->signals |= SerialSignal_DSR;
4248 if (status & BIT2)
4249 info->signals |= SerialSignal_CTS;
4250 if (status & BIT1)
4251 info->signals |= SerialSignal_DCD;
4252 if (status & BIT0)
4253 info->signals |= SerialSignal_RI;
4254 }
4255
4256 /*
4257 * set V.24 Control Register based on current configuration
4258 */
4259 static void msc_set_vcr(struct slgt_info *info)
4260 {
4261 unsigned char val = 0;
4262
4263 /* VCR (V.24 control)
4264 *
4265 * 07..04 serial IF select
4266 * 03 DTR
4267 * 02 RTS
4268 * 01 LL
4269 * 00 RL
4270 */
4271
4272 switch(info->if_mode & MGSL_INTERFACE_MASK)
4273 {
4274 case MGSL_INTERFACE_RS232:
4275 val |= BIT5; /* 0010 */
4276 break;
4277 case MGSL_INTERFACE_V35:
4278 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4279 break;
4280 case MGSL_INTERFACE_RS422:
4281 val |= BIT6; /* 0100 */
4282 break;
4283 }
4284
4285 if (info->signals & SerialSignal_DTR)
4286 val |= BIT3;
4287 if (info->signals & SerialSignal_RTS)
4288 val |= BIT2;
4289 if (info->if_mode & MGSL_INTERFACE_LL)
4290 val |= BIT1;
4291 if (info->if_mode & MGSL_INTERFACE_RL)
4292 val |= BIT0;
4293 wr_reg8(info, VCR, val);
4294 }
4295
4296 /*
4297 * set state of V24 control (output) signals
4298 */
4299 static void set_signals(struct slgt_info *info)
4300 {
4301 unsigned char val = rd_reg8(info, VCR);
4302 if (info->signals & SerialSignal_DTR)
4303 val |= BIT3;
4304 else
4305 val &= ~BIT3;
4306 if (info->signals & SerialSignal_RTS)
4307 val |= BIT2;
4308 else
4309 val &= ~BIT2;
4310 wr_reg8(info, VCR, val);
4311 }
4312
4313 /*
4314 * free range of receive DMA buffers (i to last)
4315 */
4316 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4317 {
4318 int done = 0;
4319
4320 while(!done) {
4321 /* reset current buffer for reuse */
4322 info->rbufs[i].status = 0;
4323 switch(info->params.mode) {
4324 case MGSL_MODE_RAW:
4325 case MGSL_MODE_MONOSYNC:
4326 case MGSL_MODE_BISYNC:
4327 set_desc_count(info->rbufs[i], info->raw_rx_size);
4328 break;
4329 default:
4330 set_desc_count(info->rbufs[i], DMABUFSIZE);
4331 }
4332
4333 if (i == last)
4334 done = 1;
4335 if (++i == info->rbuf_count)
4336 i = 0;
4337 }
4338 info->rbuf_current = i;
4339 }
4340
4341 /*
4342 * mark all receive DMA buffers as free
4343 */
4344 static void reset_rbufs(struct slgt_info *info)
4345 {
4346 free_rbufs(info, 0, info->rbuf_count - 1);
4347 }
4348
4349 /*
4350 * pass receive HDLC frame to upper layer
4351 *
4352 * return 1 if frame available, otherwise 0
4353 */
4354 static int rx_get_frame(struct slgt_info *info)
4355 {
4356 unsigned int start, end;
4357 unsigned short status;
4358 unsigned int framesize = 0;
4359 int rc = 0;
4360 unsigned long flags;
4361 struct tty_struct *tty = info->tty;
4362 unsigned char addr_field = 0xff;
4363 unsigned int crc_size = 0;
4364
4365 switch (info->params.crc_type & HDLC_CRC_MASK) {
4366 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4367 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4368 }
4369
4370 check_again:
4371
4372 framesize = 0;
4373 addr_field = 0xff;
4374 start = end = info->rbuf_current;
4375
4376 for (;;) {
4377 if (!desc_complete(info->rbufs[end]))
4378 goto cleanup;
4379
4380 if (framesize == 0 && info->params.addr_filter != 0xff)
4381 addr_field = info->rbufs[end].buf[0];
4382
4383 framesize += desc_count(info->rbufs[end]);
4384
4385 if (desc_eof(info->rbufs[end]))
4386 break;
4387
4388 if (++end == info->rbuf_count)
4389 end = 0;
4390
4391 if (end == info->rbuf_current) {
4392 if (info->rx_enabled){
4393 spin_lock_irqsave(&info->lock,flags);
4394 rx_start(info);
4395 spin_unlock_irqrestore(&info->lock,flags);
4396 }
4397 goto cleanup;
4398 }
4399 }
4400
4401 /* status
4402 *
4403 * 15 buffer complete
4404 * 14..06 reserved
4405 * 05..04 residue
4406 * 02 eof (end of frame)
4407 * 01 CRC error
4408 * 00 abort
4409 */
4410 status = desc_status(info->rbufs[end]);
4411
4412 /* ignore CRC bit if not using CRC (bit is undefined) */
4413 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4414 status &= ~BIT1;
4415
4416 if (framesize == 0 ||
4417 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4418 free_rbufs(info, start, end);
4419 goto check_again;
4420 }
4421
4422 if (framesize < (2 + crc_size) || status & BIT0) {
4423 info->icount.rxshort++;
4424 framesize = 0;
4425 } else if (status & BIT1) {
4426 info->icount.rxcrc++;
4427 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4428 framesize = 0;
4429 }
4430
4431 #if SYNCLINK_GENERIC_HDLC
4432 if (framesize == 0) {
4433 struct net_device_stats *stats = hdlc_stats(info->netdev);
4434 stats->rx_errors++;
4435 stats->rx_frame_errors++;
4436 }
4437 #endif
4438
4439 DBGBH(("%s rx frame status=%04X size=%d\n",
4440 info->device_name, status, framesize));
4441 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4442
4443 if (framesize) {
4444 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4445 framesize -= crc_size;
4446 crc_size = 0;
4447 }
4448
4449 if (framesize > info->max_frame_size + crc_size)
4450 info->icount.rxlong++;
4451 else {
4452 /* copy dma buffer(s) to contiguous temp buffer */
4453 int copy_count = framesize;
4454 int i = start;
4455 unsigned char *p = info->tmp_rbuf;
4456 info->tmp_rbuf_count = framesize;
4457
4458 info->icount.rxok++;
4459
4460 while(copy_count) {
4461 int partial_count = min(copy_count, DMABUFSIZE);
4462 memcpy(p, info->rbufs[i].buf, partial_count);
4463 p += partial_count;
4464 copy_count -= partial_count;
4465 if (++i == info->rbuf_count)
4466 i = 0;
4467 }
4468
4469 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4470 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4471 framesize++;
4472 }
4473
4474 #if SYNCLINK_GENERIC_HDLC
4475 if (info->netcount)
4476 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4477 else
4478 #endif
4479 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4480 }
4481 }
4482 free_rbufs(info, start, end);
4483 rc = 1;
4484
4485 cleanup:
4486 return rc;
4487 }
4488
4489 /*
4490 * pass receive buffer (RAW synchronous mode) to tty layer
4491 * return 1 if buffer available, otherwise 0
4492 */
4493 static int rx_get_buf(struct slgt_info *info)
4494 {
4495 unsigned int i = info->rbuf_current;
4496 unsigned int count;
4497
4498 if (!desc_complete(info->rbufs[i]))
4499 return 0;
4500 count = desc_count(info->rbufs[i]);
4501 switch(info->params.mode) {
4502 case MGSL_MODE_MONOSYNC:
4503 case MGSL_MODE_BISYNC:
4504 /* ignore residue in byte synchronous modes */
4505 if (desc_residue(info->rbufs[i]))
4506 count--;
4507 break;
4508 }
4509 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4510 DBGINFO(("rx_get_buf size=%d\n", count));
4511 if (count)
4512 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4513 info->flag_buf, count);
4514 free_rbufs(info, i, i);
4515 return 1;
4516 }
4517
4518 static void reset_tbufs(struct slgt_info *info)
4519 {
4520 unsigned int i;
4521 info->tbuf_current = 0;
4522 for (i=0 ; i < info->tbuf_count ; i++) {
4523 info->tbufs[i].status = 0;
4524 info->tbufs[i].count = 0;
4525 }
4526 }
4527
4528 /*
4529 * return number of free transmit DMA buffers
4530 */
4531 static unsigned int free_tbuf_count(struct slgt_info *info)
4532 {
4533 unsigned int count = 0;
4534 unsigned int i = info->tbuf_current;
4535
4536 do
4537 {
4538 if (desc_count(info->tbufs[i]))
4539 break; /* buffer in use */
4540 ++count;
4541 if (++i == info->tbuf_count)
4542 i=0;
4543 } while (i != info->tbuf_current);
4544
4545 /* last buffer with zero count may be in use, assume it is */
4546 if (count)
4547 --count;
4548
4549 return count;
4550 }
4551
4552 /*
4553 * load transmit DMA buffer(s) with data
4554 */
4555 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4556 {
4557 unsigned short count;
4558 unsigned int i;
4559 struct slgt_desc *d;
4560
4561 if (size == 0)
4562 return;
4563
4564 DBGDATA(info, buf, size, "tx");
4565
4566 info->tbuf_start = i = info->tbuf_current;
4567
4568 while (size) {
4569 d = &info->tbufs[i];
4570 if (++i == info->tbuf_count)
4571 i = 0;
4572
4573 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4574 memcpy(d->buf, buf, count);
4575
4576 size -= count;
4577 buf += count;
4578
4579 /*
4580 * set EOF bit for last buffer of HDLC frame or
4581 * for every buffer in raw mode
4582 */
4583 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4584 info->params.mode == MGSL_MODE_RAW)
4585 set_desc_eof(*d, 1);
4586 else
4587 set_desc_eof(*d, 0);
4588
4589 set_desc_count(*d, count);
4590 }
4591
4592 info->tbuf_current = i;
4593 }
4594
4595 static int register_test(struct slgt_info *info)
4596 {
4597 static unsigned short patterns[] =
4598 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4599 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4600 unsigned int i;
4601 int rc = 0;
4602
4603 for (i=0 ; i < count ; i++) {
4604 wr_reg16(info, TIR, patterns[i]);
4605 wr_reg16(info, BDR, patterns[(i+1)%count]);
4606 if ((rd_reg16(info, TIR) != patterns[i]) ||
4607 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4608 rc = -ENODEV;
4609 break;
4610 }
4611 }
4612 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4613 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4614 return rc;
4615 }
4616
4617 static int irq_test(struct slgt_info *info)
4618 {
4619 unsigned long timeout;
4620 unsigned long flags;
4621 struct tty_struct *oldtty = info->tty;
4622 u32 speed = info->params.data_rate;
4623
4624 info->params.data_rate = 921600;
4625 info->tty = NULL;
4626
4627 spin_lock_irqsave(&info->lock, flags);
4628 async_mode(info);
4629 slgt_irq_on(info, IRQ_TXIDLE);
4630
4631 /* enable transmitter */
4632 wr_reg16(info, TCR,
4633 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4634
4635 /* write one byte and wait for tx idle */
4636 wr_reg16(info, TDR, 0);
4637
4638 /* assume failure */
4639 info->init_error = DiagStatus_IrqFailure;
4640 info->irq_occurred = FALSE;
4641
4642 spin_unlock_irqrestore(&info->lock, flags);
4643
4644 timeout=100;
4645 while(timeout-- && !info->irq_occurred)
4646 msleep_interruptible(10);
4647
4648 spin_lock_irqsave(&info->lock,flags);
4649 reset_port(info);
4650 spin_unlock_irqrestore(&info->lock,flags);
4651
4652 info->params.data_rate = speed;
4653 info->tty = oldtty;
4654
4655 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4656 return info->irq_occurred ? 0 : -ENODEV;
4657 }
4658
4659 static int loopback_test_rx(struct slgt_info *info)
4660 {
4661 unsigned char *src, *dest;
4662 int count;
4663
4664 if (desc_complete(info->rbufs[0])) {
4665 count = desc_count(info->rbufs[0]);
4666 src = info->rbufs[0].buf;
4667 dest = info->tmp_rbuf;
4668
4669 for( ; count ; count-=2, src+=2) {
4670 /* src=data byte (src+1)=status byte */
4671 if (!(*(src+1) & (BIT9 + BIT8))) {
4672 *dest = *src;
4673 dest++;
4674 info->tmp_rbuf_count++;
4675 }
4676 }
4677 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4678 return 1;
4679 }
4680 return 0;
4681 }
4682
4683 static int loopback_test(struct slgt_info *info)
4684 {
4685 #define TESTFRAMESIZE 20
4686
4687 unsigned long timeout;
4688 u16 count = TESTFRAMESIZE;
4689 unsigned char buf[TESTFRAMESIZE];
4690 int rc = -ENODEV;
4691 unsigned long flags;
4692
4693 struct tty_struct *oldtty = info->tty;
4694 MGSL_PARAMS params;
4695
4696 memcpy(&params, &info->params, sizeof(params));
4697
4698 info->params.mode = MGSL_MODE_ASYNC;
4699 info->params.data_rate = 921600;
4700 info->params.loopback = 1;
4701 info->tty = NULL;
4702
4703 /* build and send transmit frame */
4704 for (count = 0; count < TESTFRAMESIZE; ++count)
4705 buf[count] = (unsigned char)count;
4706
4707 info->tmp_rbuf_count = 0;
4708 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4709
4710 /* program hardware for HDLC and enabled receiver */
4711 spin_lock_irqsave(&info->lock,flags);
4712 async_mode(info);
4713 rx_start(info);
4714 info->tx_count = count;
4715 tx_load(info, buf, count);
4716 tx_start(info);
4717 spin_unlock_irqrestore(&info->lock, flags);
4718
4719 /* wait for receive complete */
4720 for (timeout = 100; timeout; --timeout) {
4721 msleep_interruptible(10);
4722 if (loopback_test_rx(info)) {
4723 rc = 0;
4724 break;
4725 }
4726 }
4727
4728 /* verify received frame length and contents */
4729 if (!rc && (info->tmp_rbuf_count != count ||
4730 memcmp(buf, info->tmp_rbuf, count))) {
4731 rc = -ENODEV;
4732 }
4733
4734 spin_lock_irqsave(&info->lock,flags);
4735 reset_adapter(info);
4736 spin_unlock_irqrestore(&info->lock,flags);
4737
4738 memcpy(&info->params, &params, sizeof(info->params));
4739 info->tty = oldtty;
4740
4741 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4742 return rc;
4743 }
4744
4745 static int adapter_test(struct slgt_info *info)
4746 {
4747 DBGINFO(("testing %s\n", info->device_name));
4748 if (register_test(info) < 0) {
4749 printk("register test failure %s addr=%08X\n",
4750 info->device_name, info->phys_reg_addr);
4751 } else if (irq_test(info) < 0) {
4752 printk("IRQ test failure %s IRQ=%d\n",
4753 info->device_name, info->irq_level);
4754 } else if (loopback_test(info) < 0) {
4755 printk("loopback test failure %s\n", info->device_name);
4756 }
4757 return info->init_error;
4758 }
4759
4760 /*
4761 * transmit timeout handler
4762 */
4763 static void tx_timeout(unsigned long context)
4764 {
4765 struct slgt_info *info = (struct slgt_info*)context;
4766 unsigned long flags;
4767
4768 DBGINFO(("%s tx_timeout\n", info->device_name));
4769 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4770 info->icount.txtimeout++;
4771 }
4772 spin_lock_irqsave(&info->lock,flags);
4773 info->tx_active = 0;
4774 info->tx_count = 0;
4775 spin_unlock_irqrestore(&info->lock,flags);
4776
4777 #if SYNCLINK_GENERIC_HDLC
4778 if (info->netcount)
4779 hdlcdev_tx_done(info);
4780 else
4781 #endif
4782 bh_transmit(info);
4783 }
4784
4785 /*
4786 * receive buffer polling timer
4787 */
4788 static void rx_timeout(unsigned long context)
4789 {
4790 struct slgt_info *info = (struct slgt_info*)context;
4791 unsigned long flags;
4792
4793 DBGINFO(("%s rx_timeout\n", info->device_name));
4794 spin_lock_irqsave(&info->lock, flags);
4795 info->pending_bh |= BH_RECEIVE;
4796 spin_unlock_irqrestore(&info->lock, flags);
4797 bh_handler(&info->task);
4798 }
4799
WRT350N Kernel Patches