arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/notifier.h>
  12 #include <linux/smp.h>
  13 #include <linux/oprofile.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/slab.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/kdebug.h>
  18 #include <asm/nmi.h>
  19 #include <asm/msr.h>
  20 #include <asm/apic.h>
  21
  22 #include "op_counter.h"
  23 #include "op_x86_model.h"
  24
  25 static struct op_x86_model_spec const *model;
  26 static struct op_msrs cpu_msrs[NR_CPUS];
  27 static unsigned long saved_lvtpc[NR_CPUS];
  28
  29 static int nmi_start(void);
  30 static void nmi_stop(void);
  31
  32 /* 0 == registered but off, 1 == registered and on */
  33 static int nmi_enabled = 0;
  34
  35 #ifdef CONFIG_PM
  36
  37 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  38 {
  39         if (nmi_enabled == 1)
  40                 nmi_stop();
  41         return 0;
  42 }
  43
  44 static int nmi_resume(struct sys_device *dev)
  45 {
  46         if (nmi_enabled == 1)
  47                 nmi_start();
  48         return 0;
  49 }
  50
  51 static struct sysdev_class oprofile_sysclass = {
  52         .name           = "oprofile",
  53         .resume         = nmi_resume,
  54         .suspend        = nmi_suspend,
  55 };
  56
  57 static struct sys_device device_oprofile = {
  58         .id     = 0,
  59         .cls    = &oprofile_sysclass,
  60 };
  61
  62 static int __init init_sysfs(void)
  63 {
  64         int error;
  65
  66         error = sysdev_class_register(&oprofile_sysclass);
  67         if (!error)
  68                 error = sysdev_register(&device_oprofile);
  69         return error;
  70 }
  71
  72 static void exit_sysfs(void)
  73 {
  74         sysdev_unregister(&device_oprofile);
  75         sysdev_class_unregister(&oprofile_sysclass);
  76 }
  77
  78 #else
  79 #define init_sysfs() do { } while (0)
  80 #define exit_sysfs() do { } while (0)
  81 #endif /* CONFIG_PM */
  82
  83 static int profile_exceptions_notify(struct notifier_block *self,
  84                                      unsigned long val, void *data)
  85 {
  86         struct die_args *args = (struct die_args *)data;
  87         int ret = NOTIFY_DONE;
  88         int cpu = smp_processor_id();
  89
  90         switch (val) {
  91         case DIE_NMI:
  92                 if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
  93                         ret = NOTIFY_STOP;
  94                 break;
  95         default:
  96                 break;
  97         }
  98         return ret;
  99 }
 100
 101 static void nmi_cpu_save_registers(struct op_msrs *msrs)
 102 {
 103         unsigned int const nr_ctrs = model->num_counters;
 104         unsigned int const nr_ctrls = model->num_controls;
 105         struct op_msr *counters = msrs->counters;
 106         struct op_msr *controls = msrs->controls;
 107         unsigned int i;
 108
 109         for (i = 0; i < nr_ctrs; ++i) {
 110                 if (counters[i].addr) {
 111                         rdmsr(counters[i].addr,
 112                                 counters[i].saved.low,
 113                                 counters[i].saved.high);
 114                 }
 115         }
 116
 117         for (i = 0; i < nr_ctrls; ++i) {
 118                 if (controls[i].addr) {
 119                         rdmsr(controls[i].addr,
 120                                 controls[i].saved.low,
 121                                 controls[i].saved.high);
 122                 }
 123         }
 124 }
 125
 126 static void nmi_save_registers(void *dummy)
 127 {
 128         int cpu = smp_processor_id();
 129         struct op_msrs *msrs = &cpu_msrs[cpu];
 130         nmi_cpu_save_registers(msrs);
 131 }
 132
 133 static void free_msrs(void)
 134 {
 135         int i;
 136         for_each_possible_cpu(i) {
 137                 kfree(cpu_msrs[i].counters);
 138                 cpu_msrs[i].counters = NULL;
 139                 kfree(cpu_msrs[i].controls);
 140                 cpu_msrs[i].controls = NULL;
 141         }
 142 }
 143
 144 static int allocate_msrs(void)
 145 {
 146         int success = 1;
 147         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 148         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 149
 150         int i;
 151         for_each_possible_cpu(i) {
 152                 cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
 153                 if (!cpu_msrs[i].counters) {
 154                         success = 0;
 155                         break;
 156                 }
 157                 cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
 158                 if (!cpu_msrs[i].controls) {
 159                         success = 0;
 160                         break;
 161                 }
 162         }
 163
 164         if (!success)
 165                 free_msrs();
 166
 167         return success;
 168 }
 169
 170 static void nmi_cpu_setup(void *dummy)
 171 {
 172         int cpu = smp_processor_id();
 173         struct op_msrs *msrs = &cpu_msrs[cpu];
 174         spin_lock(&oprofilefs_lock);
 175         model->setup_ctrs(msrs);
 176         spin_unlock(&oprofilefs_lock);
 177         saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
 178         apic_write(APIC_LVTPC, APIC_DM_NMI);
 179 }
 180
 181 static struct notifier_block profile_exceptions_nb = {
 182         .notifier_call = profile_exceptions_notify,
 183         .next = NULL,
 184         .priority = 0
 185 };
 186
 187 static int nmi_setup(void)
 188 {
 189         int err = 0;
 190         int cpu;
 191
 192         if (!allocate_msrs())
 193                 return -ENOMEM;
 194
 195         err = register_die_notifier(&profile_exceptions_nb);
 196         if (err) {
 197                 free_msrs();
 198                 return err;
 199         }
 200
 201         /* We need to serialize save and setup for HT because the subset
 202          * of msrs are distinct for save and setup operations
 203          */
 204
 205         /* Assume saved/restored counters are the same on all CPUs */
 206         model->fill_in_addresses(&cpu_msrs[0]);
 207         for_each_possible_cpu(cpu) {
 208                 if (cpu != 0) {
 209                         memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
 210                                 sizeof(struct op_msr) * model->num_counters);
 211
 212                         memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
 213                                 sizeof(struct op_msr) * model->num_controls);
 214                 }
 215
 216         }
 217         on_each_cpu(nmi_save_registers, NULL, 0, 1);
 218         on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
 219         nmi_enabled = 1;
 220         return 0;
 221 }
 222
 223 static void nmi_restore_registers(struct op_msrs *msrs)
 224 {
 225         unsigned int const nr_ctrs = model->num_counters;
 226         unsigned int const nr_ctrls = model->num_controls;
 227         struct op_msr *counters = msrs->counters;
 228         struct op_msr *controls = msrs->controls;
 229         unsigned int i;
 230
 231         for (i = 0; i < nr_ctrls; ++i) {
 232                 if (controls[i].addr) {
 233                         wrmsr(controls[i].addr,
 234                                 controls[i].saved.low,
 235                                 controls[i].saved.high);
 236                 }
 237         }
 238
 239         for (i = 0; i < nr_ctrs; ++i) {
 240                 if (counters[i].addr) {
 241                         wrmsr(counters[i].addr,
 242                                 counters[i].saved.low,
 243                                 counters[i].saved.high);
 244                 }
 245         }
 246 }
 247
 248 static void nmi_cpu_shutdown(void *dummy)
 249 {
 250         unsigned int v;
 251         int cpu = smp_processor_id();
 252         struct op_msrs *msrs = &cpu_msrs[cpu];
 253
 254         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 255          * mode and vector nr combination can be illegal. That's by design: on
 256          * power on apic lvt contain a zero vector nr which are legal only for
 257          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 258          */
 259         v = apic_read(APIC_LVTERR);
 260         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 261         apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
 262         apic_write(APIC_LVTERR, v);
 263         nmi_restore_registers(msrs);
 264 }
 265
 266 static void nmi_shutdown(void)
 267 {
 268         nmi_enabled = 0;
 269         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
 270         unregister_die_notifier(&profile_exceptions_nb);
 271         model->shutdown(cpu_msrs);
 272         free_msrs();
 273 }
 274
 275 static void nmi_cpu_start(void *dummy)
 276 {
 277         struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
 278         model->start(msrs);
 279 }
 280
 281 static int nmi_start(void)
 282 {
 283         on_each_cpu(nmi_cpu_start, NULL, 0, 1);
 284         return 0;
 285 }
 286
 287 static void nmi_cpu_stop(void *dummy)
 288 {
 289         struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
 290         model->stop(msrs);
 291 }
 292
 293 static void nmi_stop(void)
 294 {
 295         on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
 296 }
 297
 298 struct op_counter_config counter_config[OP_MAX_COUNTER];
 299
 300 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 301 {
 302         unsigned int i;
 303
 304         for (i = 0; i < model->num_counters; ++i) {
 305                 struct dentry *dir;
 306                 char buf[4];
 307
 308                 /* quick little hack to _not_ expose a counter if it is not
 309                  * available for use.  This should protect userspace app.
 310                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 311                  *        sequentially in their struct assignment).
 312                  */
 313                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 314                         continue;
 315
 316                 snprintf(buf,  sizeof(buf), "%d", i);
 317                 dir = oprofilefs_mkdir(sb, root, buf);
 318                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 319                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 320                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 321                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 322                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 323                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int p4force;
 330 module_param(p4force, int, 0);
 331
 332 static int __init p4_init(char **cpu_type)
 333 {
 334         __u8 cpu_model = boot_cpu_data.x86_model;
 335
 336         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 337                 return 0;
 338
 339 #ifndef CONFIG_SMP
 340         *cpu_type = "i386/p4";
 341         model = &op_p4_spec;
 342         return 1;
 343 #else
 344         switch (smp_num_siblings) {
 345         case 1:
 346                 *cpu_type = "i386/p4";
 347                 model = &op_p4_spec;
 348                 return 1;
 349
 350         case 2:
 351                 *cpu_type = "i386/p4-ht";
 352                 model = &op_p4_ht2_spec;
 353                 return 1;
 354         }
 355 #endif
 356
 357         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 358         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 359         return 0;
 360 }
 361
 362 static int __init ppro_init(char **cpu_type)
 363 {
 364         __u8 cpu_model = boot_cpu_data.x86_model;
 365
 366         if (cpu_model == 14)
 367                 *cpu_type = "i386/core";
 368         else if (cpu_model == 15 || cpu_model == 23)
 369                 *cpu_type = "i386/core_2";
 370         else if (cpu_model > 0xd)
 371                 return 0;
 372         else if (cpu_model == 9) {
 373                 *cpu_type = "i386/p6_mobile";
 374         } else if (cpu_model > 5) {
 375                 *cpu_type = "i386/piii";
 376         } else if (cpu_model > 2) {
 377                 *cpu_type = "i386/pii";
 378         } else {
 379                 *cpu_type = "i386/ppro";
 380         }
 381
 382         model = &op_ppro_spec;
 383         return 1;
 384 }
 385
 386 /* in order to get sysfs right */
 387 static int using_nmi;
 388
 389 int __init op_nmi_init(struct oprofile_operations *ops)
 390 {
 391         __u8 vendor = boot_cpu_data.x86_vendor;
 392         __u8 family = boot_cpu_data.x86;
 393         char *cpu_type;
 394
 395         if (!cpu_has_apic)
 396                 return -ENODEV;
 397
 398         switch (vendor) {
 399         case X86_VENDOR_AMD:
 400                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 401
 402                 switch (family) {
 403                 default:
 404                         return -ENODEV;
 405                 case 6:
 406                         model = &op_athlon_spec;
 407                         cpu_type = "i386/athlon";
 408                         break;
 409                 case 0xf:
 410                         model = &op_athlon_spec;
 411                         /* Actually it could be i386/hammer too, but give
 412                          user space an consistent name. */
 413                         cpu_type = "x86-64/hammer";
 414                         break;
 415                 case 0x10:
 416                         model = &op_athlon_spec;
 417                         cpu_type = "x86-64/family10";
 418                         break;
 419                 }
 420                 break;
 421
 422         case X86_VENDOR_INTEL:
 423                 switch (family) {
 424                         /* Pentium IV */
 425                 case 0xf:
 426                         if (!p4_init(&cpu_type))
 427                                 return -ENODEV;
 428                         break;
 429
 430                         /* A P6-class processor */
 431                 case 6:
 432                         if (!ppro_init(&cpu_type))
 433                                 return -ENODEV;
 434                         break;
 435
 436                 default:
 437                         return -ENODEV;
 438                 }
 439                 break;
 440
 441         default:
 442                 return -ENODEV;
 443         }
 444
 445         init_sysfs();
 446         using_nmi = 1;
 447         ops->create_files = nmi_create_files;
 448         ops->setup = nmi_setup;
 449         ops->shutdown = nmi_shutdown;
 450         ops->start = nmi_start;
 451         ops->stop = nmi_stop;
 452         ops->cpu_type = cpu_type;
 453         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 454         return 0;
 455 }
 456
 457 void op_nmi_exit(void)
 458 {
 459         if (using_nmi)
 460                 exit_sysfs();
 461 }