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Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[wrt350n-kernel.git] / drivers / net / wireless / b43 / main.c
blob51dfce16178a7ca2276f91ec551635ffc3e7205d
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
44
45 #include "b43.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "sysfs.h"
51 #include "xmit.h"
52 #include "lo.h"
53 #include "pcmcia.h"
54
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
60
61 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
62
63
64 static int modparam_bad_frames_preempt;
65 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
66 MODULE_PARM_DESC(bad_frames_preempt,
67 "enable(1) / disable(0) Bad Frames Preemption");
68
69 static char modparam_fwpostfix[16];
70 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
71 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
72
73 static int modparam_hwpctl;
74 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
75 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
76
77 static int modparam_nohwcrypt;
78 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
79 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
80
81 static const struct ssb_device_id b43_ssb_tbl[] = {
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
89 SSB_DEVTABLE_END
90 };
91
92 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
93
94 /* Channel and ratetables are shared for all devices.
95 * They can't be const, because ieee80211 puts some precalculated
96 * data in there. This data is the same for all devices, so we don't
97 * get concurrency issues */
98 #define RATETAB_ENT(_rateid, _flags) \
99 { \
100 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
101 .val = (_rateid), \
102 .val2 = (_rateid), \
103 .flags = (_flags), \
104 }
105 static struct ieee80211_rate __b43_ratetable[] = {
106 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
107 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
108 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
109 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
110 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
115 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
116 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
117 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
118 };
119
120 #define b43_a_ratetable (__b43_ratetable + 4)
121 #define b43_a_ratetable_size 8
122 #define b43_b_ratetable (__b43_ratetable + 0)
123 #define b43_b_ratetable_size 4
124 #define b43_g_ratetable (__b43_ratetable + 0)
125 #define b43_g_ratetable_size 12
126
127 #define CHANTAB_ENT(_chanid, _freq) \
128 { \
129 .chan = (_chanid), \
130 .freq = (_freq), \
131 .val = (_chanid), \
132 .flag = IEEE80211_CHAN_W_SCAN | \
133 IEEE80211_CHAN_W_ACTIVE_SCAN | \
134 IEEE80211_CHAN_W_IBSS, \
135 .power_level = 0xFF, \
136 .antenna_max = 0xFF, \
137 }
138 static struct ieee80211_channel b43_2ghz_chantable[] = {
139 CHANTAB_ENT(1, 2412),
140 CHANTAB_ENT(2, 2417),
141 CHANTAB_ENT(3, 2422),
142 CHANTAB_ENT(4, 2427),
143 CHANTAB_ENT(5, 2432),
144 CHANTAB_ENT(6, 2437),
145 CHANTAB_ENT(7, 2442),
146 CHANTAB_ENT(8, 2447),
147 CHANTAB_ENT(9, 2452),
148 CHANTAB_ENT(10, 2457),
149 CHANTAB_ENT(11, 2462),
150 CHANTAB_ENT(12, 2467),
151 CHANTAB_ENT(13, 2472),
152 CHANTAB_ENT(14, 2484),
153 };
154 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
155
156 #if 0
157 static struct ieee80211_channel b43_5ghz_chantable[] = {
158 CHANTAB_ENT(36, 5180),
159 CHANTAB_ENT(40, 5200),
160 CHANTAB_ENT(44, 5220),
161 CHANTAB_ENT(48, 5240),
162 CHANTAB_ENT(52, 5260),
163 CHANTAB_ENT(56, 5280),
164 CHANTAB_ENT(60, 5300),
165 CHANTAB_ENT(64, 5320),
166 CHANTAB_ENT(149, 5745),
167 CHANTAB_ENT(153, 5765),
168 CHANTAB_ENT(157, 5785),
169 CHANTAB_ENT(161, 5805),
170 CHANTAB_ENT(165, 5825),
171 };
172 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
173 #endif
174
175 static void b43_wireless_core_exit(struct b43_wldev *dev);
176 static int b43_wireless_core_init(struct b43_wldev *dev);
177 static void b43_wireless_core_stop(struct b43_wldev *dev);
178 static int b43_wireless_core_start(struct b43_wldev *dev);
179
180 static int b43_ratelimit(struct b43_wl *wl)
181 {
182 if (!wl || !wl->current_dev)
183 return 1;
184 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
185 return 1;
186 /* We are up and running.
187 * Ratelimit the messages to avoid DoS over the net. */
188 return net_ratelimit();
189 }
190
191 void b43info(struct b43_wl *wl, const char *fmt, ...)
192 {
193 va_list args;
194
195 if (!b43_ratelimit(wl))
196 return;
197 va_start(args, fmt);
198 printk(KERN_INFO "b43-%s: ",
199 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
200 vprintk(fmt, args);
201 va_end(args);
202 }
203
204 void b43err(struct b43_wl *wl, const char *fmt, ...)
205 {
206 va_list args;
207
208 if (!b43_ratelimit(wl))
209 return;
210 va_start(args, fmt);
211 printk(KERN_ERR "b43-%s ERROR: ",
212 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
213 vprintk(fmt, args);
214 va_end(args);
215 }
216
217 void b43warn(struct b43_wl *wl, const char *fmt, ...)
218 {
219 va_list args;
220
221 if (!b43_ratelimit(wl))
222 return;
223 va_start(args, fmt);
224 printk(KERN_WARNING "b43-%s warning: ",
225 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
226 vprintk(fmt, args);
227 va_end(args);
228 }
229
230 #if B43_DEBUG
231 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
232 {
233 va_list args;
234
235 va_start(args, fmt);
236 printk(KERN_DEBUG "b43-%s debug: ",
237 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
238 vprintk(fmt, args);
239 va_end(args);
240 }
241 #endif /* DEBUG */
242
243 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
244 {
245 u32 macctl;
246
247 B43_WARN_ON(offset % 4 != 0);
248
249 macctl = b43_read32(dev, B43_MMIO_MACCTL);
250 if (macctl & B43_MACCTL_BE)
251 val = swab32(val);
252
253 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
254 mmiowb();
255 b43_write32(dev, B43_MMIO_RAM_DATA, val);
256 }
257
258 static inline void b43_shm_control_word(struct b43_wldev *dev,
259 u16 routing, u16 offset)
260 {
261 u32 control;
262
263 /* "offset" is the WORD offset. */
264 control = routing;
265 control <<= 16;
266 control |= offset;
267 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
268 }
269
270 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
271 {
272 struct b43_wl *wl = dev->wl;
273 unsigned long flags;
274 u32 ret;
275
276 spin_lock_irqsave(&wl->shm_lock, flags);
277 if (routing == B43_SHM_SHARED) {
278 B43_WARN_ON(offset & 0x0001);
279 if (offset & 0x0003) {
280 /* Unaligned access */
281 b43_shm_control_word(dev, routing, offset >> 2);
282 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
283 ret <<= 16;
284 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
285 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
286
287 goto out;
288 }
289 offset >>= 2;
290 }
291 b43_shm_control_word(dev, routing, offset);
292 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
293 out:
294 spin_unlock_irqrestore(&wl->shm_lock, flags);
295
296 return ret;
297 }
298
299 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
300 {
301 struct b43_wl *wl = dev->wl;
302 unsigned long flags;
303 u16 ret;
304
305 spin_lock_irqsave(&wl->shm_lock, flags);
306 if (routing == B43_SHM_SHARED) {
307 B43_WARN_ON(offset & 0x0001);
308 if (offset & 0x0003) {
309 /* Unaligned access */
310 b43_shm_control_word(dev, routing, offset >> 2);
311 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
312
313 goto out;
314 }
315 offset >>= 2;
316 }
317 b43_shm_control_word(dev, routing, offset);
318 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
319 out:
320 spin_unlock_irqrestore(&wl->shm_lock, flags);
321
322 return ret;
323 }
324
325 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
326 {
327 struct b43_wl *wl = dev->wl;
328 unsigned long flags;
329
330 spin_lock_irqsave(&wl->shm_lock, flags);
331 if (routing == B43_SHM_SHARED) {
332 B43_WARN_ON(offset & 0x0001);
333 if (offset & 0x0003) {
334 /* Unaligned access */
335 b43_shm_control_word(dev, routing, offset >> 2);
336 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
337 (value >> 16) & 0xffff);
338 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
339 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
340 goto out;
341 }
342 offset >>= 2;
343 }
344 b43_shm_control_word(dev, routing, offset);
345 b43_write32(dev, B43_MMIO_SHM_DATA, value);
346 out:
347 spin_unlock_irqrestore(&wl->shm_lock, flags);
348 }
349
350 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
351 {
352 struct b43_wl *wl = dev->wl;
353 unsigned long flags;
354
355 spin_lock_irqsave(&wl->shm_lock, flags);
356 if (routing == B43_SHM_SHARED) {
357 B43_WARN_ON(offset & 0x0001);
358 if (offset & 0x0003) {
359 /* Unaligned access */
360 b43_shm_control_word(dev, routing, offset >> 2);
361 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
362 goto out;
363 }
364 offset >>= 2;
365 }
366 b43_shm_control_word(dev, routing, offset);
367 b43_write16(dev, B43_MMIO_SHM_DATA, value);
368 out:
369 spin_unlock_irqrestore(&wl->shm_lock, flags);
370 }
371
372 /* Read HostFlags */
373 u32 b43_hf_read(struct b43_wldev * dev)
374 {
375 u32 ret;
376
377 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
378 ret <<= 16;
379 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
380
381 return ret;
382 }
383
384 /* Write HostFlags */
385 void b43_hf_write(struct b43_wldev *dev, u32 value)
386 {
387 b43_shm_write16(dev, B43_SHM_SHARED,
388 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
389 b43_shm_write16(dev, B43_SHM_SHARED,
390 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
391 }
392
393 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
394 {
395 /* We need to be careful. As we read the TSF from multiple
396 * registers, we should take care of register overflows.
397 * In theory, the whole tsf read process should be atomic.
398 * We try to be atomic here, by restaring the read process,
399 * if any of the high registers changed (overflew).
400 */
401 if (dev->dev->id.revision >= 3) {
402 u32 low, high, high2;
403
404 do {
405 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
406 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
407 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
408 } while (unlikely(high != high2));
409
410 *tsf = high;
411 *tsf <<= 32;
412 *tsf |= low;
413 } else {
414 u64 tmp;
415 u16 v0, v1, v2, v3;
416 u16 test1, test2, test3;
417
418 do {
419 v3 = b43_read16(dev, B43_MMIO_TSF_3);
420 v2 = b43_read16(dev, B43_MMIO_TSF_2);
421 v1 = b43_read16(dev, B43_MMIO_TSF_1);
422 v0 = b43_read16(dev, B43_MMIO_TSF_0);
423
424 test3 = b43_read16(dev, B43_MMIO_TSF_3);
425 test2 = b43_read16(dev, B43_MMIO_TSF_2);
426 test1 = b43_read16(dev, B43_MMIO_TSF_1);
427 } while (v3 != test3 || v2 != test2 || v1 != test1);
428
429 *tsf = v3;
430 *tsf <<= 48;
431 tmp = v2;
432 tmp <<= 32;
433 *tsf |= tmp;
434 tmp = v1;
435 tmp <<= 16;
436 *tsf |= tmp;
437 *tsf |= v0;
438 }
439 }
440
441 static void b43_time_lock(struct b43_wldev *dev)
442 {
443 u32 macctl;
444
445 macctl = b43_read32(dev, B43_MMIO_MACCTL);
446 macctl |= B43_MACCTL_TBTTHOLD;
447 b43_write32(dev, B43_MMIO_MACCTL, macctl);
448 /* Commit the write */
449 b43_read32(dev, B43_MMIO_MACCTL);
450 }
451
452 static void b43_time_unlock(struct b43_wldev *dev)
453 {
454 u32 macctl;
455
456 macctl = b43_read32(dev, B43_MMIO_MACCTL);
457 macctl &= ~B43_MACCTL_TBTTHOLD;
458 b43_write32(dev, B43_MMIO_MACCTL, macctl);
459 /* Commit the write */
460 b43_read32(dev, B43_MMIO_MACCTL);
461 }
462
463 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
464 {
465 /* Be careful with the in-progress timer.
466 * First zero out the low register, so we have a full
467 * register-overflow duration to complete the operation.
468 */
469 if (dev->dev->id.revision >= 3) {
470 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
471 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
472
473 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
474 mmiowb();
475 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
476 mmiowb();
477 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
478 } else {
479 u16 v0 = (tsf & 0x000000000000FFFFULL);
480 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
481 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
482 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483
484 b43_write16(dev, B43_MMIO_TSF_0, 0);
485 mmiowb();
486 b43_write16(dev, B43_MMIO_TSF_3, v3);
487 mmiowb();
488 b43_write16(dev, B43_MMIO_TSF_2, v2);
489 mmiowb();
490 b43_write16(dev, B43_MMIO_TSF_1, v1);
491 mmiowb();
492 b43_write16(dev, B43_MMIO_TSF_0, v0);
493 }
494 }
495
496 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
497 {
498 b43_time_lock(dev);
499 b43_tsf_write_locked(dev, tsf);
500 b43_time_unlock(dev);
501 }
502
503 static
504 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
505 {
506 static const u8 zero_addr[ETH_ALEN] = { 0 };
507 u16 data;
508
509 if (!mac)
510 mac = zero_addr;
511
512 offset |= 0x0020;
513 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
514
515 data = mac[0];
516 data |= mac[1] << 8;
517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 data = mac[2];
519 data |= mac[3] << 8;
520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
521 data = mac[4];
522 data |= mac[5] << 8;
523 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
524 }
525
526 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
527 {
528 const u8 *mac;
529 const u8 *bssid;
530 u8 mac_bssid[ETH_ALEN * 2];
531 int i;
532 u32 tmp;
533
534 bssid = dev->wl->bssid;
535 mac = dev->wl->mac_addr;
536
537 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
538
539 memcpy(mac_bssid, mac, ETH_ALEN);
540 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
541
542 /* Write our MAC address and BSSID to template ram */
543 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
544 tmp = (u32) (mac_bssid[i + 0]);
545 tmp |= (u32) (mac_bssid[i + 1]) << 8;
546 tmp |= (u32) (mac_bssid[i + 2]) << 16;
547 tmp |= (u32) (mac_bssid[i + 3]) << 24;
548 b43_ram_write(dev, 0x20 + i, tmp);
549 }
550 }
551
552 static void b43_upload_card_macaddress(struct b43_wldev *dev)
553 {
554 b43_write_mac_bssid_templates(dev);
555 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
556 }
557
558 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
559 {
560 /* slot_time is in usec. */
561 if (dev->phy.type != B43_PHYTYPE_G)
562 return;
563 b43_write16(dev, 0x684, 510 + slot_time);
564 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
565 }
566
567 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
568 {
569 b43_set_slot_time(dev, 9);
570 dev->short_slot = 1;
571 }
572
573 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
574 {
575 b43_set_slot_time(dev, 20);
576 dev->short_slot = 0;
577 }
578
579 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
580 * Returns the _previously_ enabled IRQ mask.
581 */
582 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
583 {
584 u32 old_mask;
585
586 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
587 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
588
589 return old_mask;
590 }
591
592 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
593 * Returns the _previously_ enabled IRQ mask.
594 */
595 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
596 {
597 u32 old_mask;
598
599 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
600 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
601
602 return old_mask;
603 }
604
605 /* Synchronize IRQ top- and bottom-half.
606 * IRQs must be masked before calling this.
607 * This must not be called with the irq_lock held.
608 */
609 static void b43_synchronize_irq(struct b43_wldev *dev)
610 {
611 synchronize_irq(dev->dev->irq);
612 tasklet_kill(&dev->isr_tasklet);
613 }
614
615 /* DummyTransmission function, as documented on
616 * http://bcm-specs.sipsolutions.net/DummyTransmission
617 */
618 void b43_dummy_transmission(struct b43_wldev *dev)
619 {
620 struct b43_phy *phy = &dev->phy;
621 unsigned int i, max_loop;
622 u16 value;
623 u32 buffer[5] = {
624 0x00000000,
625 0x00D40000,
626 0x00000000,
627 0x01000000,
628 0x00000000,
629 };
630
631 switch (phy->type) {
632 case B43_PHYTYPE_A:
633 max_loop = 0x1E;
634 buffer[0] = 0x000201CC;
635 break;
636 case B43_PHYTYPE_B:
637 case B43_PHYTYPE_G:
638 max_loop = 0xFA;
639 buffer[0] = 0x000B846E;
640 break;
641 default:
642 B43_WARN_ON(1);
643 return;
644 }
645
646 for (i = 0; i < 5; i++)
647 b43_ram_write(dev, i * 4, buffer[i]);
648
649 /* Commit writes */
650 b43_read32(dev, B43_MMIO_MACCTL);
651
652 b43_write16(dev, 0x0568, 0x0000);
653 b43_write16(dev, 0x07C0, 0x0000);
654 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
655 b43_write16(dev, 0x050C, value);
656 b43_write16(dev, 0x0508, 0x0000);
657 b43_write16(dev, 0x050A, 0x0000);
658 b43_write16(dev, 0x054C, 0x0000);
659 b43_write16(dev, 0x056A, 0x0014);
660 b43_write16(dev, 0x0568, 0x0826);
661 b43_write16(dev, 0x0500, 0x0000);
662 b43_write16(dev, 0x0502, 0x0030);
663
664 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
665 b43_radio_write16(dev, 0x0051, 0x0017);
666 for (i = 0x00; i < max_loop; i++) {
667 value = b43_read16(dev, 0x050E);
668 if (value & 0x0080)
669 break;
670 udelay(10);
671 }
672 for (i = 0x00; i < 0x0A; i++) {
673 value = b43_read16(dev, 0x050E);
674 if (value & 0x0400)
675 break;
676 udelay(10);
677 }
678 for (i = 0x00; i < 0x0A; i++) {
679 value = b43_read16(dev, 0x0690);
680 if (!(value & 0x0100))
681 break;
682 udelay(10);
683 }
684 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
685 b43_radio_write16(dev, 0x0051, 0x0037);
686 }
687
688 static void key_write(struct b43_wldev *dev,
689 u8 index, u8 algorithm, const u8 * key)
690 {
691 unsigned int i;
692 u32 offset;
693 u16 value;
694 u16 kidx;
695
696 /* Key index/algo block */
697 kidx = b43_kidx_to_fw(dev, index);
698 value = ((kidx << 4) | algorithm);
699 b43_shm_write16(dev, B43_SHM_SHARED,
700 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
701
702 /* Write the key to the Key Table Pointer offset */
703 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
704 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
705 value = key[i];
706 value |= (u16) (key[i + 1]) << 8;
707 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
708 }
709 }
710
711 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
712 {
713 u32 addrtmp[2] = { 0, 0, };
714 u8 per_sta_keys_start = 8;
715
716 if (b43_new_kidx_api(dev))
717 per_sta_keys_start = 4;
718
719 B43_WARN_ON(index < per_sta_keys_start);
720 /* We have two default TX keys and possibly two default RX keys.
721 * Physical mac 0 is mapped to physical key 4 or 8, depending
722 * on the firmware version.
723 * So we must adjust the index here.
724 */
725 index -= per_sta_keys_start;
726
727 if (addr) {
728 addrtmp[0] = addr[0];
729 addrtmp[0] |= ((u32) (addr[1]) << 8);
730 addrtmp[0] |= ((u32) (addr[2]) << 16);
731 addrtmp[0] |= ((u32) (addr[3]) << 24);
732 addrtmp[1] = addr[4];
733 addrtmp[1] |= ((u32) (addr[5]) << 8);
734 }
735
736 if (dev->dev->id.revision >= 5) {
737 /* Receive match transmitter address mechanism */
738 b43_shm_write32(dev, B43_SHM_RCMTA,
739 (index * 2) + 0, addrtmp[0]);
740 b43_shm_write16(dev, B43_SHM_RCMTA,
741 (index * 2) + 1, addrtmp[1]);
742 } else {
743 /* RXE (Receive Engine) and
744 * PSM (Programmable State Machine) mechanism
745 */
746 if (index < 8) {
747 /* TODO write to RCM 16, 19, 22 and 25 */
748 } else {
749 b43_shm_write32(dev, B43_SHM_SHARED,
750 B43_SHM_SH_PSM + (index * 6) + 0,
751 addrtmp[0]);
752 b43_shm_write16(dev, B43_SHM_SHARED,
753 B43_SHM_SH_PSM + (index * 6) + 4,
754 addrtmp[1]);
755 }
756 }
757 }
758
759 static void do_key_write(struct b43_wldev *dev,
760 u8 index, u8 algorithm,
761 const u8 * key, size_t key_len, const u8 * mac_addr)
762 {
763 u8 buf[B43_SEC_KEYSIZE] = { 0, };
764 u8 per_sta_keys_start = 8;
765
766 if (b43_new_kidx_api(dev))
767 per_sta_keys_start = 4;
768
769 B43_WARN_ON(index >= dev->max_nr_keys);
770 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
771
772 if (index >= per_sta_keys_start)
773 keymac_write(dev, index, NULL); /* First zero out mac. */
774 if (key)
775 memcpy(buf, key, key_len);
776 key_write(dev, index, algorithm, buf);
777 if (index >= per_sta_keys_start)
778 keymac_write(dev, index, mac_addr);
779
780 dev->key[index].algorithm = algorithm;
781 }
782
783 static int b43_key_write(struct b43_wldev *dev,
784 int index, u8 algorithm,
785 const u8 * key, size_t key_len,
786 const u8 * mac_addr,
787 struct ieee80211_key_conf *keyconf)
788 {
789 int i;
790 int sta_keys_start;
791
792 if (key_len > B43_SEC_KEYSIZE)
793 return -EINVAL;
794 for (i = 0; i < dev->max_nr_keys; i++) {
795 /* Check that we don't already have this key. */
796 B43_WARN_ON(dev->key[i].keyconf == keyconf);
797 }
798 if (index < 0) {
799 /* Either pairwise key or address is 00:00:00:00:00:00
800 * for transmit-only keys. Search the index. */
801 if (b43_new_kidx_api(dev))
802 sta_keys_start = 4;
803 else
804 sta_keys_start = 8;
805 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
806 if (!dev->key[i].keyconf) {
807 /* found empty */
808 index = i;
809 break;
810 }
811 }
812 if (index < 0) {
813 b43err(dev->wl, "Out of hardware key memory\n");
814 return -ENOSPC;
815 }
816 } else
817 B43_WARN_ON(index > 3);
818
819 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
820 if ((index <= 3) && !b43_new_kidx_api(dev)) {
821 /* Default RX key */
822 B43_WARN_ON(mac_addr);
823 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
824 }
825 keyconf->hw_key_idx = index;
826 dev->key[index].keyconf = keyconf;
827
828 return 0;
829 }
830
831 static int b43_key_clear(struct b43_wldev *dev, int index)
832 {
833 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
834 return -EINVAL;
835 do_key_write(dev, index, B43_SEC_ALGO_NONE,
836 NULL, B43_SEC_KEYSIZE, NULL);
837 if ((index <= 3) && !b43_new_kidx_api(dev)) {
838 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
839 NULL, B43_SEC_KEYSIZE, NULL);
840 }
841 dev->key[index].keyconf = NULL;
842
843 return 0;
844 }
845
846 static void b43_clear_keys(struct b43_wldev *dev)
847 {
848 int i;
849
850 for (i = 0; i < dev->max_nr_keys; i++)
851 b43_key_clear(dev, i);
852 }
853
854 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
855 {
856 u32 macctl;
857 u16 ucstat;
858 bool hwps;
859 bool awake;
860 int i;
861
862 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
863 (ps_flags & B43_PS_DISABLED));
864 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
865
866 if (ps_flags & B43_PS_ENABLED) {
867 hwps = 1;
868 } else if (ps_flags & B43_PS_DISABLED) {
869 hwps = 0;
870 } else {
871 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
872 // and thus is not an AP and we are associated, set bit 25
873 }
874 if (ps_flags & B43_PS_AWAKE) {
875 awake = 1;
876 } else if (ps_flags & B43_PS_ASLEEP) {
877 awake = 0;
878 } else {
879 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
880 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
881 // successful, set bit26
882 }
883
884 /* FIXME: For now we force awake-on and hwps-off */
885 hwps = 0;
886 awake = 1;
887
888 macctl = b43_read32(dev, B43_MMIO_MACCTL);
889 if (hwps)
890 macctl |= B43_MACCTL_HWPS;
891 else
892 macctl &= ~B43_MACCTL_HWPS;
893 if (awake)
894 macctl |= B43_MACCTL_AWAKE;
895 else
896 macctl &= ~B43_MACCTL_AWAKE;
897 b43_write32(dev, B43_MMIO_MACCTL, macctl);
898 /* Commit write */
899 b43_read32(dev, B43_MMIO_MACCTL);
900 if (awake && dev->dev->id.revision >= 5) {
901 /* Wait for the microcode to wake up. */
902 for (i = 0; i < 100; i++) {
903 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
904 B43_SHM_SH_UCODESTAT);
905 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
906 break;
907 udelay(10);
908 }
909 }
910 }
911
912 /* Turn the Analog ON/OFF */
913 static void b43_switch_analog(struct b43_wldev *dev, int on)
914 {
915 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
916 }
917
918 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
919 {
920 u32 tmslow;
921 u32 macctl;
922
923 flags |= B43_TMSLOW_PHYCLKEN;
924 flags |= B43_TMSLOW_PHYRESET;
925 ssb_device_enable(dev->dev, flags);
926 msleep(2); /* Wait for the PLL to turn on. */
927
928 /* Now take the PHY out of Reset again */
929 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
930 tmslow |= SSB_TMSLOW_FGC;
931 tmslow &= ~B43_TMSLOW_PHYRESET;
932 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
933 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
934 msleep(1);
935 tmslow &= ~SSB_TMSLOW_FGC;
936 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
937 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
938 msleep(1);
939
940 /* Turn Analog ON */
941 b43_switch_analog(dev, 1);
942
943 macctl = b43_read32(dev, B43_MMIO_MACCTL);
944 macctl &= ~B43_MACCTL_GMODE;
945 if (flags & B43_TMSLOW_GMODE)
946 macctl |= B43_MACCTL_GMODE;
947 macctl |= B43_MACCTL_IHR_ENABLED;
948 b43_write32(dev, B43_MMIO_MACCTL, macctl);
949 }
950
951 static void handle_irq_transmit_status(struct b43_wldev *dev)
952 {
953 u32 v0, v1;
954 u16 tmp;
955 struct b43_txstatus stat;
956
957 while (1) {
958 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
959 if (!(v0 & 0x00000001))
960 break;
961 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
962
963 stat.cookie = (v0 >> 16);
964 stat.seq = (v1 & 0x0000FFFF);
965 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
966 tmp = (v0 & 0x0000FFFF);
967 stat.frame_count = ((tmp & 0xF000) >> 12);
968 stat.rts_count = ((tmp & 0x0F00) >> 8);
969 stat.supp_reason = ((tmp & 0x001C) >> 2);
970 stat.pm_indicated = !!(tmp & 0x0080);
971 stat.intermediate = !!(tmp & 0x0040);
972 stat.for_ampdu = !!(tmp & 0x0020);
973 stat.acked = !!(tmp & 0x0002);
974
975 b43_handle_txstatus(dev, &stat);
976 }
977 }
978
979 static void drain_txstatus_queue(struct b43_wldev *dev)
980 {
981 u32 dummy;
982
983 if (dev->dev->id.revision < 5)
984 return;
985 /* Read all entries from the microcode TXstatus FIFO
986 * and throw them away.
987 */
988 while (1) {
989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
990 if (!(dummy & 0x00000001))
991 break;
992 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
993 }
994 }
995
996 static u32 b43_jssi_read(struct b43_wldev *dev)
997 {
998 u32 val = 0;
999
1000 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1001 val <<= 16;
1002 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1003
1004 return val;
1005 }
1006
1007 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1008 {
1009 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1010 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1011 }
1012
1013 static void b43_generate_noise_sample(struct b43_wldev *dev)
1014 {
1015 b43_jssi_write(dev, 0x7F7F7F7F);
1016 b43_write32(dev, B43_MMIO_MACCMD,
1017 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1018 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1019 }
1020
1021 static void b43_calculate_link_quality(struct b43_wldev *dev)
1022 {
1023 /* Top half of Link Quality calculation. */
1024
1025 if (dev->noisecalc.calculation_running)
1026 return;
1027 dev->noisecalc.channel_at_start = dev->phy.channel;
1028 dev->noisecalc.calculation_running = 1;
1029 dev->noisecalc.nr_samples = 0;
1030
1031 b43_generate_noise_sample(dev);
1032 }
1033
1034 static void handle_irq_noise(struct b43_wldev *dev)
1035 {
1036 struct b43_phy *phy = &dev->phy;
1037 u16 tmp;
1038 u8 noise[4];
1039 u8 i, j;
1040 s32 average;
1041
1042 /* Bottom half of Link Quality calculation. */
1043
1044 B43_WARN_ON(!dev->noisecalc.calculation_running);
1045 if (dev->noisecalc.channel_at_start != phy->channel)
1046 goto drop_calculation;
1047 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1048 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1049 noise[2] == 0x7F || noise[3] == 0x7F)
1050 goto generate_new;
1051
1052 /* Get the noise samples. */
1053 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1054 i = dev->noisecalc.nr_samples;
1055 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1060 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1061 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1062 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1063 dev->noisecalc.nr_samples++;
1064 if (dev->noisecalc.nr_samples == 8) {
1065 /* Calculate the Link Quality by the noise samples. */
1066 average = 0;
1067 for (i = 0; i < 8; i++) {
1068 for (j = 0; j < 4; j++)
1069 average += dev->noisecalc.samples[i][j];
1070 }
1071 average /= (8 * 4);
1072 average *= 125;
1073 average += 64;
1074 average /= 128;
1075 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1076 tmp = (tmp / 128) & 0x1F;
1077 if (tmp >= 8)
1078 average += 2;
1079 else
1080 average -= 25;
1081 if (tmp == 8)
1082 average -= 72;
1083 else
1084 average -= 48;
1085
1086 dev->stats.link_noise = average;
1087 drop_calculation:
1088 dev->noisecalc.calculation_running = 0;
1089 return;
1090 }
1091 generate_new:
1092 b43_generate_noise_sample(dev);
1093 }
1094
1095 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1096 {
1097 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1098 ///TODO: PS TBTT
1099 } else {
1100 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1101 b43_power_saving_ctl_bits(dev, 0);
1102 }
1103 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1104 dev->dfq_valid = 1;
1105 }
1106
1107 static void handle_irq_atim_end(struct b43_wldev *dev)
1108 {
1109 if (dev->dfq_valid) {
1110 b43_write32(dev, B43_MMIO_MACCMD,
1111 b43_read32(dev, B43_MMIO_MACCMD)
1112 | B43_MACCMD_DFQ_VALID);
1113 dev->dfq_valid = 0;
1114 }
1115 }
1116
1117 static void handle_irq_pmq(struct b43_wldev *dev)
1118 {
1119 u32 tmp;
1120
1121 //TODO: AP mode.
1122
1123 while (1) {
1124 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1125 if (!(tmp & 0x00000008))
1126 break;
1127 }
1128 /* 16bit write is odd, but correct. */
1129 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1130 }
1131
1132 static void b43_write_template_common(struct b43_wldev *dev,
1133 const u8 * data, u16 size,
1134 u16 ram_offset,
1135 u16 shm_size_offset, u8 rate)
1136 {
1137 u32 i, tmp;
1138 struct b43_plcp_hdr4 plcp;
1139
1140 plcp.data = 0;
1141 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1142 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1143 ram_offset += sizeof(u32);
1144 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1145 * So leave the first two bytes of the next write blank.
1146 */
1147 tmp = (u32) (data[0]) << 16;
1148 tmp |= (u32) (data[1]) << 24;
1149 b43_ram_write(dev, ram_offset, tmp);
1150 ram_offset += sizeof(u32);
1151 for (i = 2; i < size; i += sizeof(u32)) {
1152 tmp = (u32) (data[i + 0]);
1153 if (i + 1 < size)
1154 tmp |= (u32) (data[i + 1]) << 8;
1155 if (i + 2 < size)
1156 tmp |= (u32) (data[i + 2]) << 16;
1157 if (i + 3 < size)
1158 tmp |= (u32) (data[i + 3]) << 24;
1159 b43_ram_write(dev, ram_offset + i - 2, tmp);
1160 }
1161 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1162 size + sizeof(struct b43_plcp_hdr6));
1163 }
1164
1165 static void b43_write_beacon_template(struct b43_wldev *dev,
1166 u16 ram_offset,
1167 u16 shm_size_offset, u8 rate)
1168 {
1169 unsigned int i, len, variable_len;
1170 const struct ieee80211_mgmt *bcn;
1171 const u8 *ie;
1172 bool tim_found = 0;
1173
1174 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1175 len = min((size_t) dev->wl->current_beacon->len,
1176 0x200 - sizeof(struct b43_plcp_hdr6));
1177
1178 b43_write_template_common(dev, (const u8 *)bcn,
1179 len, ram_offset, shm_size_offset, rate);
1180
1181 /* Find the position of the TIM and the DTIM_period value
1182 * and write them to SHM. */
1183 ie = bcn->u.beacon.variable;
1184 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1185 for (i = 0; i < variable_len - 2; ) {
1186 uint8_t ie_id, ie_len;
1187
1188 ie_id = ie[i];
1189 ie_len = ie[i + 1];
1190 if (ie_id == 5) {
1191 u16 tim_position;
1192 u16 dtim_period;
1193 /* This is the TIM Information Element */
1194
1195 /* Check whether the ie_len is in the beacon data range. */
1196 if (variable_len < ie_len + 2 + i)
1197 break;
1198 /* A valid TIM is at least 4 bytes long. */
1199 if (ie_len < 4)
1200 break;
1201 tim_found = 1;
1202
1203 tim_position = sizeof(struct b43_plcp_hdr6);
1204 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1205 tim_position += i;
1206
1207 dtim_period = ie[i + 3];
1208
1209 b43_shm_write16(dev, B43_SHM_SHARED,
1210 B43_SHM_SH_TIMBPOS, tim_position);
1211 b43_shm_write16(dev, B43_SHM_SHARED,
1212 B43_SHM_SH_DTIMPER, dtim_period);
1213 break;
1214 }
1215 i += ie_len + 2;
1216 }
1217 if (!tim_found) {
1218 b43warn(dev->wl, "Did not find a valid TIM IE in "
1219 "the beacon template packet. AP or IBSS operation "
1220 "may be broken.\n");
1221 }
1222 }
1223
1224 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1225 u16 shm_offset, u16 size, u8 rate)
1226 {
1227 struct b43_plcp_hdr4 plcp;
1228 u32 tmp;
1229 __le16 dur;
1230
1231 plcp.data = 0;
1232 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1233 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1234 dev->wl->vif, size,
1235 B43_RATE_TO_BASE100KBPS(rate));
1236 /* Write PLCP in two parts and timing for packet transfer */
1237 tmp = le32_to_cpu(plcp.data);
1238 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1239 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1240 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1241 }
1242
1243 /* Instead of using custom probe response template, this function
1244 * just patches custom beacon template by:
1245 * 1) Changing packet type
1246 * 2) Patching duration field
1247 * 3) Stripping TIM
1248 */
1249 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1250 u16 *dest_size, u8 rate)
1251 {
1252 const u8 *src_data;
1253 u8 *dest_data;
1254 u16 src_size, elem_size, src_pos, dest_pos;
1255 __le16 dur;
1256 struct ieee80211_hdr *hdr;
1257 size_t ie_start;
1258
1259 src_size = dev->wl->current_beacon->len;
1260 src_data = (const u8 *)dev->wl->current_beacon->data;
1261
1262 /* Get the start offset of the variable IEs in the packet. */
1263 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1264 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1265
1266 if (B43_WARN_ON(src_size < ie_start))
1267 return NULL;
1268
1269 dest_data = kmalloc(src_size, GFP_ATOMIC);
1270 if (unlikely(!dest_data))
1271 return NULL;
1272
1273 /* Copy the static data and all Information Elements, except the TIM. */
1274 memcpy(dest_data, src_data, ie_start);
1275 src_pos = ie_start;
1276 dest_pos = ie_start;
1277 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1278 elem_size = src_data[src_pos + 1] + 2;
1279 if (src_data[src_pos] == 5) {
1280 /* This is the TIM. */
1281 continue;
1282 }
1283 memcpy(dest_data + dest_pos, src_data + src_pos,
1284 elem_size);
1285 dest_pos += elem_size;
1286 }
1287 *dest_size = dest_pos;
1288 hdr = (struct ieee80211_hdr *)dest_data;
1289
1290 /* Set the frame control. */
1291 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1292 IEEE80211_STYPE_PROBE_RESP);
1293 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1294 dev->wl->vif, *dest_size,
1295 B43_RATE_TO_BASE100KBPS(rate));
1296 hdr->duration_id = dur;
1297
1298 return dest_data;
1299 }
1300
1301 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1302 u16 ram_offset,
1303 u16 shm_size_offset, u8 rate)
1304 {
1305 const u8 *probe_resp_data;
1306 u16 size;
1307
1308 size = dev->wl->current_beacon->len;
1309 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1310 if (unlikely(!probe_resp_data))
1311 return;
1312
1313 /* Looks like PLCP headers plus packet timings are stored for
1314 * all possible basic rates
1315 */
1316 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1317 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1318 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1319 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1320
1321 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1322 b43_write_template_common(dev, probe_resp_data,
1323 size, ram_offset, shm_size_offset, rate);
1324 kfree(probe_resp_data);
1325 }
1326
1327 /* Asynchronously update the packet templates in template RAM.
1328 * Locking: Requires wl->irq_lock to be locked. */
1329 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1330 {
1331 /* This is the top half of the ansynchronous beacon update.
1332 * The bottom half is the beacon IRQ.
1333 * Beacon update must be asynchronous to avoid sending an
1334 * invalid beacon. This can happen for example, if the firmware
1335 * transmits a beacon while we are updating it. */
1336
1337 if (wl->current_beacon)
1338 dev_kfree_skb_any(wl->current_beacon);
1339 wl->current_beacon = beacon;
1340 wl->beacon0_uploaded = 0;
1341 wl->beacon1_uploaded = 0;
1342 }
1343
1344 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1345 {
1346 u32 tmp;
1347 u16 i, len;
1348
1349 len = min((u16) ssid_len, (u16) 0x100);
1350 for (i = 0; i < len; i += sizeof(u32)) {
1351 tmp = (u32) (ssid[i + 0]);
1352 if (i + 1 < len)
1353 tmp |= (u32) (ssid[i + 1]) << 8;
1354 if (i + 2 < len)
1355 tmp |= (u32) (ssid[i + 2]) << 16;
1356 if (i + 3 < len)
1357 tmp |= (u32) (ssid[i + 3]) << 24;
1358 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1359 }
1360 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1361 }
1362
1363 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1364 {
1365 b43_time_lock(dev);
1366 if (dev->dev->id.revision >= 3) {
1367 b43_write32(dev, 0x188, (beacon_int << 16));
1368 } else {
1369 b43_write16(dev, 0x606, (beacon_int >> 6));
1370 b43_write16(dev, 0x610, beacon_int);
1371 }
1372 b43_time_unlock(dev);
1373 }
1374
1375 static void handle_irq_beacon(struct b43_wldev *dev)
1376 {
1377 struct b43_wl *wl = dev->wl;
1378 u32 cmd;
1379
1380 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1381 return;
1382
1383 /* This is the bottom half of the asynchronous beacon update. */
1384
1385 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1386 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1387 if (!wl->beacon0_uploaded) {
1388 b43_write_beacon_template(dev, 0x68, 0x18,
1389 B43_CCK_RATE_1MB);
1390 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1391 B43_CCK_RATE_11MB);
1392 wl->beacon0_uploaded = 1;
1393 }
1394 cmd |= B43_MACCMD_BEACON0_VALID;
1395 }
1396 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1397 if (!wl->beacon1_uploaded) {
1398 b43_write_beacon_template(dev, 0x468, 0x1A,
1399 B43_CCK_RATE_1MB);
1400 wl->beacon1_uploaded = 1;
1401 }
1402 cmd |= B43_MACCMD_BEACON1_VALID;
1403 }
1404 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1405 }
1406
1407 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1408 {
1409 //TODO
1410 }
1411
1412 /* Interrupt handler bottom-half */
1413 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1414 {
1415 u32 reason;
1416 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1417 u32 merged_dma_reason = 0;
1418 int i;
1419 unsigned long flags;
1420
1421 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1422
1423 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1424
1425 reason = dev->irq_reason;
1426 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1427 dma_reason[i] = dev->dma_reason[i];
1428 merged_dma_reason |= dma_reason[i];
1429 }
1430
1431 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1432 b43err(dev->wl, "MAC transmission error\n");
1433
1434 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1435 b43err(dev->wl, "PHY transmission error\n");
1436 rmb();
1437 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1438 atomic_set(&dev->phy.txerr_cnt,
1439 B43_PHY_TX_BADNESS_LIMIT);
1440 b43err(dev->wl, "Too many PHY TX errors, "
1441 "restarting the controller\n");
1442 b43_controller_restart(dev, "PHY TX errors");
1443 }
1444 }
1445
1446 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1447 B43_DMAIRQ_NONFATALMASK))) {
1448 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1449 b43err(dev->wl, "Fatal DMA error: "
1450 "0x%08X, 0x%08X, 0x%08X, "
1451 "0x%08X, 0x%08X, 0x%08X\n",
1452 dma_reason[0], dma_reason[1],
1453 dma_reason[2], dma_reason[3],
1454 dma_reason[4], dma_reason[5]);
1455 b43_controller_restart(dev, "DMA error");
1456 mmiowb();
1457 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1458 return;
1459 }
1460 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1461 b43err(dev->wl, "DMA error: "
1462 "0x%08X, 0x%08X, 0x%08X, "
1463 "0x%08X, 0x%08X, 0x%08X\n",
1464 dma_reason[0], dma_reason[1],
1465 dma_reason[2], dma_reason[3],
1466 dma_reason[4], dma_reason[5]);
1467 }
1468 }
1469
1470 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1471 handle_irq_ucode_debug(dev);
1472 if (reason & B43_IRQ_TBTT_INDI)
1473 handle_irq_tbtt_indication(dev);
1474 if (reason & B43_IRQ_ATIM_END)
1475 handle_irq_atim_end(dev);
1476 if (reason & B43_IRQ_BEACON)
1477 handle_irq_beacon(dev);
1478 if (reason & B43_IRQ_PMQ)
1479 handle_irq_pmq(dev);
1480 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1481 ;/* TODO */
1482 if (reason & B43_IRQ_NOISESAMPLE_OK)
1483 handle_irq_noise(dev);
1484
1485 /* Check the DMA reason registers for received data. */
1486 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1487 b43_dma_rx(dev->dma.rx_ring0);
1488 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1489 b43_dma_rx(dev->dma.rx_ring3);
1490 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1491 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1492 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1493 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1494
1495 if (reason & B43_IRQ_TX_OK)
1496 handle_irq_transmit_status(dev);
1497
1498 b43_interrupt_enable(dev, dev->irq_savedstate);
1499 mmiowb();
1500 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1501 }
1502
1503 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1504 {
1505 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1506
1507 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1508 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1509 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1510 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1511 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1512 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1513 }
1514
1515 /* Interrupt handler top-half */
1516 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1517 {
1518 irqreturn_t ret = IRQ_NONE;
1519 struct b43_wldev *dev = dev_id;
1520 u32 reason;
1521
1522 if (!dev)
1523 return IRQ_NONE;
1524
1525 spin_lock(&dev->wl->irq_lock);
1526
1527 if (b43_status(dev) < B43_STAT_STARTED)
1528 goto out;
1529 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1530 if (reason == 0xffffffff) /* shared IRQ */
1531 goto out;
1532 ret = IRQ_HANDLED;
1533 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1534 if (!reason)
1535 goto out;
1536
1537 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1538 & 0x0001DC00;
1539 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1540 & 0x0000DC00;
1541 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1542 & 0x0000DC00;
1543 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1544 & 0x0001DC00;
1545 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1546 & 0x0000DC00;
1547 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1548 & 0x0000DC00;
1549
1550 b43_interrupt_ack(dev, reason);
1551 /* disable all IRQs. They are enabled again in the bottom half. */
1552 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1553 /* save the reason code and call our bottom half. */
1554 dev->irq_reason = reason;
1555 tasklet_schedule(&dev->isr_tasklet);
1556 out:
1557 mmiowb();
1558 spin_unlock(&dev->wl->irq_lock);
1559
1560 return ret;
1561 }
1562
1563 static void do_release_fw(struct b43_firmware_file *fw)
1564 {
1565 release_firmware(fw->data);
1566 fw->data = NULL;
1567 fw->filename = NULL;
1568 }
1569
1570 static void b43_release_firmware(struct b43_wldev *dev)
1571 {
1572 do_release_fw(&dev->fw.ucode);
1573 do_release_fw(&dev->fw.pcm);
1574 do_release_fw(&dev->fw.initvals);
1575 do_release_fw(&dev->fw.initvals_band);
1576 }
1577
1578 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1579 {
1580 const char *text;
1581
1582 text = "You must go to "
1583 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1584 "and download the latest firmware (version 4).\n";
1585 if (error)
1586 b43err(wl, text);
1587 else
1588 b43warn(wl, text);
1589 }
1590
1591 static int do_request_fw(struct b43_wldev *dev,
1592 const char *name,
1593 struct b43_firmware_file *fw)
1594 {
1595 char path[sizeof(modparam_fwpostfix) + 32];
1596 const struct firmware *blob;
1597 struct b43_fw_header *hdr;
1598 u32 size;
1599 int err;
1600
1601 if (!name) {
1602 /* Don't fetch anything. Free possibly cached firmware. */
1603 do_release_fw(fw);
1604 return 0;
1605 }
1606 if (fw->filename) {
1607 if (strcmp(fw->filename, name) == 0)
1608 return 0; /* Already have this fw. */
1609 /* Free the cached firmware first. */
1610 do_release_fw(fw);
1611 }
1612
1613 snprintf(path, ARRAY_SIZE(path),
1614 "b43%s/%s.fw",
1615 modparam_fwpostfix, name);
1616 err = request_firmware(&blob, path, dev->dev->dev);
1617 if (err) {
1618 b43err(dev->wl, "Firmware file \"%s\" not found "
1619 "or load failed.\n", path);
1620 return err;
1621 }
1622 if (blob->size < sizeof(struct b43_fw_header))
1623 goto err_format;
1624 hdr = (struct b43_fw_header *)(blob->data);
1625 switch (hdr->type) {
1626 case B43_FW_TYPE_UCODE:
1627 case B43_FW_TYPE_PCM:
1628 size = be32_to_cpu(hdr->size);
1629 if (size != blob->size - sizeof(struct b43_fw_header))
1630 goto err_format;
1631 /* fallthrough */
1632 case B43_FW_TYPE_IV:
1633 if (hdr->ver != 1)
1634 goto err_format;
1635 break;
1636 default:
1637 goto err_format;
1638 }
1639
1640 fw->data = blob;
1641 fw->filename = name;
1642
1643 return 0;
1644
1645 err_format:
1646 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1647 release_firmware(blob);
1648
1649 return -EPROTO;
1650 }
1651
1652 static int b43_request_firmware(struct b43_wldev *dev)
1653 {
1654 struct b43_firmware *fw = &dev->fw;
1655 const u8 rev = dev->dev->id.revision;
1656 const char *filename;
1657 u32 tmshigh;
1658 int err;
1659
1660 /* Get microcode */
1661 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1662 if ((rev >= 5) && (rev <= 10))
1663 filename = "ucode5";
1664 else if ((rev >= 11) && (rev <= 12))
1665 filename = "ucode11";
1666 else if (rev >= 13)
1667 filename = "ucode13";
1668 else
1669 goto err_no_ucode;
1670 err = do_request_fw(dev, filename, &fw->ucode);
1671 if (err)
1672 goto err_load;
1673
1674 /* Get PCM code */
1675 if ((rev >= 5) && (rev <= 10))
1676 filename = "pcm5";
1677 else if (rev >= 11)
1678 filename = NULL;
1679 else
1680 goto err_no_pcm;
1681 err = do_request_fw(dev, filename, &fw->pcm);
1682 if (err)
1683 goto err_load;
1684
1685 /* Get initvals */
1686 switch (dev->phy.type) {
1687 case B43_PHYTYPE_A:
1688 if ((rev >= 5) && (rev <= 10)) {
1689 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1690 filename = "a0g1initvals5";
1691 else
1692 filename = "a0g0initvals5";
1693 } else
1694 goto err_no_initvals;
1695 break;
1696 case B43_PHYTYPE_G:
1697 if ((rev >= 5) && (rev <= 10))
1698 filename = "b0g0initvals5";
1699 else if (rev >= 13)
1700 filename = "lp0initvals13";
1701 else
1702 goto err_no_initvals;
1703 break;
1704 case B43_PHYTYPE_N:
1705 if ((rev >= 11) && (rev <= 12))
1706 filename = "n0initvals11";
1707 else
1708 goto err_no_initvals;
1709 break;
1710 default:
1711 goto err_no_initvals;
1712 }
1713 err = do_request_fw(dev, filename, &fw->initvals);
1714 if (err)
1715 goto err_load;
1716
1717 /* Get bandswitch initvals */
1718 switch (dev->phy.type) {
1719 case B43_PHYTYPE_A:
1720 if ((rev >= 5) && (rev <= 10)) {
1721 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1722 filename = "a0g1bsinitvals5";
1723 else
1724 filename = "a0g0bsinitvals5";
1725 } else if (rev >= 11)
1726 filename = NULL;
1727 else
1728 goto err_no_initvals;
1729 break;
1730 case B43_PHYTYPE_G:
1731 if ((rev >= 5) && (rev <= 10))
1732 filename = "b0g0bsinitvals5";
1733 else if (rev >= 11)
1734 filename = NULL;
1735 else
1736 goto err_no_initvals;
1737 break;
1738 case B43_PHYTYPE_N:
1739 if ((rev >= 11) && (rev <= 12))
1740 filename = "n0bsinitvals11";
1741 else
1742 goto err_no_initvals;
1743 break;
1744 default:
1745 goto err_no_initvals;
1746 }
1747 err = do_request_fw(dev, filename, &fw->initvals_band);
1748 if (err)
1749 goto err_load;
1750
1751 return 0;
1752
1753 err_load:
1754 b43_print_fw_helptext(dev->wl, 1);
1755 goto error;
1756
1757 err_no_ucode:
1758 err = -ENODEV;
1759 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1760 goto error;
1761
1762 err_no_pcm:
1763 err = -ENODEV;
1764 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1765 goto error;
1766
1767 err_no_initvals:
1768 err = -ENODEV;
1769 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1770 "core rev %u\n", dev->phy.type, rev);
1771 goto error;
1772
1773 error:
1774 b43_release_firmware(dev);
1775 return err;
1776 }
1777
1778 static int b43_upload_microcode(struct b43_wldev *dev)
1779 {
1780 const size_t hdr_len = sizeof(struct b43_fw_header);
1781 const __be32 *data;
1782 unsigned int i, len;
1783 u16 fwrev, fwpatch, fwdate, fwtime;
1784 u32 tmp, macctl;
1785 int err = 0;
1786
1787 /* Jump the microcode PSM to offset 0 */
1788 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1789 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1790 macctl |= B43_MACCTL_PSM_JMP0;
1791 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1792 /* Zero out all microcode PSM registers and shared memory. */
1793 for (i = 0; i < 64; i++)
1794 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1795 for (i = 0; i < 4096; i += 2)
1796 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1797
1798 /* Upload Microcode. */
1799 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1800 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1801 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1802 for (i = 0; i < len; i++) {
1803 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1804 udelay(10);
1805 }
1806
1807 if (dev->fw.pcm.data) {
1808 /* Upload PCM data. */
1809 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1810 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1811 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1812 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1813 /* No need for autoinc bit in SHM_HW */
1814 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1815 for (i = 0; i < len; i++) {
1816 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1817 udelay(10);
1818 }
1819 }
1820
1821 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1822
1823 /* Start the microcode PSM */
1824 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1825 macctl &= ~B43_MACCTL_PSM_JMP0;
1826 macctl |= B43_MACCTL_PSM_RUN;
1827 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1828
1829 /* Wait for the microcode to load and respond */
1830 i = 0;
1831 while (1) {
1832 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1833 if (tmp == B43_IRQ_MAC_SUSPENDED)
1834 break;
1835 i++;
1836 if (i >= 20) {
1837 b43err(dev->wl, "Microcode not responding\n");
1838 b43_print_fw_helptext(dev->wl, 1);
1839 err = -ENODEV;
1840 goto error;
1841 }
1842 msleep_interruptible(50);
1843 if (signal_pending(current)) {
1844 err = -EINTR;
1845 goto error;
1846 }
1847 }
1848 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1849
1850 /* Get and check the revisions. */
1851 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1852 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1853 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1854 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1855
1856 if (fwrev <= 0x128) {
1857 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1858 "binary drivers older than version 4.x is unsupported. "
1859 "You must upgrade your firmware files.\n");
1860 b43_print_fw_helptext(dev->wl, 1);
1861 err = -EOPNOTSUPP;
1862 goto error;
1863 }
1864 b43info(dev->wl, "Loading firmware version %u.%u "
1865 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1866 fwrev, fwpatch,
1867 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1868 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1869
1870 dev->fw.rev = fwrev;
1871 dev->fw.patch = fwpatch;
1872
1873 if (b43_is_old_txhdr_format(dev)) {
1874 b43warn(dev->wl, "You are using an old firmware image. "
1875 "Support for old firmware will be removed in July 2008.\n");
1876 b43_print_fw_helptext(dev->wl, 0);
1877 }
1878
1879 return 0;
1880
1881 error:
1882 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1883 macctl &= ~B43_MACCTL_PSM_RUN;
1884 macctl |= B43_MACCTL_PSM_JMP0;
1885 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1886
1887 return err;
1888 }
1889
1890 static int b43_write_initvals(struct b43_wldev *dev,
1891 const struct b43_iv *ivals,
1892 size_t count,
1893 size_t array_size)
1894 {
1895 const struct b43_iv *iv;
1896 u16 offset;
1897 size_t i;
1898 bool bit32;
1899
1900 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1901 iv = ivals;
1902 for (i = 0; i < count; i++) {
1903 if (array_size < sizeof(iv->offset_size))
1904 goto err_format;
1905 array_size -= sizeof(iv->offset_size);
1906 offset = be16_to_cpu(iv->offset_size);
1907 bit32 = !!(offset & B43_IV_32BIT);
1908 offset &= B43_IV_OFFSET_MASK;
1909 if (offset >= 0x1000)
1910 goto err_format;
1911 if (bit32) {
1912 u32 value;
1913
1914 if (array_size < sizeof(iv->data.d32))
1915 goto err_format;
1916 array_size -= sizeof(iv->data.d32);
1917
1918 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1919 b43_write32(dev, offset, value);
1920
1921 iv = (const struct b43_iv *)((const uint8_t *)iv +
1922 sizeof(__be16) +
1923 sizeof(__be32));
1924 } else {
1925 u16 value;
1926
1927 if (array_size < sizeof(iv->data.d16))
1928 goto err_format;
1929 array_size -= sizeof(iv->data.d16);
1930
1931 value = be16_to_cpu(iv->data.d16);
1932 b43_write16(dev, offset, value);
1933
1934 iv = (const struct b43_iv *)((const uint8_t *)iv +
1935 sizeof(__be16) +
1936 sizeof(__be16));
1937 }
1938 }
1939 if (array_size)
1940 goto err_format;
1941
1942 return 0;
1943
1944 err_format:
1945 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1946 b43_print_fw_helptext(dev->wl, 1);
1947
1948 return -EPROTO;
1949 }
1950
1951 static int b43_upload_initvals(struct b43_wldev *dev)
1952 {
1953 const size_t hdr_len = sizeof(struct b43_fw_header);
1954 const struct b43_fw_header *hdr;
1955 struct b43_firmware *fw = &dev->fw;
1956 const struct b43_iv *ivals;
1957 size_t count;
1958 int err;
1959
1960 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1961 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1962 count = be32_to_cpu(hdr->size);
1963 err = b43_write_initvals(dev, ivals, count,
1964 fw->initvals.data->size - hdr_len);
1965 if (err)
1966 goto out;
1967 if (fw->initvals_band.data) {
1968 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1969 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1970 count = be32_to_cpu(hdr->size);
1971 err = b43_write_initvals(dev, ivals, count,
1972 fw->initvals_band.data->size - hdr_len);
1973 if (err)
1974 goto out;
1975 }
1976 out:
1977
1978 return err;
1979 }
1980
1981 /* Initialize the GPIOs
1982 * http://bcm-specs.sipsolutions.net/GPIO
1983 */
1984 static int b43_gpio_init(struct b43_wldev *dev)
1985 {
1986 struct ssb_bus *bus = dev->dev->bus;
1987 struct ssb_device *gpiodev, *pcidev = NULL;
1988 u32 mask, set;
1989
1990 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1991 & ~B43_MACCTL_GPOUTSMSK);
1992
1993 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1994 | 0x000F);
1995
1996 mask = 0x0000001F;
1997 set = 0x0000000F;
1998 if (dev->dev->bus->chip_id == 0x4301) {
1999 mask |= 0x0060;
2000 set |= 0x0060;
2001 }
2002 if (0 /* FIXME: conditional unknown */ ) {
2003 b43_write16(dev, B43_MMIO_GPIO_MASK,
2004 b43_read16(dev, B43_MMIO_GPIO_MASK)
2005 | 0x0100);
2006 mask |= 0x0180;
2007 set |= 0x0180;
2008 }
2009 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2010 b43_write16(dev, B43_MMIO_GPIO_MASK,
2011 b43_read16(dev, B43_MMIO_GPIO_MASK)
2012 | 0x0200);
2013 mask |= 0x0200;
2014 set |= 0x0200;
2015 }
2016 if (dev->dev->id.revision >= 2)
2017 mask |= 0x0010; /* FIXME: This is redundant. */
2018
2019 #ifdef CONFIG_SSB_DRIVER_PCICORE
2020 pcidev = bus->pcicore.dev;
2021 #endif
2022 gpiodev = bus->chipco.dev ? : pcidev;
2023 if (!gpiodev)
2024 return 0;
2025 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2026 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2027 & mask) | set);
2028
2029 return 0;
2030 }
2031
2032 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2033 static void b43_gpio_cleanup(struct b43_wldev *dev)
2034 {
2035 struct ssb_bus *bus = dev->dev->bus;
2036 struct ssb_device *gpiodev, *pcidev = NULL;
2037
2038 #ifdef CONFIG_SSB_DRIVER_PCICORE
2039 pcidev = bus->pcicore.dev;
2040 #endif
2041 gpiodev = bus->chipco.dev ? : pcidev;
2042 if (!gpiodev)
2043 return;
2044 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2045 }
2046
2047 /* http://bcm-specs.sipsolutions.net/EnableMac */
2048 void b43_mac_enable(struct b43_wldev *dev)
2049 {
2050 dev->mac_suspended--;
2051 B43_WARN_ON(dev->mac_suspended < 0);
2052 B43_WARN_ON(irqs_disabled());
2053 if (dev->mac_suspended == 0) {
2054 b43_write32(dev, B43_MMIO_MACCTL,
2055 b43_read32(dev, B43_MMIO_MACCTL)
2056 | B43_MACCTL_ENABLED);
2057 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2058 B43_IRQ_MAC_SUSPENDED);
2059 /* Commit writes */
2060 b43_read32(dev, B43_MMIO_MACCTL);
2061 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2062 b43_power_saving_ctl_bits(dev, 0);
2063
2064 /* Re-enable IRQs. */
2065 spin_lock_irq(&dev->wl->irq_lock);
2066 b43_interrupt_enable(dev, dev->irq_savedstate);
2067 spin_unlock_irq(&dev->wl->irq_lock);
2068 }
2069 }
2070
2071 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2072 void b43_mac_suspend(struct b43_wldev *dev)
2073 {
2074 int i;
2075 u32 tmp;
2076
2077 might_sleep();
2078 B43_WARN_ON(irqs_disabled());
2079 B43_WARN_ON(dev->mac_suspended < 0);
2080
2081 if (dev->mac_suspended == 0) {
2082 /* Mask IRQs before suspending MAC. Otherwise
2083 * the MAC stays busy and won't suspend. */
2084 spin_lock_irq(&dev->wl->irq_lock);
2085 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2086 spin_unlock_irq(&dev->wl->irq_lock);
2087 b43_synchronize_irq(dev);
2088 dev->irq_savedstate = tmp;
2089
2090 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2091 b43_write32(dev, B43_MMIO_MACCTL,
2092 b43_read32(dev, B43_MMIO_MACCTL)
2093 & ~B43_MACCTL_ENABLED);
2094 /* force pci to flush the write */
2095 b43_read32(dev, B43_MMIO_MACCTL);
2096 for (i = 40; i; i--) {
2097 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2098 if (tmp & B43_IRQ_MAC_SUSPENDED)
2099 goto out;
2100 msleep(1);
2101 }
2102 b43err(dev->wl, "MAC suspend failed\n");
2103 }
2104 out:
2105 dev->mac_suspended++;
2106 }
2107
2108 static void b43_adjust_opmode(struct b43_wldev *dev)
2109 {
2110 struct b43_wl *wl = dev->wl;
2111 u32 ctl;
2112 u16 cfp_pretbtt;
2113
2114 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2115 /* Reset status to STA infrastructure mode. */
2116 ctl &= ~B43_MACCTL_AP;
2117 ctl &= ~B43_MACCTL_KEEP_CTL;
2118 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2119 ctl &= ~B43_MACCTL_KEEP_BAD;
2120 ctl &= ~B43_MACCTL_PROMISC;
2121 ctl &= ~B43_MACCTL_BEACPROMISC;
2122 ctl |= B43_MACCTL_INFRA;
2123
2124 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2125 ctl |= B43_MACCTL_AP;
2126 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2127 ctl &= ~B43_MACCTL_INFRA;
2128
2129 if (wl->filter_flags & FIF_CONTROL)
2130 ctl |= B43_MACCTL_KEEP_CTL;
2131 if (wl->filter_flags & FIF_FCSFAIL)
2132 ctl |= B43_MACCTL_KEEP_BAD;
2133 if (wl->filter_flags & FIF_PLCPFAIL)
2134 ctl |= B43_MACCTL_KEEP_BADPLCP;
2135 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2136 ctl |= B43_MACCTL_PROMISC;
2137 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2138 ctl |= B43_MACCTL_BEACPROMISC;
2139
2140 /* Workaround: On old hardware the HW-MAC-address-filter
2141 * doesn't work properly, so always run promisc in filter
2142 * it in software. */
2143 if (dev->dev->id.revision <= 4)
2144 ctl |= B43_MACCTL_PROMISC;
2145
2146 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2147
2148 cfp_pretbtt = 2;
2149 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2150 if (dev->dev->bus->chip_id == 0x4306 &&
2151 dev->dev->bus->chip_rev == 3)
2152 cfp_pretbtt = 100;
2153 else
2154 cfp_pretbtt = 50;
2155 }
2156 b43_write16(dev, 0x612, cfp_pretbtt);
2157 }
2158
2159 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2160 {
2161 u16 offset;
2162
2163 if (is_ofdm) {
2164 offset = 0x480;
2165 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2166 } else {
2167 offset = 0x4C0;
2168 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2169 }
2170 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2171 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2172 }
2173
2174 static void b43_rate_memory_init(struct b43_wldev *dev)
2175 {
2176 switch (dev->phy.type) {
2177 case B43_PHYTYPE_A:
2178 case B43_PHYTYPE_G:
2179 case B43_PHYTYPE_N:
2180 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2181 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2182 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2183 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2184 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2185 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2186 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2187 if (dev->phy.type == B43_PHYTYPE_A)
2188 break;
2189 /* fallthrough */
2190 case B43_PHYTYPE_B:
2191 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2192 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2193 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2194 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2195 break;
2196 default:
2197 B43_WARN_ON(1);
2198 }
2199 }
2200
2201 /* Set the TX-Antenna for management frames sent by firmware. */
2202 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2203 {
2204 u16 ant = 0;
2205 u16 tmp;
2206
2207 switch (antenna) {
2208 case B43_ANTENNA0:
2209 ant |= B43_TXH_PHY_ANT0;
2210 break;
2211 case B43_ANTENNA1:
2212 ant |= B43_TXH_PHY_ANT1;
2213 break;
2214 case B43_ANTENNA2:
2215 ant |= B43_TXH_PHY_ANT2;
2216 break;
2217 case B43_ANTENNA3:
2218 ant |= B43_TXH_PHY_ANT3;
2219 break;
2220 case B43_ANTENNA_AUTO:
2221 ant |= B43_TXH_PHY_ANT01AUTO;
2222 break;
2223 default:
2224 B43_WARN_ON(1);
2225 }
2226
2227 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2228
2229 /* For Beacons */
2230 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2231 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2232 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2233 /* For ACK/CTS */
2234 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2235 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2236 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2237 /* For Probe Resposes */
2238 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2239 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2240 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2241 }
2242
2243 /* This is the opposite of b43_chip_init() */
2244 static void b43_chip_exit(struct b43_wldev *dev)
2245 {
2246 b43_radio_turn_off(dev, 1);
2247 b43_gpio_cleanup(dev);
2248 /* firmware is released later */
2249 }
2250
2251 /* Initialize the chip
2252 * http://bcm-specs.sipsolutions.net/ChipInit
2253 */
2254 static int b43_chip_init(struct b43_wldev *dev)
2255 {
2256 struct b43_phy *phy = &dev->phy;
2257 int err, tmp;
2258 u32 value32, macctl;
2259 u16 value16;
2260
2261 /* Initialize the MAC control */
2262 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2263 if (dev->phy.gmode)
2264 macctl |= B43_MACCTL_GMODE;
2265 macctl |= B43_MACCTL_INFRA;
2266 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2267
2268 err = b43_request_firmware(dev);
2269 if (err)
2270 goto out;
2271 err = b43_upload_microcode(dev);
2272 if (err)
2273 goto out; /* firmware is released later */
2274
2275 err = b43_gpio_init(dev);
2276 if (err)
2277 goto out; /* firmware is released later */
2278
2279 err = b43_upload_initvals(dev);
2280 if (err)
2281 goto err_gpio_clean;
2282 b43_radio_turn_on(dev);
2283
2284 b43_write16(dev, 0x03E6, 0x0000);
2285 err = b43_phy_init(dev);
2286 if (err)
2287 goto err_radio_off;
2288
2289 /* Select initial Interference Mitigation. */
2290 tmp = phy->interfmode;
2291 phy->interfmode = B43_INTERFMODE_NONE;
2292 b43_radio_set_interference_mitigation(dev, tmp);
2293
2294 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2295 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2296
2297 if (phy->type == B43_PHYTYPE_B) {
2298 value16 = b43_read16(dev, 0x005E);
2299 value16 |= 0x0004;
2300 b43_write16(dev, 0x005E, value16);
2301 }
2302 b43_write32(dev, 0x0100, 0x01000000);
2303 if (dev->dev->id.revision < 5)
2304 b43_write32(dev, 0x010C, 0x01000000);
2305
2306 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2307 & ~B43_MACCTL_INFRA);
2308 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2309 | B43_MACCTL_INFRA);
2310
2311 /* Probe Response Timeout value */
2312 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2313 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2314
2315 /* Initially set the wireless operation mode. */
2316 b43_adjust_opmode(dev);
2317
2318 if (dev->dev->id.revision < 3) {
2319 b43_write16(dev, 0x060E, 0x0000);
2320 b43_write16(dev, 0x0610, 0x8000);
2321 b43_write16(dev, 0x0604, 0x0000);
2322 b43_write16(dev, 0x0606, 0x0200);
2323 } else {
2324 b43_write32(dev, 0x0188, 0x80000000);
2325 b43_write32(dev, 0x018C, 0x02000000);
2326 }
2327 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2328 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2329 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2330 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2331 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2332 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2333 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2334
2335 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2336 value32 |= 0x00100000;
2337 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2338
2339 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2340 dev->dev->bus->chipco.fast_pwrup_delay);
2341
2342 err = 0;
2343 b43dbg(dev->wl, "Chip initialized\n");
2344 out:
2345 return err;
2346
2347 err_radio_off:
2348 b43_radio_turn_off(dev, 1);
2349 err_gpio_clean:
2350 b43_gpio_cleanup(dev);
2351 return err;
2352 }
2353
2354 static void b43_periodic_every120sec(struct b43_wldev *dev)
2355 {
2356 struct b43_phy *phy = &dev->phy;
2357
2358 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2359 return;
2360
2361 b43_mac_suspend(dev);
2362 b43_lo_g_measure(dev);
2363 b43_mac_enable(dev);
2364 if (b43_has_hardware_pctl(phy))
2365 b43_lo_g_ctl_mark_all_unused(dev);
2366 }
2367
2368 static void b43_periodic_every60sec(struct b43_wldev *dev)
2369 {
2370 struct b43_phy *phy = &dev->phy;
2371
2372 if (phy->type != B43_PHYTYPE_G)
2373 return;
2374 if (!b43_has_hardware_pctl(phy))
2375 b43_lo_g_ctl_mark_all_unused(dev);
2376 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2377 b43_mac_suspend(dev);
2378 b43_calc_nrssi_slope(dev);
2379 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2380 u8 old_chan = phy->channel;
2381
2382 /* VCO Calibration */
2383 if (old_chan >= 8)
2384 b43_radio_selectchannel(dev, 1, 0);
2385 else
2386 b43_radio_selectchannel(dev, 13, 0);
2387 b43_radio_selectchannel(dev, old_chan, 0);
2388 }
2389 b43_mac_enable(dev);
2390 }
2391 }
2392
2393 static void b43_periodic_every30sec(struct b43_wldev *dev)
2394 {
2395 /* Update device statistics. */
2396 b43_calculate_link_quality(dev);
2397 }
2398
2399 static void b43_periodic_every15sec(struct b43_wldev *dev)
2400 {
2401 struct b43_phy *phy = &dev->phy;
2402
2403 if (phy->type == B43_PHYTYPE_G) {
2404 //TODO: update_aci_moving_average
2405 if (phy->aci_enable && phy->aci_wlan_automatic) {
2406 b43_mac_suspend(dev);
2407 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2408 if (0 /*TODO: bunch of conditions */ ) {
2409 b43_radio_set_interference_mitigation
2410 (dev, B43_INTERFMODE_MANUALWLAN);
2411 }
2412 } else if (1 /*TODO*/) {
2413 /*
2414 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2415 b43_radio_set_interference_mitigation(dev,
2416 B43_INTERFMODE_NONE);
2417 }
2418 */
2419 }
2420 b43_mac_enable(dev);
2421 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2422 phy->rev == 1) {
2423 //TODO: implement rev1 workaround
2424 }
2425 }
2426 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2427 //TODO for APHY (temperature?)
2428
2429 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2430 wmb();
2431 }
2432
2433 static void do_periodic_work(struct b43_wldev *dev)
2434 {
2435 unsigned int state;
2436
2437 state = dev->periodic_state;
2438 if (state % 8 == 0)
2439 b43_periodic_every120sec(dev);
2440 if (state % 4 == 0)
2441 b43_periodic_every60sec(dev);
2442 if (state % 2 == 0)
2443 b43_periodic_every30sec(dev);
2444 b43_periodic_every15sec(dev);
2445 }
2446
2447 /* Periodic work locking policy:
2448 * The whole periodic work handler is protected by
2449 * wl->mutex. If another lock is needed somewhere in the
2450 * pwork callchain, it's aquired in-place, where it's needed.
2451 */
2452 static void b43_periodic_work_handler(struct work_struct *work)
2453 {
2454 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2455 periodic_work.work);
2456 struct b43_wl *wl = dev->wl;
2457 unsigned long delay;
2458
2459 mutex_lock(&wl->mutex);
2460
2461 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2462 goto out;
2463 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2464 goto out_requeue;
2465
2466 do_periodic_work(dev);
2467
2468 dev->periodic_state++;
2469 out_requeue:
2470 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2471 delay = msecs_to_jiffies(50);
2472 else
2473 delay = round_jiffies_relative(HZ * 15);
2474 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2475 out:
2476 mutex_unlock(&wl->mutex);
2477 }
2478
2479 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2480 {
2481 struct delayed_work *work = &dev->periodic_work;
2482
2483 dev->periodic_state = 0;
2484 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2485 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2486 }
2487
2488 /* Check if communication with the device works correctly. */
2489 static int b43_validate_chipaccess(struct b43_wldev *dev)
2490 {
2491 u32 v, backup;
2492
2493 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2494
2495 /* Check for read/write and endianness problems. */
2496 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2497 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2498 goto error;
2499 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2500 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2501 goto error;
2502
2503 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2504
2505 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2506 /* The 32bit register shadows the two 16bit registers
2507 * with update sideeffects. Validate this. */
2508 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2509 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2510 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2511 goto error;
2512 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2513 goto error;
2514 }
2515 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2516
2517 v = b43_read32(dev, B43_MMIO_MACCTL);
2518 v |= B43_MACCTL_GMODE;
2519 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2520 goto error;
2521
2522 return 0;
2523 error:
2524 b43err(dev->wl, "Failed to validate the chipaccess\n");
2525 return -ENODEV;
2526 }
2527
2528 static void b43_security_init(struct b43_wldev *dev)
2529 {
2530 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2531 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2532 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2533 /* KTP is a word address, but we address SHM bytewise.
2534 * So multiply by two.
2535 */
2536 dev->ktp *= 2;
2537 if (dev->dev->id.revision >= 5) {
2538 /* Number of RCMTA address slots */
2539 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2540 }
2541 b43_clear_keys(dev);
2542 }
2543
2544 static int b43_rng_read(struct hwrng *rng, u32 * data)
2545 {
2546 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2547 unsigned long flags;
2548
2549 /* Don't take wl->mutex here, as it could deadlock with
2550 * hwrng internal locking. It's not needed to take
2551 * wl->mutex here, anyway. */
2552
2553 spin_lock_irqsave(&wl->irq_lock, flags);
2554 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2555 spin_unlock_irqrestore(&wl->irq_lock, flags);
2556
2557 return (sizeof(u16));
2558 }
2559
2560 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2561 {
2562 if (wl->rng_initialized)
2563 __hwrng_unregister(&wl->rng, suspended);
2564 }
2565
2566 static int b43_rng_init(struct b43_wl *wl)
2567 {
2568 int err;
2569
2570 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2571 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2572 wl->rng.name = wl->rng_name;
2573 wl->rng.data_read = b43_rng_read;
2574 wl->rng.priv = (unsigned long)wl;
2575 wl->rng_initialized = 1;
2576 err = hwrng_register(&wl->rng);
2577 if (err) {
2578 wl->rng_initialized = 0;
2579 b43err(wl, "Failed to register the random "
2580 "number generator (%d)\n", err);
2581 }
2582
2583 return err;
2584 }
2585
2586 static int b43_op_tx(struct ieee80211_hw *hw,
2587 struct sk_buff *skb,
2588 struct ieee80211_tx_control *ctl)
2589 {
2590 struct b43_wl *wl = hw_to_b43_wl(hw);
2591 struct b43_wldev *dev = wl->current_dev;
2592 int err = -ENODEV;
2593
2594 if (unlikely(!dev))
2595 goto out;
2596 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2597 goto out;
2598 /* DMA-TX is done without a global lock. */
2599 err = b43_dma_tx(dev, skb, ctl);
2600 out:
2601 if (unlikely(err))
2602 return NETDEV_TX_BUSY;
2603 return NETDEV_TX_OK;
2604 }
2605
2606 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2607 int queue,
2608 const struct ieee80211_tx_queue_params *params)
2609 {
2610 return 0;
2611 }
2612
2613 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2614 struct ieee80211_tx_queue_stats *stats)
2615 {
2616 struct b43_wl *wl = hw_to_b43_wl(hw);
2617 struct b43_wldev *dev = wl->current_dev;
2618 unsigned long flags;
2619 int err = -ENODEV;
2620
2621 if (!dev)
2622 goto out;
2623 spin_lock_irqsave(&wl->irq_lock, flags);
2624 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2625 b43_dma_get_tx_stats(dev, stats);
2626 err = 0;
2627 }
2628 spin_unlock_irqrestore(&wl->irq_lock, flags);
2629 out:
2630 return err;
2631 }
2632
2633 static int b43_op_get_stats(struct ieee80211_hw *hw,
2634 struct ieee80211_low_level_stats *stats)
2635 {
2636 struct b43_wl *wl = hw_to_b43_wl(hw);
2637 unsigned long flags;
2638
2639 spin_lock_irqsave(&wl->irq_lock, flags);
2640 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2641 spin_unlock_irqrestore(&wl->irq_lock, flags);
2642
2643 return 0;
2644 }
2645
2646 static const char *phymode_to_string(unsigned int phymode)
2647 {
2648 switch (phymode) {
2649 case B43_PHYMODE_A:
2650 return "A";
2651 case B43_PHYMODE_B:
2652 return "B";
2653 case B43_PHYMODE_G:
2654 return "G";
2655 default:
2656 B43_WARN_ON(1);
2657 }
2658 return "";
2659 }
2660
2661 static int find_wldev_for_phymode(struct b43_wl *wl,
2662 unsigned int phymode,
2663 struct b43_wldev **dev, bool * gmode)
2664 {
2665 struct b43_wldev *d;
2666
2667 list_for_each_entry(d, &wl->devlist, list) {
2668 if (d->phy.possible_phymodes & phymode) {
2669 /* Ok, this device supports the PHY-mode.
2670 * Now figure out how the gmode bit has to be
2671 * set to support it. */
2672 if (phymode == B43_PHYMODE_A)
2673 *gmode = 0;
2674 else
2675 *gmode = 1;
2676 *dev = d;
2677
2678 return 0;
2679 }
2680 }
2681
2682 return -ESRCH;
2683 }
2684
2685 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2686 {
2687 struct ssb_device *sdev = dev->dev;
2688 u32 tmslow;
2689
2690 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2691 tmslow &= ~B43_TMSLOW_GMODE;
2692 tmslow |= B43_TMSLOW_PHYRESET;
2693 tmslow |= SSB_TMSLOW_FGC;
2694 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2695 msleep(1);
2696
2697 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2698 tmslow &= ~SSB_TMSLOW_FGC;
2699 tmslow |= B43_TMSLOW_PHYRESET;
2700 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2701 msleep(1);
2702 }
2703
2704 /* Expects wl->mutex locked */
2705 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2706 {
2707 struct b43_wldev *up_dev;
2708 struct b43_wldev *down_dev;
2709 int err;
2710 bool gmode = 0;
2711 int prev_status;
2712
2713 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2714 if (err) {
2715 b43err(wl, "Could not find a device for %s-PHY mode\n",
2716 phymode_to_string(new_mode));
2717 return err;
2718 }
2719 if ((up_dev == wl->current_dev) &&
2720 (!!wl->current_dev->phy.gmode == !!gmode)) {
2721 /* This device is already running. */
2722 return 0;
2723 }
2724 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2725 phymode_to_string(new_mode));
2726 down_dev = wl->current_dev;
2727
2728 prev_status = b43_status(down_dev);
2729 /* Shutdown the currently running core. */
2730 if (prev_status >= B43_STAT_STARTED)
2731 b43_wireless_core_stop(down_dev);
2732 if (prev_status >= B43_STAT_INITIALIZED)
2733 b43_wireless_core_exit(down_dev);
2734
2735 if (down_dev != up_dev) {
2736 /* We switch to a different core, so we put PHY into
2737 * RESET on the old core. */
2738 b43_put_phy_into_reset(down_dev);
2739 }
2740
2741 /* Now start the new core. */
2742 up_dev->phy.gmode = gmode;
2743 if (prev_status >= B43_STAT_INITIALIZED) {
2744 err = b43_wireless_core_init(up_dev);
2745 if (err) {
2746 b43err(wl, "Fatal: Could not initialize device for "
2747 "newly selected %s-PHY mode\n",
2748 phymode_to_string(new_mode));
2749 goto init_failure;
2750 }
2751 }
2752 if (prev_status >= B43_STAT_STARTED) {
2753 err = b43_wireless_core_start(up_dev);
2754 if (err) {
2755 b43err(wl, "Fatal: Coult not start device for "
2756 "newly selected %s-PHY mode\n",
2757 phymode_to_string(new_mode));
2758 b43_wireless_core_exit(up_dev);
2759 goto init_failure;
2760 }
2761 }
2762 B43_WARN_ON(b43_status(up_dev) != prev_status);
2763
2764 wl->current_dev = up_dev;
2765
2766 return 0;
2767 init_failure:
2768 /* Whoops, failed to init the new core. No core is operating now. */
2769 wl->current_dev = NULL;
2770 return err;
2771 }
2772
2773 /* Check if the use of the antenna that ieee80211 told us to
2774 * use is possible. This will fall back to DEFAULT.
2775 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2776 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2777 u8 antenna_nr)
2778 {
2779 u8 antenna_mask;
2780
2781 if (antenna_nr == 0) {
2782 /* Zero means "use default antenna". That's always OK. */
2783 return 0;
2784 }
2785
2786 /* Get the mask of available antennas. */
2787 if (dev->phy.gmode)
2788 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2789 else
2790 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2791
2792 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2793 /* This antenna is not available. Fall back to default. */
2794 return 0;
2795 }
2796
2797 return antenna_nr;
2798 }
2799
2800 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2801 {
2802 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2803 switch (antenna) {
2804 case 0: /* default/diversity */
2805 return B43_ANTENNA_DEFAULT;
2806 case 1: /* Antenna 0 */
2807 return B43_ANTENNA0;
2808 case 2: /* Antenna 1 */
2809 return B43_ANTENNA1;
2810 case 3: /* Antenna 2 */
2811 return B43_ANTENNA2;
2812 case 4: /* Antenna 3 */
2813 return B43_ANTENNA3;
2814 default:
2815 return B43_ANTENNA_DEFAULT;
2816 }
2817 }
2818
2819 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2820 {
2821 struct b43_wl *wl = hw_to_b43_wl(hw);
2822 struct b43_wldev *dev;
2823 struct b43_phy *phy;
2824 unsigned long flags;
2825 unsigned int new_phymode = 0xFFFF;
2826 int antenna;
2827 int err = 0;
2828 u32 savedirqs;
2829
2830 mutex_lock(&wl->mutex);
2831
2832 /* Switch the PHY mode (if necessary). */
2833 switch (conf->phymode) {
2834 case MODE_IEEE80211A:
2835 new_phymode = B43_PHYMODE_A;
2836 break;
2837 case MODE_IEEE80211B:
2838 new_phymode = B43_PHYMODE_B;
2839 break;
2840 case MODE_IEEE80211G:
2841 new_phymode = B43_PHYMODE_G;
2842 break;
2843 default:
2844 B43_WARN_ON(1);
2845 }
2846 err = b43_switch_phymode(wl, new_phymode);
2847 if (err)
2848 goto out_unlock_mutex;
2849 dev = wl->current_dev;
2850 phy = &dev->phy;
2851
2852 /* Disable IRQs while reconfiguring the device.
2853 * This makes it possible to drop the spinlock throughout
2854 * the reconfiguration process. */
2855 spin_lock_irqsave(&wl->irq_lock, flags);
2856 if (b43_status(dev) < B43_STAT_STARTED) {
2857 spin_unlock_irqrestore(&wl->irq_lock, flags);
2858 goto out_unlock_mutex;
2859 }
2860 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2861 spin_unlock_irqrestore(&wl->irq_lock, flags);
2862 b43_synchronize_irq(dev);
2863
2864 /* Switch to the requested channel.
2865 * The firmware takes care of races with the TX handler. */
2866 if (conf->channel_val != phy->channel)
2867 b43_radio_selectchannel(dev, conf->channel_val, 0);
2868
2869 /* Enable/Disable ShortSlot timing. */
2870 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2871 dev->short_slot) {
2872 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2873 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2874 b43_short_slot_timing_enable(dev);
2875 else
2876 b43_short_slot_timing_disable(dev);
2877 }
2878
2879 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2880
2881 /* Adjust the desired TX power level. */
2882 if (conf->power_level != 0) {
2883 if (conf->power_level != phy->power_level) {
2884 phy->power_level = conf->power_level;
2885 b43_phy_xmitpower(dev);
2886 }
2887 }
2888
2889 /* Antennas for RX and management frame TX. */
2890 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2891 b43_mgmtframe_txantenna(dev, antenna);
2892 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2893 b43_set_rx_antenna(dev, antenna);
2894
2895 /* Update templates for AP mode. */
2896 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2897 b43_set_beacon_int(dev, conf->beacon_int);
2898
2899 if (!!conf->radio_enabled != phy->radio_on) {
2900 if (conf->radio_enabled) {
2901 b43_radio_turn_on(dev);
2902 b43info(dev->wl, "Radio turned on by software\n");
2903 if (!dev->radio_hw_enable) {
2904 b43info(dev->wl, "The hardware RF-kill button "
2905 "still turns the radio physically off. "
2906 "Press the button to turn it on.\n");
2907 }
2908 } else {
2909 b43_radio_turn_off(dev, 0);
2910 b43info(dev->wl, "Radio turned off by software\n");
2911 }
2912 }
2913
2914 spin_lock_irqsave(&wl->irq_lock, flags);
2915 b43_interrupt_enable(dev, savedirqs);
2916 mmiowb();
2917 spin_unlock_irqrestore(&wl->irq_lock, flags);
2918 out_unlock_mutex:
2919 mutex_unlock(&wl->mutex);
2920
2921 return err;
2922 }
2923
2924 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2925 const u8 *local_addr, const u8 *addr,
2926 struct ieee80211_key_conf *key)
2927 {
2928 struct b43_wl *wl = hw_to_b43_wl(hw);
2929 struct b43_wldev *dev;
2930 unsigned long flags;
2931 u8 algorithm;
2932 u8 index;
2933 int err;
2934 DECLARE_MAC_BUF(mac);
2935
2936 if (modparam_nohwcrypt)
2937 return -ENOSPC; /* User disabled HW-crypto */
2938
2939 mutex_lock(&wl->mutex);
2940 spin_lock_irqsave(&wl->irq_lock, flags);
2941
2942 dev = wl->current_dev;
2943 err = -ENODEV;
2944 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2945 goto out_unlock;
2946
2947 err = -EINVAL;
2948 switch (key->alg) {
2949 case ALG_WEP:
2950 if (key->keylen == 5)
2951 algorithm = B43_SEC_ALGO_WEP40;
2952 else
2953 algorithm = B43_SEC_ALGO_WEP104;
2954 break;
2955 case ALG_TKIP:
2956 algorithm = B43_SEC_ALGO_TKIP;
2957 break;
2958 case ALG_CCMP:
2959 algorithm = B43_SEC_ALGO_AES;
2960 break;
2961 default:
2962 B43_WARN_ON(1);
2963 goto out_unlock;
2964 }
2965 index = (u8) (key->keyidx);
2966 if (index > 3)
2967 goto out_unlock;
2968
2969 switch (cmd) {
2970 case SET_KEY:
2971 if (algorithm == B43_SEC_ALGO_TKIP) {
2972 /* FIXME: No TKIP hardware encryption for now. */
2973 err = -EOPNOTSUPP;
2974 goto out_unlock;
2975 }
2976
2977 if (is_broadcast_ether_addr(addr)) {
2978 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2979 err = b43_key_write(dev, index, algorithm,
2980 key->key, key->keylen, NULL, key);
2981 } else {
2982 /*
2983 * either pairwise key or address is 00:00:00:00:00:00
2984 * for transmit-only keys
2985 */
2986 err = b43_key_write(dev, -1, algorithm,
2987 key->key, key->keylen, addr, key);
2988 }
2989 if (err)
2990 goto out_unlock;
2991
2992 if (algorithm == B43_SEC_ALGO_WEP40 ||
2993 algorithm == B43_SEC_ALGO_WEP104) {
2994 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2995 } else {
2996 b43_hf_write(dev,
2997 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2998 }
2999 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3000 break;
3001 case DISABLE_KEY: {
3002 err = b43_key_clear(dev, key->hw_key_idx);
3003 if (err)
3004 goto out_unlock;
3005 break;
3006 }
3007 default:
3008 B43_WARN_ON(1);
3009 }
3010 out_unlock:
3011 spin_unlock_irqrestore(&wl->irq_lock, flags);
3012 mutex_unlock(&wl->mutex);
3013 if (!err) {
3014 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3015 "mac: %s\n",
3016 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3017 print_mac(mac, addr));
3018 }
3019 return err;
3020 }
3021
3022 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3023 unsigned int changed, unsigned int *fflags,
3024 int mc_count, struct dev_addr_list *mc_list)
3025 {
3026 struct b43_wl *wl = hw_to_b43_wl(hw);
3027 struct b43_wldev *dev = wl->current_dev;
3028 unsigned long flags;
3029
3030 if (!dev) {
3031 *fflags = 0;
3032 return;
3033 }
3034
3035 spin_lock_irqsave(&wl->irq_lock, flags);
3036 *fflags &= FIF_PROMISC_IN_BSS |
3037 FIF_ALLMULTI |
3038 FIF_FCSFAIL |
3039 FIF_PLCPFAIL |
3040 FIF_CONTROL |
3041 FIF_OTHER_BSS |
3042 FIF_BCN_PRBRESP_PROMISC;
3043
3044 changed &= FIF_PROMISC_IN_BSS |
3045 FIF_ALLMULTI |
3046 FIF_FCSFAIL |
3047 FIF_PLCPFAIL |
3048 FIF_CONTROL |
3049 FIF_OTHER_BSS |
3050 FIF_BCN_PRBRESP_PROMISC;
3051
3052 wl->filter_flags = *fflags;
3053
3054 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3055 b43_adjust_opmode(dev);
3056 spin_unlock_irqrestore(&wl->irq_lock, flags);
3057 }
3058
3059 static int b43_op_config_interface(struct ieee80211_hw *hw,
3060 struct ieee80211_vif *vif,
3061 struct ieee80211_if_conf *conf)
3062 {
3063 struct b43_wl *wl = hw_to_b43_wl(hw);
3064 struct b43_wldev *dev = wl->current_dev;
3065 unsigned long flags;
3066
3067 if (!dev)
3068 return -ENODEV;
3069 mutex_lock(&wl->mutex);
3070 spin_lock_irqsave(&wl->irq_lock, flags);
3071 B43_WARN_ON(wl->vif != vif);
3072 if (conf->bssid)
3073 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3074 else
3075 memset(wl->bssid, 0, ETH_ALEN);
3076 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3077 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3078 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3079 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3080 if (conf->beacon)
3081 b43_update_templates(wl, conf->beacon);
3082 }
3083 b43_write_mac_bssid_templates(dev);
3084 }
3085 spin_unlock_irqrestore(&wl->irq_lock, flags);
3086 mutex_unlock(&wl->mutex);
3087
3088 return 0;
3089 }
3090
3091 /* Locking: wl->mutex */
3092 static void b43_wireless_core_stop(struct b43_wldev *dev)
3093 {
3094 struct b43_wl *wl = dev->wl;
3095 unsigned long flags;
3096
3097 if (b43_status(dev) < B43_STAT_STARTED)
3098 return;
3099
3100 /* Disable and sync interrupts. We must do this before than
3101 * setting the status to INITIALIZED, as the interrupt handler
3102 * won't care about IRQs then. */
3103 spin_lock_irqsave(&wl->irq_lock, flags);
3104 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3105 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3106 spin_unlock_irqrestore(&wl->irq_lock, flags);
3107 b43_synchronize_irq(dev);
3108
3109 b43_set_status(dev, B43_STAT_INITIALIZED);
3110
3111 mutex_unlock(&wl->mutex);
3112 /* Must unlock as it would otherwise deadlock. No races here.
3113 * Cancel the possibly running self-rearming periodic work. */
3114 cancel_delayed_work_sync(&dev->periodic_work);
3115 mutex_lock(&wl->mutex);
3116
3117 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3118
3119 b43_mac_suspend(dev);
3120 free_irq(dev->dev->irq, dev);
3121 b43dbg(wl, "Wireless interface stopped\n");
3122 }
3123
3124 /* Locking: wl->mutex */
3125 static int b43_wireless_core_start(struct b43_wldev *dev)
3126 {
3127 int err;
3128
3129 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3130
3131 drain_txstatus_queue(dev);
3132 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3133 IRQF_SHARED, KBUILD_MODNAME, dev);
3134 if (err) {
3135 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3136 goto out;
3137 }
3138
3139 /* We are ready to run. */
3140 b43_set_status(dev, B43_STAT_STARTED);
3141
3142 /* Start data flow (TX/RX). */
3143 b43_mac_enable(dev);
3144 b43_interrupt_enable(dev, dev->irq_savedstate);
3145 ieee80211_start_queues(dev->wl->hw);
3146
3147 /* Start maintainance work */
3148 b43_periodic_tasks_setup(dev);
3149
3150 b43dbg(dev->wl, "Wireless interface started\n");
3151 out:
3152 return err;
3153 }
3154
3155 /* Get PHY and RADIO versioning numbers */
3156 static int b43_phy_versioning(struct b43_wldev *dev)
3157 {
3158 struct b43_phy *phy = &dev->phy;
3159 u32 tmp;
3160 u8 analog_type;
3161 u8 phy_type;
3162 u8 phy_rev;
3163 u16 radio_manuf;
3164 u16 radio_ver;
3165 u16 radio_rev;
3166 int unsupported = 0;
3167
3168 /* Get PHY versioning */
3169 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3170 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3171 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3172 phy_rev = (tmp & B43_PHYVER_VERSION);
3173 switch (phy_type) {
3174 case B43_PHYTYPE_A:
3175 if (phy_rev >= 4)
3176 unsupported = 1;
3177 break;
3178 case B43_PHYTYPE_B:
3179 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3180 && phy_rev != 7)
3181 unsupported = 1;
3182 break;
3183 case B43_PHYTYPE_G:
3184 if (phy_rev > 9)
3185 unsupported = 1;
3186 break;
3187 #ifdef CONFIG_B43_NPHY
3188 case B43_PHYTYPE_N:
3189 if (phy_rev > 1)
3190 unsupported = 1;
3191 break;
3192 #endif
3193 default:
3194 unsupported = 1;
3195 };
3196 if (unsupported) {
3197 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3198 "(Analog %u, Type %u, Revision %u)\n",
3199 analog_type, phy_type, phy_rev);
3200 return -EOPNOTSUPP;
3201 }
3202 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3203 analog_type, phy_type, phy_rev);
3204
3205 /* Get RADIO versioning */
3206 if (dev->dev->bus->chip_id == 0x4317) {
3207 if (dev->dev->bus->chip_rev == 0)
3208 tmp = 0x3205017F;
3209 else if (dev->dev->bus->chip_rev == 1)
3210 tmp = 0x4205017F;
3211 else
3212 tmp = 0x5205017F;
3213 } else {
3214 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3215 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3216 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3217 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3218 }
3219 radio_manuf = (tmp & 0x00000FFF);
3220 radio_ver = (tmp & 0x0FFFF000) >> 12;
3221 radio_rev = (tmp & 0xF0000000) >> 28;
3222 if (radio_manuf != 0x17F /* Broadcom */)
3223 unsupported = 1;
3224 switch (phy_type) {
3225 case B43_PHYTYPE_A:
3226 if (radio_ver != 0x2060)
3227 unsupported = 1;
3228 if (radio_rev != 1)
3229 unsupported = 1;
3230 if (radio_manuf != 0x17F)
3231 unsupported = 1;
3232 break;
3233 case B43_PHYTYPE_B:
3234 if ((radio_ver & 0xFFF0) != 0x2050)
3235 unsupported = 1;
3236 break;
3237 case B43_PHYTYPE_G:
3238 if (radio_ver != 0x2050)
3239 unsupported = 1;
3240 break;
3241 case B43_PHYTYPE_N:
3242 if (radio_ver != 0x2055)
3243 unsupported = 1;
3244 break;
3245 default:
3246 B43_WARN_ON(1);
3247 }
3248 if (unsupported) {
3249 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3250 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3251 radio_manuf, radio_ver, radio_rev);
3252 return -EOPNOTSUPP;
3253 }
3254 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3255 radio_manuf, radio_ver, radio_rev);
3256
3257 phy->radio_manuf = radio_manuf;
3258 phy->radio_ver = radio_ver;
3259 phy->radio_rev = radio_rev;
3260
3261 phy->analog = analog_type;
3262 phy->type = phy_type;
3263 phy->rev = phy_rev;
3264
3265 return 0;
3266 }
3267
3268 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3269 struct b43_phy *phy)
3270 {
3271 struct b43_txpower_lo_control *lo;
3272 int i;
3273
3274 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3275 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3276
3277 phy->aci_enable = 0;
3278 phy->aci_wlan_automatic = 0;
3279 phy->aci_hw_rssi = 0;
3280
3281 phy->radio_off_context.valid = 0;
3282
3283 lo = phy->lo_control;
3284 if (lo) {
3285 memset(lo, 0, sizeof(*(phy->lo_control)));
3286 lo->rebuild = 1;
3287 lo->tx_bias = 0xFF;
3288 }
3289 phy->max_lb_gain = 0;
3290 phy->trsw_rx_gain = 0;
3291 phy->txpwr_offset = 0;
3292
3293 /* NRSSI */
3294 phy->nrssislope = 0;
3295 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3296 phy->nrssi[i] = -1000;
3297 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3298 phy->nrssi_lt[i] = i;
3299
3300 phy->lofcal = 0xFFFF;
3301 phy->initval = 0xFFFF;
3302
3303 phy->interfmode = B43_INTERFMODE_NONE;
3304 phy->channel = 0xFF;
3305
3306 phy->hardware_power_control = !!modparam_hwpctl;
3307
3308 /* PHY TX errors counter. */
3309 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3310
3311 /* OFDM-table address caching. */
3312 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3313 }
3314
3315 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3316 {
3317 dev->dfq_valid = 0;
3318
3319 /* Assume the radio is enabled. If it's not enabled, the state will
3320 * immediately get fixed on the first periodic work run. */
3321 dev->radio_hw_enable = 1;
3322
3323 /* Stats */
3324 memset(&dev->stats, 0, sizeof(dev->stats));
3325
3326 setup_struct_phy_for_init(dev, &dev->phy);
3327
3328 /* IRQ related flags */
3329 dev->irq_reason = 0;
3330 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3331 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3332
3333 dev->mac_suspended = 1;
3334
3335 /* Noise calculation context */
3336 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3337 }
3338
3339 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3340 {
3341 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3342 u32 hf;
3343
3344 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3345 return;
3346 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3347 return;
3348
3349 hf = b43_hf_read(dev);
3350 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3351 hf |= B43_HF_BTCOEXALT;
3352 else
3353 hf |= B43_HF_BTCOEX;
3354 b43_hf_write(dev, hf);
3355 //TODO
3356 }
3357
3358 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3359 { //TODO
3360 }
3361
3362 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3363 {
3364 #ifdef CONFIG_SSB_DRIVER_PCICORE
3365 struct ssb_bus *bus = dev->dev->bus;
3366 u32 tmp;
3367
3368 if (bus->pcicore.dev &&
3369 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3370 bus->pcicore.dev->id.revision <= 5) {
3371 /* IMCFGLO timeouts workaround. */
3372 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3373 tmp &= ~SSB_IMCFGLO_REQTO;
3374 tmp &= ~SSB_IMCFGLO_SERTO;
3375 switch (bus->bustype) {
3376 case SSB_BUSTYPE_PCI:
3377 case SSB_BUSTYPE_PCMCIA:
3378 tmp |= 0x32;
3379 break;
3380 case SSB_BUSTYPE_SSB:
3381 tmp |= 0x53;
3382 break;
3383 }
3384 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3385 }
3386 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3387 }
3388
3389 /* Write the short and long frame retry limit values. */
3390 static void b43_set_retry_limits(struct b43_wldev *dev,
3391 unsigned int short_retry,
3392 unsigned int long_retry)
3393 {
3394 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3395 * the chip-internal counter. */
3396 short_retry = min(short_retry, (unsigned int)0xF);
3397 long_retry = min(long_retry, (unsigned int)0xF);
3398
3399 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3400 short_retry);
3401 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3402 long_retry);
3403 }
3404
3405 /* Shutdown a wireless core */
3406 /* Locking: wl->mutex */
3407 static void b43_wireless_core_exit(struct b43_wldev *dev)
3408 {
3409 struct b43_phy *phy = &dev->phy;
3410 u32 macctl;
3411
3412 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3413 if (b43_status(dev) != B43_STAT_INITIALIZED)
3414 return;
3415 b43_set_status(dev, B43_STAT_UNINIT);
3416
3417 /* Stop the microcode PSM. */
3418 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3419 macctl &= ~B43_MACCTL_PSM_RUN;
3420 macctl |= B43_MACCTL_PSM_JMP0;
3421 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3422
3423 if (!dev->suspend_in_progress) {
3424 b43_leds_exit(dev);
3425 b43_rng_exit(dev->wl, false);
3426 }
3427 b43_dma_free(dev);
3428 b43_chip_exit(dev);
3429 b43_radio_turn_off(dev, 1);
3430 b43_switch_analog(dev, 0);
3431 if (phy->dyn_tssi_tbl)
3432 kfree(phy->tssi2dbm);
3433 kfree(phy->lo_control);
3434 phy->lo_control = NULL;
3435 if (dev->wl->current_beacon) {
3436 dev_kfree_skb_any(dev->wl->current_beacon);
3437 dev->wl->current_beacon = NULL;
3438 }
3439
3440 ssb_device_disable(dev->dev, 0);
3441 ssb_bus_may_powerdown(dev->dev->bus);
3442 }
3443
3444 /* Initialize a wireless core */
3445 static int b43_wireless_core_init(struct b43_wldev *dev)
3446 {
3447 struct b43_wl *wl = dev->wl;
3448 struct ssb_bus *bus = dev->dev->bus;
3449 struct ssb_sprom *sprom = &bus->sprom;
3450 struct b43_phy *phy = &dev->phy;
3451 int err;
3452 u32 hf, tmp;
3453
3454 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3455
3456 err = ssb_bus_powerup(bus, 0);
3457 if (err)
3458 goto out;
3459 if (!ssb_device_is_enabled(dev->dev)) {
3460 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3461 b43_wireless_core_reset(dev, tmp);
3462 }
3463
3464 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3465 phy->lo_control =
3466 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3467 if (!phy->lo_control) {
3468 err = -ENOMEM;
3469 goto err_busdown;
3470 }
3471 }
3472 setup_struct_wldev_for_init(dev);
3473
3474 err = b43_phy_init_tssi2dbm_table(dev);
3475 if (err)
3476 goto err_kfree_lo_control;
3477
3478 /* Enable IRQ routing to this device. */
3479 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3480
3481 b43_imcfglo_timeouts_workaround(dev);
3482 b43_bluetooth_coext_disable(dev);
3483 b43_phy_early_init(dev);
3484 err = b43_chip_init(dev);
3485 if (err)
3486 goto err_kfree_tssitbl;
3487 b43_shm_write16(dev, B43_SHM_SHARED,
3488 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3489 hf = b43_hf_read(dev);
3490 if (phy->type == B43_PHYTYPE_G) {
3491 hf |= B43_HF_SYMW;
3492 if (phy->rev == 1)
3493 hf |= B43_HF_GDCW;
3494 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3495 hf |= B43_HF_OFDMPABOOST;
3496 } else if (phy->type == B43_PHYTYPE_B) {
3497 hf |= B43_HF_SYMW;
3498 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3499 hf &= ~B43_HF_GDCW;
3500 }
3501 b43_hf_write(dev, hf);
3502
3503 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3504 B43_DEFAULT_LONG_RETRY_LIMIT);
3505 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3506 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3507
3508 /* Disable sending probe responses from firmware.
3509 * Setting the MaxTime to one usec will always trigger
3510 * a timeout, so we never send any probe resp.
3511 * A timeout of zero is infinite. */
3512 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3513
3514 b43_rate_memory_init(dev);
3515
3516 /* Minimum Contention Window */
3517 if (phy->type == B43_PHYTYPE_B) {
3518 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3519 } else {
3520 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3521 }
3522 /* Maximum Contention Window */
3523 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3524
3525 err = b43_dma_init(dev);
3526 if (err)
3527 goto err_chip_exit;
3528 b43_qos_init(dev);
3529
3530 //FIXME
3531 #if 1
3532 b43_write16(dev, 0x0612, 0x0050);
3533 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3534 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3535 #endif
3536
3537 b43_bluetooth_coext_enable(dev);
3538
3539 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3540 b43_upload_card_macaddress(dev);
3541 b43_security_init(dev);
3542 if (!dev->suspend_in_progress)
3543 b43_rng_init(wl);
3544
3545 b43_set_status(dev, B43_STAT_INITIALIZED);
3546
3547 if (!dev->suspend_in_progress)
3548 b43_leds_init(dev);
3549 out:
3550 return err;
3551
3552 err_chip_exit:
3553 b43_chip_exit(dev);
3554 err_kfree_tssitbl:
3555 if (phy->dyn_tssi_tbl)
3556 kfree(phy->tssi2dbm);
3557 err_kfree_lo_control:
3558 kfree(phy->lo_control);
3559 phy->lo_control = NULL;
3560 err_busdown:
3561 ssb_bus_may_powerdown(bus);
3562 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3563 return err;
3564 }
3565
3566 static int b43_op_add_interface(struct ieee80211_hw *hw,
3567 struct ieee80211_if_init_conf *conf)
3568 {
3569 struct b43_wl *wl = hw_to_b43_wl(hw);
3570 struct b43_wldev *dev;
3571 unsigned long flags;
3572 int err = -EOPNOTSUPP;
3573
3574 /* TODO: allow WDS/AP devices to coexist */
3575
3576 if (conf->type != IEEE80211_IF_TYPE_AP &&
3577 conf->type != IEEE80211_IF_TYPE_STA &&
3578 conf->type != IEEE80211_IF_TYPE_WDS &&
3579 conf->type != IEEE80211_IF_TYPE_IBSS)
3580 return -EOPNOTSUPP;
3581
3582 mutex_lock(&wl->mutex);
3583 if (wl->operating)
3584 goto out_mutex_unlock;
3585
3586 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3587
3588 dev = wl->current_dev;
3589 wl->operating = 1;
3590 wl->vif = conf->vif;
3591 wl->if_type = conf->type;
3592 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3593
3594 spin_lock_irqsave(&wl->irq_lock, flags);
3595 b43_adjust_opmode(dev);
3596 b43_upload_card_macaddress(dev);
3597 spin_unlock_irqrestore(&wl->irq_lock, flags);
3598
3599 err = 0;
3600 out_mutex_unlock:
3601 mutex_unlock(&wl->mutex);
3602
3603 return err;
3604 }
3605
3606 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3607 struct ieee80211_if_init_conf *conf)
3608 {
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
3610 struct b43_wldev *dev = wl->current_dev;
3611 unsigned long flags;
3612
3613 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3614
3615 mutex_lock(&wl->mutex);
3616
3617 B43_WARN_ON(!wl->operating);
3618 B43_WARN_ON(wl->vif != conf->vif);
3619 wl->vif = NULL;
3620
3621 wl->operating = 0;
3622
3623 spin_lock_irqsave(&wl->irq_lock, flags);
3624 b43_adjust_opmode(dev);
3625 memset(wl->mac_addr, 0, ETH_ALEN);
3626 b43_upload_card_macaddress(dev);
3627 spin_unlock_irqrestore(&wl->irq_lock, flags);
3628
3629 mutex_unlock(&wl->mutex);
3630 }
3631
3632 static int b43_op_start(struct ieee80211_hw *hw)
3633 {
3634 struct b43_wl *wl = hw_to_b43_wl(hw);
3635 struct b43_wldev *dev = wl->current_dev;
3636 int did_init = 0;
3637 int err = 0;
3638 bool do_rfkill_exit = 0;
3639
3640 /* Kill all old instance specific information to make sure
3641 * the card won't use it in the short timeframe between start
3642 * and mac80211 reconfiguring it. */
3643 memset(wl->bssid, 0, ETH_ALEN);
3644 memset(wl->mac_addr, 0, ETH_ALEN);
3645 wl->filter_flags = 0;
3646 wl->radiotap_enabled = 0;
3647
3648 /* First register RFkill.
3649 * LEDs that are registered later depend on it. */
3650 b43_rfkill_init(dev);
3651
3652 mutex_lock(&wl->mutex);
3653
3654 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3655 err = b43_wireless_core_init(dev);
3656 if (err) {
3657 do_rfkill_exit = 1;
3658 goto out_mutex_unlock;
3659 }
3660 did_init = 1;
3661 }
3662
3663 if (b43_status(dev) < B43_STAT_STARTED) {
3664 err = b43_wireless_core_start(dev);
3665 if (err) {
3666 if (did_init)
3667 b43_wireless_core_exit(dev);
3668 do_rfkill_exit = 1;
3669 goto out_mutex_unlock;
3670 }
3671 }
3672
3673 out_mutex_unlock:
3674 mutex_unlock(&wl->mutex);
3675
3676 if (do_rfkill_exit)
3677 b43_rfkill_exit(dev);
3678
3679 return err;
3680 }
3681
3682 static void b43_op_stop(struct ieee80211_hw *hw)
3683 {
3684 struct b43_wl *wl = hw_to_b43_wl(hw);
3685 struct b43_wldev *dev = wl->current_dev;
3686
3687 b43_rfkill_exit(dev);
3688
3689 mutex_lock(&wl->mutex);
3690 if (b43_status(dev) >= B43_STAT_STARTED)
3691 b43_wireless_core_stop(dev);
3692 b43_wireless_core_exit(dev);
3693 mutex_unlock(&wl->mutex);
3694 }
3695
3696 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3697 u32 short_retry_limit, u32 long_retry_limit)
3698 {
3699 struct b43_wl *wl = hw_to_b43_wl(hw);
3700 struct b43_wldev *dev;
3701 int err = 0;
3702
3703 mutex_lock(&wl->mutex);
3704 dev = wl->current_dev;
3705 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3706 err = -ENODEV;
3707 goto out_unlock;
3708 }
3709 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3710 out_unlock:
3711 mutex_unlock(&wl->mutex);
3712
3713 return err;
3714 }
3715
3716 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3717 {
3718 struct b43_wl *wl = hw_to_b43_wl(hw);
3719 struct sk_buff *beacon;
3720 unsigned long flags;
3721
3722 /* We could modify the existing beacon and set the aid bit in
3723 * the TIM field, but that would probably require resizing and
3724 * moving of data within the beacon template.
3725 * Simply request a new beacon and let mac80211 do the hard work. */
3726 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3727 if (unlikely(!beacon))
3728 return -ENOMEM;
3729 spin_lock_irqsave(&wl->irq_lock, flags);
3730 b43_update_templates(wl, beacon);
3731 spin_unlock_irqrestore(&wl->irq_lock, flags);
3732
3733 return 0;
3734 }
3735
3736 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3737 struct sk_buff *beacon,
3738 struct ieee80211_tx_control *ctl)
3739 {
3740 struct b43_wl *wl = hw_to_b43_wl(hw);
3741 unsigned long flags;
3742
3743 spin_lock_irqsave(&wl->irq_lock, flags);
3744 b43_update_templates(wl, beacon);
3745 spin_unlock_irqrestore(&wl->irq_lock, flags);
3746
3747 return 0;
3748 }
3749
3750 static const struct ieee80211_ops b43_hw_ops = {
3751 .tx = b43_op_tx,
3752 .conf_tx = b43_op_conf_tx,
3753 .add_interface = b43_op_add_interface,
3754 .remove_interface = b43_op_remove_interface,
3755 .config = b43_op_config,
3756 .config_interface = b43_op_config_interface,
3757 .configure_filter = b43_op_configure_filter,
3758 .set_key = b43_op_set_key,
3759 .get_stats = b43_op_get_stats,
3760 .get_tx_stats = b43_op_get_tx_stats,
3761 .start = b43_op_start,
3762 .stop = b43_op_stop,
3763 .set_retry_limit = b43_op_set_retry_limit,
3764 .set_tim = b43_op_beacon_set_tim,
3765 .beacon_update = b43_op_ibss_beacon_update,
3766 };
3767
3768 /* Hard-reset the chip. Do not call this directly.
3769 * Use b43_controller_restart()
3770 */
3771 static void b43_chip_reset(struct work_struct *work)
3772 {
3773 struct b43_wldev *dev =
3774 container_of(work, struct b43_wldev, restart_work);
3775 struct b43_wl *wl = dev->wl;
3776 int err = 0;
3777 int prev_status;
3778
3779 mutex_lock(&wl->mutex);
3780
3781 prev_status = b43_status(dev);
3782 /* Bring the device down... */
3783 if (prev_status >= B43_STAT_STARTED)
3784 b43_wireless_core_stop(dev);
3785 if (prev_status >= B43_STAT_INITIALIZED)
3786 b43_wireless_core_exit(dev);
3787
3788 /* ...and up again. */
3789 if (prev_status >= B43_STAT_INITIALIZED) {
3790 err = b43_wireless_core_init(dev);
3791 if (err)
3792 goto out;
3793 }
3794 if (prev_status >= B43_STAT_STARTED) {
3795 err = b43_wireless_core_start(dev);
3796 if (err) {
3797 b43_wireless_core_exit(dev);
3798 goto out;
3799 }
3800 }
3801 out:
3802 mutex_unlock(&wl->mutex);
3803 if (err)
3804 b43err(wl, "Controller restart FAILED\n");
3805 else
3806 b43info(wl, "Controller restarted\n");
3807 }
3808
3809 static int b43_setup_modes(struct b43_wldev *dev,
3810 bool have_2ghz_phy, bool have_5ghz_phy)
3811 {
3812 struct ieee80211_hw *hw = dev->wl->hw;
3813 struct ieee80211_hw_mode *mode;
3814 struct b43_phy *phy = &dev->phy;
3815 int err;
3816
3817 /* XXX: This function will go away soon, when mac80211
3818 * band stuff is rewritten. So this is just a hack.
3819 * For now we always claim GPHY mode, as there is no
3820 * support for NPHY and APHY in the device, yet.
3821 * This assumption is OK, as any B, N or A PHY will already
3822 * have died a horrible sanity check death earlier. */
3823
3824 mode = &phy->hwmodes[0];
3825 mode->mode = MODE_IEEE80211G;
3826 mode->num_channels = b43_2ghz_chantable_size;
3827 mode->channels = b43_2ghz_chantable;
3828 mode->num_rates = b43_g_ratetable_size;
3829 mode->rates = b43_g_ratetable;
3830 err = ieee80211_register_hwmode(hw, mode);
3831 if (err)
3832 return err;
3833 phy->possible_phymodes |= B43_PHYMODE_G;
3834
3835 return 0;
3836 }
3837
3838 static void b43_wireless_core_detach(struct b43_wldev *dev)
3839 {
3840 /* We release firmware that late to not be required to re-request
3841 * is all the time when we reinit the core. */
3842 b43_release_firmware(dev);
3843 }
3844
3845 static int b43_wireless_core_attach(struct b43_wldev *dev)
3846 {
3847 struct b43_wl *wl = dev->wl;
3848 struct ssb_bus *bus = dev->dev->bus;
3849 struct pci_dev *pdev = bus->host_pci;
3850 int err;
3851 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3852 u32 tmp;
3853
3854 /* Do NOT do any device initialization here.
3855 * Do it in wireless_core_init() instead.
3856 * This function is for gathering basic information about the HW, only.
3857 * Also some structs may be set up here. But most likely you want to have
3858 * that in core_init(), too.
3859 */
3860
3861 err = ssb_bus_powerup(bus, 0);
3862 if (err) {
3863 b43err(wl, "Bus powerup failed\n");
3864 goto out;
3865 }
3866 /* Get the PHY type. */
3867 if (dev->dev->id.revision >= 5) {
3868 u32 tmshigh;
3869
3870 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3871 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3872 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3873 } else
3874 B43_WARN_ON(1);
3875
3876 dev->phy.gmode = have_2ghz_phy;
3877 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3878 b43_wireless_core_reset(dev, tmp);
3879
3880 err = b43_phy_versioning(dev);
3881 if (err)
3882 goto err_powerdown;
3883 /* Check if this device supports multiband. */
3884 if (!pdev ||
3885 (pdev->device != 0x4312 &&
3886 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3887 /* No multiband support. */
3888 have_2ghz_phy = 0;
3889 have_5ghz_phy = 0;
3890 switch (dev->phy.type) {
3891 case B43_PHYTYPE_A:
3892 have_5ghz_phy = 1;
3893 break;
3894 case B43_PHYTYPE_G:
3895 case B43_PHYTYPE_N:
3896 have_2ghz_phy = 1;
3897 break;
3898 default:
3899 B43_WARN_ON(1);
3900 }
3901 }
3902 if (dev->phy.type == B43_PHYTYPE_A) {
3903 /* FIXME */
3904 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3905 err = -EOPNOTSUPP;
3906 goto err_powerdown;
3907 }
3908 dev->phy.gmode = have_2ghz_phy;
3909 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3910 b43_wireless_core_reset(dev, tmp);
3911
3912 err = b43_validate_chipaccess(dev);
3913 if (err)
3914 goto err_powerdown;
3915 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3916 if (err)
3917 goto err_powerdown;
3918
3919 /* Now set some default "current_dev" */
3920 if (!wl->current_dev)
3921 wl->current_dev = dev;
3922 INIT_WORK(&dev->restart_work, b43_chip_reset);
3923
3924 b43_radio_turn_off(dev, 1);
3925 b43_switch_analog(dev, 0);
3926 ssb_device_disable(dev->dev, 0);
3927 ssb_bus_may_powerdown(bus);
3928
3929 out:
3930 return err;
3931
3932 err_powerdown:
3933 ssb_bus_may_powerdown(bus);
3934 return err;
3935 }
3936
3937 static void b43_one_core_detach(struct ssb_device *dev)
3938 {
3939 struct b43_wldev *wldev;
3940 struct b43_wl *wl;
3941
3942 wldev = ssb_get_drvdata(dev);
3943 wl = wldev->wl;
3944 cancel_work_sync(&wldev->restart_work);
3945 b43_debugfs_remove_device(wldev);
3946 b43_wireless_core_detach(wldev);
3947 list_del(&wldev->list);
3948 wl->nr_devs--;
3949 ssb_set_drvdata(dev, NULL);
3950 kfree(wldev);
3951 }
3952
3953 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3954 {
3955 struct b43_wldev *wldev;
3956 struct pci_dev *pdev;
3957 int err = -ENOMEM;
3958
3959 if (!list_empty(&wl->devlist)) {
3960 /* We are not the first core on this chip. */
3961 pdev = dev->bus->host_pci;
3962 /* Only special chips support more than one wireless
3963 * core, although some of the other chips have more than
3964 * one wireless core as well. Check for this and
3965 * bail out early.
3966 */
3967 if (!pdev ||
3968 ((pdev->device != 0x4321) &&
3969 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3970 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3971 return -ENODEV;
3972 }
3973 }
3974
3975 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3976 if (!wldev)
3977 goto out;
3978
3979 wldev->dev = dev;
3980 wldev->wl = wl;
3981 b43_set_status(wldev, B43_STAT_UNINIT);
3982 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3983 tasklet_init(&wldev->isr_tasklet,
3984 (void (*)(unsigned long))b43_interrupt_tasklet,
3985 (unsigned long)wldev);
3986 INIT_LIST_HEAD(&wldev->list);
3987
3988 err = b43_wireless_core_attach(wldev);
3989 if (err)
3990 goto err_kfree_wldev;
3991
3992 list_add(&wldev->list, &wl->devlist);
3993 wl->nr_devs++;
3994 ssb_set_drvdata(dev, wldev);
3995 b43_debugfs_add_device(wldev);
3996
3997 out:
3998 return err;
3999
4000 err_kfree_wldev:
4001 kfree(wldev);
4002 return err;
4003 }
4004
4005 static void b43_sprom_fixup(struct ssb_bus *bus)
4006 {
4007 /* boardflags workarounds */
4008 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4009 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4010 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4011 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4012 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4013 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4014 }
4015
4016 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4017 {
4018 struct ieee80211_hw *hw = wl->hw;
4019
4020 ssb_set_devtypedata(dev, NULL);
4021 ieee80211_free_hw(hw);
4022 }
4023
4024 static int b43_wireless_init(struct ssb_device *dev)
4025 {
4026 struct ssb_sprom *sprom = &dev->bus->sprom;
4027 struct ieee80211_hw *hw;
4028 struct b43_wl *wl;
4029 int err = -ENOMEM;
4030
4031 b43_sprom_fixup(dev->bus);
4032
4033 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4034 if (!hw) {
4035 b43err(NULL, "Could not allocate ieee80211 device\n");
4036 goto out;
4037 }
4038
4039 /* fill hw info */
4040 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4041 IEEE80211_HW_RX_INCLUDES_FCS;
4042 hw->max_signal = 100;
4043 hw->max_rssi = -110;
4044 hw->max_noise = -110;
4045 hw->queues = 1; /* FIXME: hardware has more queues */
4046 SET_IEEE80211_DEV(hw, dev->dev);
4047 if (is_valid_ether_addr(sprom->et1mac))
4048 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4049 else
4050 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4051
4052 /* Get and initialize struct b43_wl */
4053 wl = hw_to_b43_wl(hw);
4054 memset(wl, 0, sizeof(*wl));
4055 wl->hw = hw;
4056 spin_lock_init(&wl->irq_lock);
4057 spin_lock_init(&wl->leds_lock);
4058 spin_lock_init(&wl->shm_lock);
4059 mutex_init(&wl->mutex);
4060 INIT_LIST_HEAD(&wl->devlist);
4061
4062 ssb_set_devtypedata(dev, wl);
4063 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4064 err = 0;
4065 out:
4066 return err;
4067 }
4068
4069 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4070 {
4071 struct b43_wl *wl;
4072 int err;
4073 int first = 0;
4074
4075 wl = ssb_get_devtypedata(dev);
4076 if (!wl) {
4077 /* Probing the first core. Must setup common struct b43_wl */
4078 first = 1;
4079 err = b43_wireless_init(dev);
4080 if (err)
4081 goto out;
4082 wl = ssb_get_devtypedata(dev);
4083 B43_WARN_ON(!wl);
4084 }
4085 err = b43_one_core_attach(dev, wl);
4086 if (err)
4087 goto err_wireless_exit;
4088
4089 if (first) {
4090 err = ieee80211_register_hw(wl->hw);
4091 if (err)
4092 goto err_one_core_detach;
4093 }
4094
4095 out:
4096 return err;
4097
4098 err_one_core_detach:
4099 b43_one_core_detach(dev);
4100 err_wireless_exit:
4101 if (first)
4102 b43_wireless_exit(dev, wl);
4103 return err;
4104 }
4105
4106 static void b43_remove(struct ssb_device *dev)
4107 {
4108 struct b43_wl *wl = ssb_get_devtypedata(dev);
4109 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4110
4111 B43_WARN_ON(!wl);
4112 if (wl->current_dev == wldev)
4113 ieee80211_unregister_hw(wl->hw);
4114
4115 b43_one_core_detach(dev);
4116
4117 if (list_empty(&wl->devlist)) {
4118 /* Last core on the chip unregistered.
4119 * We can destroy common struct b43_wl.
4120 */
4121 b43_wireless_exit(dev, wl);
4122 }
4123 }
4124
4125 /* Perform a hardware reset. This can be called from any context. */
4126 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4127 {
4128 /* Must avoid requeueing, if we are in shutdown. */
4129 if (b43_status(dev) < B43_STAT_INITIALIZED)
4130 return;
4131 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4132 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4133 }
4134
4135 #ifdef CONFIG_PM
4136
4137 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4138 {
4139 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4140 struct b43_wl *wl = wldev->wl;
4141
4142 b43dbg(wl, "Suspending...\n");
4143
4144 mutex_lock(&wl->mutex);
4145 wldev->suspend_in_progress = true;
4146 wldev->suspend_init_status = b43_status(wldev);
4147 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4148 b43_wireless_core_stop(wldev);
4149 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4150 b43_wireless_core_exit(wldev);
4151 mutex_unlock(&wl->mutex);
4152
4153 b43dbg(wl, "Device suspended.\n");
4154
4155 return 0;
4156 }
4157
4158 static int b43_resume(struct ssb_device *dev)
4159 {
4160 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4161 struct b43_wl *wl = wldev->wl;
4162 int err = 0;
4163
4164 b43dbg(wl, "Resuming...\n");
4165
4166 mutex_lock(&wl->mutex);
4167 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4168 err = b43_wireless_core_init(wldev);
4169 if (err) {
4170 b43err(wl, "Resume failed at core init\n");
4171 goto out;
4172 }
4173 }
4174 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4175 err = b43_wireless_core_start(wldev);
4176 if (err) {
4177 b43_leds_exit(wldev);
4178 b43_rng_exit(wldev->wl, true);
4179 b43_wireless_core_exit(wldev);
4180 b43err(wl, "Resume failed at core start\n");
4181 goto out;
4182 }
4183 }
4184 b43dbg(wl, "Device resumed.\n");
4185 out:
4186 wldev->suspend_in_progress = false;
4187 mutex_unlock(&wl->mutex);
4188 return err;
4189 }
4190
4191 #else /* CONFIG_PM */
4192 # define b43_suspend NULL
4193 # define b43_resume NULL
4194 #endif /* CONFIG_PM */
4195
4196 static struct ssb_driver b43_ssb_driver = {
4197 .name = KBUILD_MODNAME,
4198 .id_table = b43_ssb_tbl,
4199 .probe = b43_probe,
4200 .remove = b43_remove,
4201 .suspend = b43_suspend,
4202 .resume = b43_resume,
4203 };
4204
4205 static void b43_print_driverinfo(void)
4206 {
4207 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4208 *feat_leds = "", *feat_rfkill = "";
4209
4210 #ifdef CONFIG_B43_PCI_AUTOSELECT
4211 feat_pci = "P";
4212 #endif
4213 #ifdef CONFIG_B43_PCMCIA
4214 feat_pcmcia = "M";
4215 #endif
4216 #ifdef CONFIG_B43_NPHY
4217 feat_nphy = "N";
4218 #endif
4219 #ifdef CONFIG_B43_LEDS
4220 feat_leds = "L";
4221 #endif
4222 #ifdef CONFIG_B43_RFKILL
4223 feat_rfkill = "R";
4224 #endif
4225 printk(KERN_INFO "Broadcom 43xx driver loaded "
4226 "[ Features: %s%s%s%s%s, Firmware-ID: "
4227 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4228 feat_pci, feat_pcmcia, feat_nphy,
4229 feat_leds, feat_rfkill);
4230 }
4231
4232 static int __init b43_init(void)
4233 {
4234 int err;
4235
4236 b43_debugfs_init();
4237 err = b43_pcmcia_init();
4238 if (err)
4239 goto err_dfs_exit;
4240 err = ssb_driver_register(&b43_ssb_driver);
4241 if (err)
4242 goto err_pcmcia_exit;
4243 b43_print_driverinfo();
4244
4245 return err;
4246
4247 err_pcmcia_exit:
4248 b43_pcmcia_exit();
4249 err_dfs_exit:
4250 b43_debugfs_exit();
4251 return err;
4252 }
4253
4254 static void __exit b43_exit(void)
4255 {
4256 ssb_driver_unregister(&b43_ssb_driver);
4257 b43_pcmcia_exit();
4258 b43_debugfs_exit();
4259 }
4260
4261 module_init(b43_init)
4262 module_exit(b43_exit)
WRT350N Kernel Patches