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Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[wrt350n-kernel.git] / drivers / net / wireless / rt2x00 / rt73usb.c
blob8103d41a1543d04461611fada2d53d684d873962
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/usb.h>
33
34 #include "rt2x00.h"
35 #include "rt2x00usb.h"
36 #include "rt73usb.h"
37
38 /*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 * The _lock versions must be used if you already hold the usb_cache_mutex
51 */
52 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
53 const unsigned int offset, u32 *value)
54 {
55 __le32 reg;
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 &reg, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
60 }
61
62 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
64 {
65 __le32 reg;
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 &reg, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
70 }
71
72 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 void *value, const u32 length)
75 {
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
80 }
81
82 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
83 const unsigned int offset, u32 value)
84 {
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 &reg, sizeof(u32), REGISTER_TIMEOUT);
89 }
90
91 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
93 {
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 &reg, sizeof(u32), REGISTER_TIMEOUT);
98 }
99
100 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
101 const unsigned int offset,
102 void *value, const u32 length)
103 {
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
108 }
109
110 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
111 {
112 u32 reg;
113 unsigned int i;
114
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
118 break;
119 udelay(REGISTER_BUSY_DELAY);
120 }
121
122 return reg;
123 }
124
125 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127 {
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->usb_cache_mutex);
131
132 /*
133 * Wait until the BBP becomes ready.
134 */
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
139 return;
140 }
141
142 /*
143 * Write the data into the BBP.
144 */
145 reg = 0;
146 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
150
151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
153 }
154
155 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
156 const unsigned int word, u8 *value)
157 {
158 u32 reg;
159
160 mutex_lock(&rt2x00dev->usb_cache_mutex);
161
162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
169 return;
170 }
171
172 /*
173 * Write the request into the BBP.
174 */
175 reg = 0;
176 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
179
180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
181
182 /*
183 * Wait until the BBP becomes ready.
184 */
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
188 *value = 0xff;
189 return;
190 }
191
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
194 }
195
196 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
197 const unsigned int word, const u32 value)
198 {
199 u32 reg;
200 unsigned int i;
201
202 if (!word)
203 return;
204
205 mutex_lock(&rt2x00dev->usb_cache_mutex);
206
207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
210 goto rf_write;
211 udelay(REGISTER_BUSY_DELAY);
212 }
213
214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
216 return;
217
218 rf_write:
219 reg = 0;
220 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
221
222 /*
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
225 */
226 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
229 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
231
232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
233 rt2x00_rf_write(rt2x00dev, word, value);
234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
235 }
236
237 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
238 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
239
240 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
241 const unsigned int word, u32 *data)
242 {
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
244 }
245
246 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
247 const unsigned int word, u32 data)
248 {
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
250 }
251
252 static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
254 .csr = {
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
259 },
260 .eeprom = {
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
271 },
272 .rf = {
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278 };
279 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281 /*
282 * Configuration handlers.
283 */
284 static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
285 {
286 u32 tmp;
287
288 tmp = le32_to_cpu(mac[1]);
289 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
290 mac[1] = cpu_to_le32(tmp);
291
292 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
293 (2 * sizeof(__le32)));
294 }
295
296 static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
297 {
298 u32 tmp;
299
300 tmp = le32_to_cpu(bssid[1]);
301 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
302 bssid[1] = cpu_to_le32(tmp);
303
304 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
305 (2 * sizeof(__le32)));
306 }
307
308 static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
309 const int tsf_sync)
310 {
311 u32 reg;
312
313 /*
314 * Clear current synchronisation setup.
315 * For the Beacon base registers we only need to clear
316 * the first byte since that byte contains the VALID and OWNER
317 * bits which (when set to 0) will invalidate the entire beacon.
318 */
319 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
320 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
321 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
322 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
323 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
324
325 /*
326 * Enable synchronisation.
327 */
328 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
329 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
330 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
331 (tsf_sync == TSF_SYNC_BEACON));
332 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
333 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
334 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
335 }
336
337 static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
338 const int short_preamble,
339 const int ack_timeout,
340 const int ack_consume_time)
341 {
342 u32 reg;
343
344 /*
345 * When in atomic context, reschedule and let rt2x00lib
346 * call this function again.
347 */
348 if (in_atomic()) {
349 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
350 return;
351 }
352
353 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
354 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
355 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
356
357 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
358 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
359 !!short_preamble);
360 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
361 }
362
363 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
364 const int basic_rate_mask)
365 {
366 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
367 }
368
369 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
370 struct rf_channel *rf, const int txpower)
371 {
372 u8 r3;
373 u8 r94;
374 u8 smart;
375
376 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
377 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
378
379 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
380 rt2x00_rf(&rt2x00dev->chip, RF2527));
381
382 rt73usb_bbp_read(rt2x00dev, 3, &r3);
383 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
384 rt73usb_bbp_write(rt2x00dev, 3, r3);
385
386 r94 = 6;
387 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
388 r94 += txpower - MAX_TXPOWER;
389 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
390 r94 += txpower;
391 rt73usb_bbp_write(rt2x00dev, 94, r94);
392
393 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
394 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
395 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
396 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
397
398 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
399 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
400 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
401 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
402
403 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
404 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
405 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
406 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
407
408 udelay(10);
409 }
410
411 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
412 const int txpower)
413 {
414 struct rf_channel rf;
415
416 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
417 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
418 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
419 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
420
421 rt73usb_config_channel(rt2x00dev, &rf, txpower);
422 }
423
424 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
425 struct antenna_setup *ant)
426 {
427 u8 r3;
428 u8 r4;
429 u8 r77;
430 u8 temp;
431
432 rt73usb_bbp_read(rt2x00dev, 3, &r3);
433 rt73usb_bbp_read(rt2x00dev, 4, &r4);
434 rt73usb_bbp_read(rt2x00dev, 77, &r77);
435
436 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
437
438 /*
439 * Configure the RX antenna.
440 */
441 switch (ant->rx) {
442 case ANTENNA_HW_DIVERSITY:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
444 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
445 && (rt2x00dev->curr_hwmode != HWMODE_A);
446 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
447 break;
448 case ANTENNA_A:
449 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
450 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
451 if (rt2x00dev->curr_hwmode == HWMODE_A)
452 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
453 else
454 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
455 break;
456 case ANTENNA_SW_DIVERSITY:
457 /*
458 * NOTE: We should never come here because rt2x00lib is
459 * supposed to catch this and send us the correct antenna
460 * explicitely. However we are nog going to bug about this.
461 * Instead, just default to antenna B.
462 */
463 case ANTENNA_B:
464 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
465 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
466 if (rt2x00dev->curr_hwmode == HWMODE_A)
467 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
468 else
469 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
470 break;
471 }
472
473 rt73usb_bbp_write(rt2x00dev, 77, r77);
474 rt73usb_bbp_write(rt2x00dev, 3, r3);
475 rt73usb_bbp_write(rt2x00dev, 4, r4);
476 }
477
478 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
479 struct antenna_setup *ant)
480 {
481 u8 r3;
482 u8 r4;
483 u8 r77;
484
485 rt73usb_bbp_read(rt2x00dev, 3, &r3);
486 rt73usb_bbp_read(rt2x00dev, 4, &r4);
487 rt73usb_bbp_read(rt2x00dev, 77, &r77);
488
489 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
490 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
491 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
492
493 /*
494 * Configure the RX antenna.
495 */
496 switch (ant->rx) {
497 case ANTENNA_HW_DIVERSITY:
498 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
499 break;
500 case ANTENNA_A:
501 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
502 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
503 break;
504 case ANTENNA_SW_DIVERSITY:
505 /*
506 * NOTE: We should never come here because rt2x00lib is
507 * supposed to catch this and send us the correct antenna
508 * explicitely. However we are nog going to bug about this.
509 * Instead, just default to antenna B.
510 */
511 case ANTENNA_B:
512 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
513 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
514 break;
515 }
516
517 rt73usb_bbp_write(rt2x00dev, 77, r77);
518 rt73usb_bbp_write(rt2x00dev, 3, r3);
519 rt73usb_bbp_write(rt2x00dev, 4, r4);
520 }
521
522 struct antenna_sel {
523 u8 word;
524 /*
525 * value[0] -> non-LNA
526 * value[1] -> LNA
527 */
528 u8 value[2];
529 };
530
531 static const struct antenna_sel antenna_sel_a[] = {
532 { 96, { 0x58, 0x78 } },
533 { 104, { 0x38, 0x48 } },
534 { 75, { 0xfe, 0x80 } },
535 { 86, { 0xfe, 0x80 } },
536 { 88, { 0xfe, 0x80 } },
537 { 35, { 0x60, 0x60 } },
538 { 97, { 0x58, 0x58 } },
539 { 98, { 0x58, 0x58 } },
540 };
541
542 static const struct antenna_sel antenna_sel_bg[] = {
543 { 96, { 0x48, 0x68 } },
544 { 104, { 0x2c, 0x3c } },
545 { 75, { 0xfe, 0x80 } },
546 { 86, { 0xfe, 0x80 } },
547 { 88, { 0xfe, 0x80 } },
548 { 35, { 0x50, 0x50 } },
549 { 97, { 0x48, 0x48 } },
550 { 98, { 0x48, 0x48 } },
551 };
552
553 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
554 struct antenna_setup *ant)
555 {
556 const struct antenna_sel *sel;
557 unsigned int lna;
558 unsigned int i;
559 u32 reg;
560
561 if (rt2x00dev->curr_hwmode == HWMODE_A) {
562 sel = antenna_sel_a;
563 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
564 } else {
565 sel = antenna_sel_bg;
566 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
567 }
568
569 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
570 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
571
572 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
573
574 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
575 (rt2x00dev->curr_hwmode == HWMODE_B ||
576 rt2x00dev->curr_hwmode == HWMODE_G));
577 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
578 (rt2x00dev->curr_hwmode == HWMODE_A));
579
580 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
581
582 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
583 rt2x00_rf(&rt2x00dev->chip, RF5225))
584 rt73usb_config_antenna_5x(rt2x00dev, ant);
585 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
586 rt2x00_rf(&rt2x00dev->chip, RF2527))
587 rt73usb_config_antenna_2x(rt2x00dev, ant);
588 }
589
590 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
591 struct rt2x00lib_conf *libconf)
592 {
593 u32 reg;
594
595 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
596 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
597 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
598
599 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
600 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
601 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
602 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
603 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
604
605 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
606 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
607 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
608
609 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
610 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
611 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
612
613 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
614 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
615 libconf->conf->beacon_int * 16);
616 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
617 }
618
619 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
620 const unsigned int flags,
621 struct rt2x00lib_conf *libconf)
622 {
623 if (flags & CONFIG_UPDATE_PHYMODE)
624 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
625 if (flags & CONFIG_UPDATE_CHANNEL)
626 rt73usb_config_channel(rt2x00dev, &libconf->rf,
627 libconf->conf->power_level);
628 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
629 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
630 if (flags & CONFIG_UPDATE_ANTENNA)
631 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
632 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
633 rt73usb_config_duration(rt2x00dev, libconf);
634 }
635
636 /*
637 * LED functions.
638 */
639 static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
640 {
641 u32 reg;
642
643 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
644 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
645 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
646 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
647
648 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
649 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
650 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
651 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
652 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
653
654 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
655 rt2x00dev->led_reg, REGISTER_TIMEOUT);
656 }
657
658 static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
659 {
660 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
661 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
662 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
663
664 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
665 rt2x00dev->led_reg, REGISTER_TIMEOUT);
666 }
667
668 static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
669 {
670 u32 led;
671
672 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
673 return;
674
675 /*
676 * Led handling requires a positive value for the rssi,
677 * to do that correctly we need to add the correction.
678 */
679 rssi += rt2x00dev->rssi_offset;
680
681 if (rssi <= 30)
682 led = 0;
683 else if (rssi <= 39)
684 led = 1;
685 else if (rssi <= 49)
686 led = 2;
687 else if (rssi <= 53)
688 led = 3;
689 else if (rssi <= 63)
690 led = 4;
691 else
692 led = 5;
693
694 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
695 rt2x00dev->led_reg, REGISTER_TIMEOUT);
696 }
697
698 /*
699 * Link tuning
700 */
701 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
702 struct link_qual *qual)
703 {
704 u32 reg;
705
706 /*
707 * Update FCS error count from register.
708 */
709 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
710 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
711
712 /*
713 * Update False CCA count from register.
714 */
715 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
716 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
717 }
718
719 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
720 {
721 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
722 rt2x00dev->link.vgc_level = 0x20;
723 }
724
725 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
726 {
727 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
728 u8 r17;
729 u8 up_bound;
730 u8 low_bound;
731
732 /*
733 * Update Led strength
734 */
735 rt73usb_activity_led(rt2x00dev, rssi);
736
737 rt73usb_bbp_read(rt2x00dev, 17, &r17);
738
739 /*
740 * Determine r17 bounds.
741 */
742 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
743 low_bound = 0x28;
744 up_bound = 0x48;
745
746 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
747 low_bound += 0x10;
748 up_bound += 0x10;
749 }
750 } else {
751 if (rssi > -82) {
752 low_bound = 0x1c;
753 up_bound = 0x40;
754 } else if (rssi > -84) {
755 low_bound = 0x1c;
756 up_bound = 0x20;
757 } else {
758 low_bound = 0x1c;
759 up_bound = 0x1c;
760 }
761
762 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
763 low_bound += 0x14;
764 up_bound += 0x10;
765 }
766 }
767
768 /*
769 * Special big-R17 for very short distance
770 */
771 if (rssi > -35) {
772 if (r17 != 0x60)
773 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
774 return;
775 }
776
777 /*
778 * Special big-R17 for short distance
779 */
780 if (rssi >= -58) {
781 if (r17 != up_bound)
782 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
783 return;
784 }
785
786 /*
787 * Special big-R17 for middle-short distance
788 */
789 if (rssi >= -66) {
790 low_bound += 0x10;
791 if (r17 != low_bound)
792 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
793 return;
794 }
795
796 /*
797 * Special mid-R17 for middle distance
798 */
799 if (rssi >= -74) {
800 if (r17 != (low_bound + 0x10))
801 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
802 return;
803 }
804
805 /*
806 * Special case: Change up_bound based on the rssi.
807 * Lower up_bound when rssi is weaker then -74 dBm.
808 */
809 up_bound -= 2 * (-74 - rssi);
810 if (low_bound > up_bound)
811 up_bound = low_bound;
812
813 if (r17 > up_bound) {
814 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
815 return;
816 }
817
818 /*
819 * r17 does not yet exceed upper limit, continue and base
820 * the r17 tuning on the false CCA count.
821 */
822 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
823 r17 += 4;
824 if (r17 > up_bound)
825 r17 = up_bound;
826 rt73usb_bbp_write(rt2x00dev, 17, r17);
827 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
828 r17 -= 4;
829 if (r17 < low_bound)
830 r17 = low_bound;
831 rt73usb_bbp_write(rt2x00dev, 17, r17);
832 }
833 }
834
835 /*
836 * Firmware name function.
837 */
838 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
839 {
840 return FIRMWARE_RT2571;
841 }
842
843 /*
844 * Initialization functions.
845 */
846 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
847 const size_t len)
848 {
849 unsigned int i;
850 int status;
851 u32 reg;
852 char *ptr = data;
853 char *cache;
854 int buflen;
855 int timeout;
856
857 /*
858 * Wait for stable hardware.
859 */
860 for (i = 0; i < 100; i++) {
861 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
862 if (reg)
863 break;
864 msleep(1);
865 }
866
867 if (!reg) {
868 ERROR(rt2x00dev, "Unstable hardware.\n");
869 return -EBUSY;
870 }
871
872 /*
873 * Write firmware to device.
874 * We setup a seperate cache for this action,
875 * since we are going to write larger chunks of data
876 * then normally used cache size.
877 */
878 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
879 if (!cache) {
880 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
881 return -ENOMEM;
882 }
883
884 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
885 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
886 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
887
888 memcpy(cache, ptr, buflen);
889
890 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
891 USB_VENDOR_REQUEST_OUT,
892 FIRMWARE_IMAGE_BASE + i, 0x0000,
893 cache, buflen, timeout);
894
895 ptr += buflen;
896 }
897
898 kfree(cache);
899
900 /*
901 * Send firmware request to device to load firmware,
902 * we need to specify a long timeout time.
903 */
904 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
905 0x0000, USB_MODE_FIRMWARE,
906 REGISTER_TIMEOUT_FIRMWARE);
907 if (status < 0) {
908 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
909 return status;
910 }
911
912 rt73usb_disable_led(rt2x00dev);
913
914 return 0;
915 }
916
917 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
918 {
919 u32 reg;
920
921 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
922 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
923 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
924 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
925 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
926
927 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
928 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
929 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
930 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
931 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
932 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
933 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
934 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
935 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
936 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
937
938 /*
939 * CCK TXD BBP registers
940 */
941 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
942 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
943 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
944 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
945 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
946 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
947 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
948 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
949 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
950 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
951
952 /*
953 * OFDM TXD BBP registers
954 */
955 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
956 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
957 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
958 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
959 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
960 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
961 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
962 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
963
964 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
965 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
966 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
967 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
968 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
969 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
970
971 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
972 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
973 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
974 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
975 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
976 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
977
978 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
979
980 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
981 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
982 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
983
984 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
985
986 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
987 return -EBUSY;
988
989 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
990
991 /*
992 * Invalidate all Shared Keys (SEC_CSR0),
993 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
994 */
995 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
996 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
997 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
998
999 reg = 0x000023b0;
1000 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1001 rt2x00_rf(&rt2x00dev->chip, RF2527))
1002 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1003 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1004
1005 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1006 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1007 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1008
1009 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1010 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1011 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1012 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1013
1014 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1015 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1016 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1017 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1018
1019 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1020 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1021 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1022
1023 /*
1024 * We must clear the error counters.
1025 * These registers are cleared on read,
1026 * so we may pass a useless variable to store the value.
1027 */
1028 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1029 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1030 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1031
1032 /*
1033 * Reset MAC and BBP registers.
1034 */
1035 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1036 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1037 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1038 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1039
1040 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1041 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1042 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1043 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1044
1045 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1046 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1047 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1048
1049 return 0;
1050 }
1051
1052 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1053 {
1054 unsigned int i;
1055 u16 eeprom;
1056 u8 reg_id;
1057 u8 value;
1058
1059 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1060 rt73usb_bbp_read(rt2x00dev, 0, &value);
1061 if ((value != 0xff) && (value != 0x00))
1062 goto continue_csr_init;
1063 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1064 udelay(REGISTER_BUSY_DELAY);
1065 }
1066
1067 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1068 return -EACCES;
1069
1070 continue_csr_init:
1071 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1072 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1073 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1074 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1075 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1076 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1077 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1078 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1079 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1080 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1081 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1082 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1083 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1084 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1085 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1086 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1087 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1088 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1089 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1090 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1091 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1092 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1093 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1094 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1095 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1096
1097 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1098 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1099 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1100
1101 if (eeprom != 0xffff && eeprom != 0x0000) {
1102 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1103 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1104 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1105 reg_id, value);
1106 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1107 }
1108 }
1109 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1110
1111 return 0;
1112 }
1113
1114 /*
1115 * Device state switch handlers.
1116 */
1117 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1118 enum dev_state state)
1119 {
1120 u32 reg;
1121
1122 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1123 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1124 state == STATE_RADIO_RX_OFF);
1125 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1126 }
1127
1128 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1129 {
1130 /*
1131 * Initialize all registers.
1132 */
1133 if (rt73usb_init_registers(rt2x00dev) ||
1134 rt73usb_init_bbp(rt2x00dev)) {
1135 ERROR(rt2x00dev, "Register initialization failed.\n");
1136 return -EIO;
1137 }
1138
1139 /*
1140 * Enable LED
1141 */
1142 rt73usb_enable_led(rt2x00dev);
1143
1144 return 0;
1145 }
1146
1147 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1148 {
1149 /*
1150 * Disable LED
1151 */
1152 rt73usb_disable_led(rt2x00dev);
1153
1154 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1155
1156 /*
1157 * Disable synchronisation.
1158 */
1159 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1160
1161 rt2x00usb_disable_radio(rt2x00dev);
1162 }
1163
1164 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1165 {
1166 u32 reg;
1167 unsigned int i;
1168 char put_to_sleep;
1169 char current_state;
1170
1171 put_to_sleep = (state != STATE_AWAKE);
1172
1173 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1174 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1175 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1176 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1177
1178 /*
1179 * Device is not guaranteed to be in the requested state yet.
1180 * We must wait until the register indicates that the
1181 * device has entered the correct state.
1182 */
1183 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1184 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1185 current_state =
1186 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1187 if (current_state == !put_to_sleep)
1188 return 0;
1189 msleep(10);
1190 }
1191
1192 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1193 "current device state %d.\n", !put_to_sleep, current_state);
1194
1195 return -EBUSY;
1196 }
1197
1198 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1199 enum dev_state state)
1200 {
1201 int retval = 0;
1202
1203 switch (state) {
1204 case STATE_RADIO_ON:
1205 retval = rt73usb_enable_radio(rt2x00dev);
1206 break;
1207 case STATE_RADIO_OFF:
1208 rt73usb_disable_radio(rt2x00dev);
1209 break;
1210 case STATE_RADIO_RX_ON:
1211 case STATE_RADIO_RX_ON_LINK:
1212 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1213 break;
1214 case STATE_RADIO_RX_OFF:
1215 case STATE_RADIO_RX_OFF_LINK:
1216 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1217 break;
1218 case STATE_DEEP_SLEEP:
1219 case STATE_SLEEP:
1220 case STATE_STANDBY:
1221 case STATE_AWAKE:
1222 retval = rt73usb_set_state(rt2x00dev, state);
1223 break;
1224 default:
1225 retval = -ENOTSUPP;
1226 break;
1227 }
1228
1229 return retval;
1230 }
1231
1232 /*
1233 * TX descriptor initialization
1234 */
1235 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1236 struct sk_buff *skb,
1237 struct txdata_entry_desc *desc,
1238 struct ieee80211_tx_control *control)
1239 {
1240 struct skb_desc *skbdesc = get_skb_desc(skb);
1241 __le32 *txd = skbdesc->desc;
1242 u32 word;
1243
1244 /*
1245 * Start writing the descriptor words.
1246 */
1247 rt2x00_desc_read(txd, 1, &word);
1248 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1249 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1250 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1251 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1252 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1253 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1254 rt2x00_desc_write(txd, 1, word);
1255
1256 rt2x00_desc_read(txd, 2, &word);
1257 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1258 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1259 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1260 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1261 rt2x00_desc_write(txd, 2, word);
1262
1263 rt2x00_desc_read(txd, 5, &word);
1264 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1265 TXPOWER_TO_DEV(control->power_level));
1266 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1267 rt2x00_desc_write(txd, 5, word);
1268
1269 rt2x00_desc_read(txd, 0, &word);
1270 rt2x00_set_field32(&word, TXD_W0_BURST,
1271 test_bit(ENTRY_TXD_BURST, &desc->flags));
1272 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1273 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1274 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1275 rt2x00_set_field32(&word, TXD_W0_ACK,
1276 test_bit(ENTRY_TXD_ACK, &desc->flags));
1277 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1278 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1279 rt2x00_set_field32(&word, TXD_W0_OFDM,
1280 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1281 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1282 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1283 !!(control->flags &
1284 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1285 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1286 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1287 rt2x00_set_field32(&word, TXD_W0_BURST2,
1288 test_bit(ENTRY_TXD_BURST, &desc->flags));
1289 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1290 rt2x00_desc_write(txd, 0, word);
1291 }
1292
1293 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1294 struct sk_buff *skb)
1295 {
1296 int length;
1297
1298 /*
1299 * The length _must_ be a multiple of 4,
1300 * but it must _not_ be a multiple of the USB packet size.
1301 */
1302 length = roundup(skb->len, 4);
1303 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1304
1305 return length;
1306 }
1307
1308 /*
1309 * TX data initialization
1310 */
1311 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1312 unsigned int queue)
1313 {
1314 u32 reg;
1315
1316 if (queue != IEEE80211_TX_QUEUE_BEACON)
1317 return;
1318
1319 /*
1320 * For Wi-Fi faily generated beacons between participating stations.
1321 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1322 */
1323 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1324
1325 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1326 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1327 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1328 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1329 }
1330 }
1331
1332 /*
1333 * RX control handlers
1334 */
1335 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1336 {
1337 u16 eeprom;
1338 u8 offset;
1339 u8 lna;
1340
1341 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1342 switch (lna) {
1343 case 3:
1344 offset = 90;
1345 break;
1346 case 2:
1347 offset = 74;
1348 break;
1349 case 1:
1350 offset = 64;
1351 break;
1352 default:
1353 return 0;
1354 }
1355
1356 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1357 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1358 if (lna == 3 || lna == 2)
1359 offset += 10;
1360 } else {
1361 if (lna == 3)
1362 offset += 6;
1363 else if (lna == 2)
1364 offset += 8;
1365 }
1366
1367 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1368 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1369 } else {
1370 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1371 offset += 14;
1372
1373 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1374 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1375 }
1376
1377 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1378 }
1379
1380 static void rt73usb_fill_rxdone(struct data_entry *entry,
1381 struct rxdata_entry_desc *desc)
1382 {
1383 struct skb_desc *skbdesc = get_skb_desc(entry->skb);
1384 __le32 *rxd = (__le32 *)entry->skb->data;
1385 u32 word0;
1386 u32 word1;
1387
1388 rt2x00_desc_read(rxd, 0, &word0);
1389 rt2x00_desc_read(rxd, 1, &word1);
1390
1391 desc->flags = 0;
1392 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1393 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1394
1395 /*
1396 * Obtain the status about this packet.
1397 */
1398 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1399 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1400 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1401 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1402 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1403
1404 /*
1405 * Set descriptor and data pointer.
1406 */
1407 skbdesc->desc = entry->skb->data;
1408 skbdesc->desc_len = entry->ring->desc_size;
1409 skbdesc->data = entry->skb->data + entry->ring->desc_size;
1410 skbdesc->data_len = desc->size;
1411 }
1412
1413 /*
1414 * Device probe functions.
1415 */
1416 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1417 {
1418 u16 word;
1419 u8 *mac;
1420 s8 value;
1421
1422 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1423
1424 /*
1425 * Start validation of the data that has been read.
1426 */
1427 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1428 if (!is_valid_ether_addr(mac)) {
1429 DECLARE_MAC_BUF(macbuf);
1430
1431 random_ether_addr(mac);
1432 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1433 }
1434
1435 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1436 if (word == 0xffff) {
1437 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1438 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1439 ANTENNA_B);
1440 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1441 ANTENNA_B);
1442 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1443 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1444 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1445 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1446 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1447 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1448 }
1449
1450 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1451 if (word == 0xffff) {
1452 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1453 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1454 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1455 }
1456
1457 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1458 if (word == 0xffff) {
1459 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1460 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1461 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1462 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1463 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1464 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1465 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1466 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1467 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1468 LED_MODE_DEFAULT);
1469 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1470 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1471 }
1472
1473 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1474 if (word == 0xffff) {
1475 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1476 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1477 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1478 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1479 }
1480
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1482 if (word == 0xffff) {
1483 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1484 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1485 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1486 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1487 } else {
1488 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1489 if (value < -10 || value > 10)
1490 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1491 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1492 if (value < -10 || value > 10)
1493 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1494 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1495 }
1496
1497 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1498 if (word == 0xffff) {
1499 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1500 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1501 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1502 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1503 } else {
1504 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1505 if (value < -10 || value > 10)
1506 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1507 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1508 if (value < -10 || value > 10)
1509 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1510 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1511 }
1512
1513 return 0;
1514 }
1515
1516 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1517 {
1518 u32 reg;
1519 u16 value;
1520 u16 eeprom;
1521
1522 /*
1523 * Read EEPROM word for configuration.
1524 */
1525 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1526
1527 /*
1528 * Identify RF chipset.
1529 */
1530 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1531 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1532 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1533
1534 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1535 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1536 return -ENODEV;
1537 }
1538
1539 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1540 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1541 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1542 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1543 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1544 return -ENODEV;
1545 }
1546
1547 /*
1548 * Identify default antenna configuration.
1549 */
1550 rt2x00dev->default_ant.tx =
1551 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1552 rt2x00dev->default_ant.rx =
1553 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1554
1555 /*
1556 * Read the Frame type.
1557 */
1558 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1559 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1560
1561 /*
1562 * Read frequency offset.
1563 */
1564 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1565 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1566
1567 /*
1568 * Read external LNA informations.
1569 */
1570 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1571
1572 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1573 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1574 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1575 }
1576
1577 /*
1578 * Store led settings, for correct led behaviour.
1579 */
1580 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1581
1582 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1583 rt2x00dev->led_mode);
1584 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1585 rt2x00_get_field16(eeprom,
1586 EEPROM_LED_POLARITY_GPIO_0));
1587 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1588 rt2x00_get_field16(eeprom,
1589 EEPROM_LED_POLARITY_GPIO_1));
1590 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1591 rt2x00_get_field16(eeprom,
1592 EEPROM_LED_POLARITY_GPIO_2));
1593 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1594 rt2x00_get_field16(eeprom,
1595 EEPROM_LED_POLARITY_GPIO_3));
1596 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1597 rt2x00_get_field16(eeprom,
1598 EEPROM_LED_POLARITY_GPIO_4));
1599 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1600 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1601 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1602 rt2x00_get_field16(eeprom,
1603 EEPROM_LED_POLARITY_RDY_G));
1604 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1605 rt2x00_get_field16(eeprom,
1606 EEPROM_LED_POLARITY_RDY_A));
1607
1608 return 0;
1609 }
1610
1611 /*
1612 * RF value list for RF2528
1613 * Supports: 2.4 GHz
1614 */
1615 static const struct rf_channel rf_vals_bg_2528[] = {
1616 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1617 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1618 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1619 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1620 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1621 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1622 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1623 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1624 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1625 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1626 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1627 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1628 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1629 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1630 };
1631
1632 /*
1633 * RF value list for RF5226
1634 * Supports: 2.4 GHz & 5.2 GHz
1635 */
1636 static const struct rf_channel rf_vals_5226[] = {
1637 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1638 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1639 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1640 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1641 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1642 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1643 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1644 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1645 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1646 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1647 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1648 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1649 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1650 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1651
1652 /* 802.11 UNI / HyperLan 2 */
1653 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1654 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1655 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1656 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1657 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1658 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1659 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1660 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1661
1662 /* 802.11 HyperLan 2 */
1663 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1664 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1665 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1666 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1667 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1668 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1669 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1670 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1671 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1672 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1673
1674 /* 802.11 UNII */
1675 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1676 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1677 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1678 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1679 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1680 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1681
1682 /* MMAC(Japan)J52 ch 34,38,42,46 */
1683 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1684 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1685 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1686 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1687 };
1688
1689 /*
1690 * RF value list for RF5225 & RF2527
1691 * Supports: 2.4 GHz & 5.2 GHz
1692 */
1693 static const struct rf_channel rf_vals_5225_2527[] = {
1694 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1695 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1696 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1697 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1698 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1699 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1700 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1701 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1702 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1703 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1704 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1705 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1706 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1707 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1708
1709 /* 802.11 UNI / HyperLan 2 */
1710 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1711 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1712 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1713 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1714 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1715 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1716 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1717 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1718
1719 /* 802.11 HyperLan 2 */
1720 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1721 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1722 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1723 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1724 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1725 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1726 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1727 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1728 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1729 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1730
1731 /* 802.11 UNII */
1732 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1733 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1734 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1735 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1736 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1737 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1738
1739 /* MMAC(Japan)J52 ch 34,38,42,46 */
1740 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1741 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1742 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1743 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1744 };
1745
1746
1747 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1748 {
1749 struct hw_mode_spec *spec = &rt2x00dev->spec;
1750 u8 *txpower;
1751 unsigned int i;
1752
1753 /*
1754 * Initialize all hw fields.
1755 */
1756 rt2x00dev->hw->flags =
1757 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1758 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1759 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1760 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1761 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1762 rt2x00dev->hw->queues = 5;
1763
1764 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1765 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1766 rt2x00_eeprom_addr(rt2x00dev,
1767 EEPROM_MAC_ADDR_0));
1768
1769 /*
1770 * Convert tx_power array in eeprom.
1771 */
1772 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1773 for (i = 0; i < 14; i++)
1774 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1775
1776 /*
1777 * Initialize hw_mode information.
1778 */
1779 spec->num_modes = 2;
1780 spec->num_rates = 12;
1781 spec->tx_power_a = NULL;
1782 spec->tx_power_bg = txpower;
1783 spec->tx_power_default = DEFAULT_TXPOWER;
1784
1785 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1786 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1787 spec->channels = rf_vals_bg_2528;
1788 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1789 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1790 spec->channels = rf_vals_5226;
1791 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1792 spec->num_channels = 14;
1793 spec->channels = rf_vals_5225_2527;
1794 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1795 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1796 spec->channels = rf_vals_5225_2527;
1797 }
1798
1799 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1800 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1801 spec->num_modes = 3;
1802
1803 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1804 for (i = 0; i < 14; i++)
1805 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1806
1807 spec->tx_power_a = txpower;
1808 }
1809 }
1810
1811 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1812 {
1813 int retval;
1814
1815 /*
1816 * Allocate eeprom data.
1817 */
1818 retval = rt73usb_validate_eeprom(rt2x00dev);
1819 if (retval)
1820 return retval;
1821
1822 retval = rt73usb_init_eeprom(rt2x00dev);
1823 if (retval)
1824 return retval;
1825
1826 /*
1827 * Initialize hw specifications.
1828 */
1829 rt73usb_probe_hw_mode(rt2x00dev);
1830
1831 /*
1832 * This device requires firmware
1833 */
1834 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1835
1836 /*
1837 * Set the rssi offset.
1838 */
1839 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1840
1841 return 0;
1842 }
1843
1844 /*
1845 * IEEE80211 stack callback functions.
1846 */
1847 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1848 unsigned int changed_flags,
1849 unsigned int *total_flags,
1850 int mc_count,
1851 struct dev_addr_list *mc_list)
1852 {
1853 struct rt2x00_dev *rt2x00dev = hw->priv;
1854 u32 reg;
1855
1856 /*
1857 * Mask off any flags we are going to ignore from
1858 * the total_flags field.
1859 */
1860 *total_flags &=
1861 FIF_ALLMULTI |
1862 FIF_FCSFAIL |
1863 FIF_PLCPFAIL |
1864 FIF_CONTROL |
1865 FIF_OTHER_BSS |
1866 FIF_PROMISC_IN_BSS;
1867
1868 /*
1869 * Apply some rules to the filters:
1870 * - Some filters imply different filters to be set.
1871 * - Some things we can't filter out at all.
1872 * - Multicast filter seems to kill broadcast traffic so never use it.
1873 */
1874 *total_flags |= FIF_ALLMULTI;
1875 if (*total_flags & FIF_OTHER_BSS ||
1876 *total_flags & FIF_PROMISC_IN_BSS)
1877 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1878
1879 /*
1880 * Check if there is any work left for us.
1881 */
1882 if (rt2x00dev->packet_filter == *total_flags)
1883 return;
1884 rt2x00dev->packet_filter = *total_flags;
1885
1886 /*
1887 * When in atomic context, reschedule and let rt2x00lib
1888 * call this function again.
1889 */
1890 if (in_atomic()) {
1891 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1892 return;
1893 }
1894
1895 /*
1896 * Start configuration steps.
1897 * Note that the version error will always be dropped
1898 * and broadcast frames will always be accepted since
1899 * there is no filter for it at this time.
1900 */
1901 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1902 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1903 !(*total_flags & FIF_FCSFAIL));
1904 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1905 !(*total_flags & FIF_PLCPFAIL));
1906 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1907 !(*total_flags & FIF_CONTROL));
1908 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1909 !(*total_flags & FIF_PROMISC_IN_BSS));
1910 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1911 !(*total_flags & FIF_PROMISC_IN_BSS));
1912 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1913 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1914 !(*total_flags & FIF_ALLMULTI));
1915 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1916 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1917 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1918 }
1919
1920 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1921 u32 short_retry, u32 long_retry)
1922 {
1923 struct rt2x00_dev *rt2x00dev = hw->priv;
1924 u32 reg;
1925
1926 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1927 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1928 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1929 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1930
1931 return 0;
1932 }
1933
1934 #if 0
1935 /*
1936 * Mac80211 demands get_tsf must be atomic.
1937 * This is not possible for rt73usb since all register access
1938 * functions require sleeping. Untill mac80211 no longer needs
1939 * get_tsf to be atomic, this function should be disabled.
1940 */
1941 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1942 {
1943 struct rt2x00_dev *rt2x00dev = hw->priv;
1944 u64 tsf;
1945 u32 reg;
1946
1947 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1948 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1949 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1950 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1951
1952 return tsf;
1953 }
1954 #else
1955 #define rt73usb_get_tsf NULL
1956 #endif
1957
1958 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1959 {
1960 struct rt2x00_dev *rt2x00dev = hw->priv;
1961
1962 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1963 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1964 }
1965
1966 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1967 struct ieee80211_tx_control *control)
1968 {
1969 struct rt2x00_dev *rt2x00dev = hw->priv;
1970 struct skb_desc *desc;
1971 struct data_ring *ring;
1972 struct data_entry *entry;
1973 int timeout;
1974
1975 /*
1976 * Just in case the ieee80211 doesn't set this,
1977 * but we need this queue set for the descriptor
1978 * initialization.
1979 */
1980 control->queue = IEEE80211_TX_QUEUE_BEACON;
1981 ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
1982 entry = rt2x00_get_data_entry(ring);
1983
1984 /*
1985 * Add the descriptor in front of the skb.
1986 */
1987 skb_push(skb, ring->desc_size);
1988 memset(skb->data, 0, ring->desc_size);
1989
1990 /*
1991 * Fill in skb descriptor
1992 */
1993 desc = get_skb_desc(skb);
1994 desc->desc_len = ring->desc_size;
1995 desc->data_len = skb->len - ring->desc_size;
1996 desc->desc = skb->data;
1997 desc->data = skb->data + ring->desc_size;
1998 desc->ring = ring;
1999 desc->entry = entry;
2000
2001 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2002
2003 /*
2004 * Write entire beacon with descriptor to register,
2005 * and kick the beacon generator.
2006 */
2007 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2008 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2009 USB_VENDOR_REQUEST_OUT,
2010 HW_BEACON_BASE0, 0x0000,
2011 skb->data, skb->len, timeout);
2012 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2013
2014 return 0;
2015 }
2016
2017 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2018 .tx = rt2x00mac_tx,
2019 .start = rt2x00mac_start,
2020 .stop = rt2x00mac_stop,
2021 .add_interface = rt2x00mac_add_interface,
2022 .remove_interface = rt2x00mac_remove_interface,
2023 .config = rt2x00mac_config,
2024 .config_interface = rt2x00mac_config_interface,
2025 .configure_filter = rt73usb_configure_filter,
2026 .get_stats = rt2x00mac_get_stats,
2027 .set_retry_limit = rt73usb_set_retry_limit,
2028 .bss_info_changed = rt2x00mac_bss_info_changed,
2029 .conf_tx = rt2x00mac_conf_tx,
2030 .get_tx_stats = rt2x00mac_get_tx_stats,
2031 .get_tsf = rt73usb_get_tsf,
2032 .reset_tsf = rt73usb_reset_tsf,
2033 .beacon_update = rt73usb_beacon_update,
2034 };
2035
2036 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2037 .probe_hw = rt73usb_probe_hw,
2038 .get_firmware_name = rt73usb_get_firmware_name,
2039 .load_firmware = rt73usb_load_firmware,
2040 .initialize = rt2x00usb_initialize,
2041 .uninitialize = rt2x00usb_uninitialize,
2042 .init_rxentry = rt2x00usb_init_rxentry,
2043 .init_txentry = rt2x00usb_init_txentry,
2044 .set_device_state = rt73usb_set_device_state,
2045 .link_stats = rt73usb_link_stats,
2046 .reset_tuner = rt73usb_reset_tuner,
2047 .link_tuner = rt73usb_link_tuner,
2048 .write_tx_desc = rt73usb_write_tx_desc,
2049 .write_tx_data = rt2x00usb_write_tx_data,
2050 .get_tx_data_len = rt73usb_get_tx_data_len,
2051 .kick_tx_queue = rt73usb_kick_tx_queue,
2052 .fill_rxdone = rt73usb_fill_rxdone,
2053 .config_mac_addr = rt73usb_config_mac_addr,
2054 .config_bssid = rt73usb_config_bssid,
2055 .config_type = rt73usb_config_type,
2056 .config_preamble = rt73usb_config_preamble,
2057 .config = rt73usb_config,
2058 };
2059
2060 static const struct rt2x00_ops rt73usb_ops = {
2061 .name = KBUILD_MODNAME,
2062 .rxd_size = RXD_DESC_SIZE,
2063 .txd_size = TXD_DESC_SIZE,
2064 .eeprom_size = EEPROM_SIZE,
2065 .rf_size = RF_SIZE,
2066 .lib = &rt73usb_rt2x00_ops,
2067 .hw = &rt73usb_mac80211_ops,
2068 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2069 .debugfs = &rt73usb_rt2x00debug,
2070 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2071 };
2072
2073 /*
2074 * rt73usb module information.
2075 */
2076 static struct usb_device_id rt73usb_device_table[] = {
2077 /* AboCom */
2078 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2079 /* Askey */
2080 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2081 /* ASUS */
2082 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2083 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2084 /* Belkin */
2085 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2086 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2087 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2088 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2089 /* Billionton */
2090 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2091 /* Buffalo */
2092 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2093 /* CNet */
2094 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2095 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2096 /* Conceptronic */
2097 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2098 /* D-Link */
2099 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2100 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2101 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2102 /* Gemtek */
2103 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2104 /* Gigabyte */
2105 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2106 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2107 /* Huawei-3Com */
2108 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2109 /* Hercules */
2110 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2111 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2112 /* Linksys */
2113 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2114 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2115 /* MSI */
2116 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2117 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2118 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2119 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2120 /* Ralink */
2121 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2122 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2123 /* Qcom */
2124 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2125 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2126 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2127 /* Senao */
2128 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2129 /* Sitecom */
2130 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2131 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2132 /* Surecom */
2133 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2134 /* Planex */
2135 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2137 { 0, }
2138 };
2139
2140 MODULE_AUTHOR(DRV_PROJECT);
2141 MODULE_VERSION(DRV_VERSION);
2142 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2143 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2144 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2145 MODULE_FIRMWARE(FIRMWARE_RT2571);
2146 MODULE_LICENSE("GPL");
2147
2148 static struct usb_driver rt73usb_driver = {
2149 .name = KBUILD_MODNAME,
2150 .id_table = rt73usb_device_table,
2151 .probe = rt2x00usb_probe,
2152 .disconnect = rt2x00usb_disconnect,
2153 .suspend = rt2x00usb_suspend,
2154 .resume = rt2x00usb_resume,
2155 };
2156
2157 static int __init rt73usb_init(void)
2158 {
2159 return usb_register(&rt73usb_driver);
2160 }
2161
2162 static void __exit rt73usb_exit(void)
2163 {
2164 usb_deregister(&rt73usb_driver);
2165 }
2166
2167 module_init(rt73usb_init);
2168 module_exit(rt73usb_exit);
WRT350N Kernel Patches