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x86: arch/x86/mm/init_32.c cleanup
[wrt350n-kernel.git] / drivers / atm / firestream.c
blobc662d686154a1ac64ad5b1c1e7deca1029fce0bc
1
2 /* drivers/atm/firestream.c - FireStream 155 (MB86697) and
3 * FireStream 50 (MB86695) device driver
4 */
5
6 /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
9 */
10
11 /*
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
27 system and in the file COPYING in the Linux kernel source.
28 */
29
30
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/errno.h>
38 #include <linux/atm.h>
39 #include <linux/atmdev.h>
40 #include <linux/sonet.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/delay.h>
44 #include <linux/ioport.h> /* for request_region */
45 #include <linux/uio.h>
46 #include <linux/init.h>
47 #include <linux/capability.h>
48 #include <linux/bitops.h>
49 #include <asm/byteorder.h>
50 #include <asm/system.h>
51 #include <asm/string.h>
52 #include <asm/io.h>
53 #include <asm/atomic.h>
54 #include <asm/uaccess.h>
55 #include <linux/wait.h>
56
57 #include "firestream.h"
58
59 static int loopback = 0;
60 static int num=0x5a;
61
62 /* According to measurements (but they look suspicious to me!) done in
63 * '97, 37% of the packets are one cell in size. So it pays to have
64 * buffers allocated at that size. A large jump in percentage of
65 * packets occurs at packets around 536 bytes in length. So it also
66 * pays to have those pre-allocated. Unfortunately, we can't fully
67 * take advantage of this as the majority of the packets is likely to
68 * be TCP/IP (As where obviously the measurement comes from) There the
69 * link would be opened with say a 1500 byte MTU, and we can't handle
70 * smaller buffers more efficiently than the larger ones. -- REW
71 */
72
73 /* Due to the way Linux memory management works, specifying "576" as
74 * an allocation size here isn't going to help. They are allocated
75 * from 1024-byte regions anyway. With the size of the sk_buffs (quite
76 * large), it doesn't pay to allocate the smallest size (64) -- REW */
77
78 /* This is all guesswork. Hard numbers to back this up or disprove this,
79 * are appreciated. -- REW */
80
81 /* The last entry should be about 64k. However, the "buffer size" is
82 * passed to the chip in a 16 bit field. I don't know how "65536"
83 * would be interpreted. -- REW */
84
85 #define NP FS_NR_FREE_POOLS
86 static int rx_buf_sizes[NP] = {128, 256, 512, 1024, 2048, 4096, 16384, 65520};
87 /* log2: 7 8 9 10 11 12 14 16 */
88
89 #if 0
90 static int rx_pool_sizes[NP] = {1024, 1024, 512, 256, 128, 64, 32, 32};
91 #else
92 /* debug */
93 static int rx_pool_sizes[NP] = {128, 128, 128, 64, 64, 64, 32, 32};
94 #endif
95 /* log2: 10 10 9 8 7 6 5 5 */
96 /* sumlog2: 17 18 18 18 18 18 19 21 */
97 /* mem allocated: 128k 256k 256k 256k 256k 256k 512k 2M */
98 /* tot mem: almost 4M */
99
100 /* NP is shorter, so that it fits on a single line. */
101 #undef NP
102
103
104 /* Small hardware gotcha:
105
106 The FS50 CAM (VP/VC match registers) always take the lowest channel
107 number that matches. This is not a problem.
108
109 However, they also ignore whether the channel is enabled or
110 not. This means that if you allocate channel 0 to 1.2 and then
111 channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
112 match channel for channel 0 will "steal" the traffic from channel
113 1, even if you correctly disable channel 0.
114
115 Workaround:
116
117 - When disabling channels, write an invalid VP/VC value to the
118 match register. (We use 0xffffffff, which in the worst case
119 matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
120 anything as some "when not in use, program to 0" bits are now
121 programmed to 1...)
122
123 - Don't initialize the match registers to 0, as 0.0 is a valid
124 channel.
125 */
126
127
128 /* Optimization hints and tips.
129
130 The FireStream chips are very capable of reducing the amount of
131 "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
132 action. You could try to minimize this a bit.
133
134 Besides that, the userspace->kernel copy and the PCI bus are the
135 performance limiting issues for this driver.
136
137 You could queue up a bunch of outgoing packets without telling the
138 FireStream. I'm not sure that's going to win you much though. The
139 Linux layer won't tell us in advance when it's not going to give us
140 any more packets in a while. So this is tricky to implement right without
141 introducing extra delays.
142
143 -- REW
144 */
145
146
147
148
149 /* The strings that define what the RX queue entry is all about. */
150 /* Fujitsu: Please tell me which ones can have a pointer to a
151 freepool descriptor! */
152 static char *res_strings[] = {
153 "RX OK: streaming not EOP",
154 "RX OK: streaming EOP",
155 "RX OK: Single buffer packet",
156 "RX OK: packet mode",
157 "RX OK: F4 OAM (end to end)",
158 "RX OK: F4 OAM (Segment)",
159 "RX OK: F5 OAM (end to end)",
160 "RX OK: F5 OAM (Segment)",
161 "RX OK: RM cell",
162 "RX OK: TRANSP cell",
163 "RX OK: TRANSPC cell",
164 "Unmatched cell",
165 "reserved 12",
166 "reserved 13",
167 "reserved 14",
168 "Unrecognized cell",
169 "reserved 16",
170 "reassemby abort: AAL5 abort",
171 "packet purged",
172 "packet ageing timeout",
173 "channel ageing timeout",
174 "calculated length error",
175 "programmed length limit error",
176 "aal5 crc32 error",
177 "oam transp or transpc crc10 error",
178 "reserved 25",
179 "reserved 26",
180 "reserved 27",
181 "reserved 28",
182 "reserved 29",
183 "reserved 30",
184 "reassembly abort: no buffers",
185 "receive buffer overflow",
186 "change in GFC",
187 "receive buffer full",
188 "low priority discard - no receive descriptor",
189 "low priority discard - missing end of packet",
190 "reserved 41",
191 "reserved 42",
192 "reserved 43",
193 "reserved 44",
194 "reserved 45",
195 "reserved 46",
196 "reserved 47",
197 "reserved 48",
198 "reserved 49",
199 "reserved 50",
200 "reserved 51",
201 "reserved 52",
202 "reserved 53",
203 "reserved 54",
204 "reserved 55",
205 "reserved 56",
206 "reserved 57",
207 "reserved 58",
208 "reserved 59",
209 "reserved 60",
210 "reserved 61",
211 "reserved 62",
212 "reserved 63",
213 };
214
215 static char *irq_bitname[] = {
216 "LPCO",
217 "DPCO",
218 "RBRQ0_W",
219 "RBRQ1_W",
220 "RBRQ2_W",
221 "RBRQ3_W",
222 "RBRQ0_NF",
223 "RBRQ1_NF",
224 "RBRQ2_NF",
225 "RBRQ3_NF",
226 "BFP_SC",
227 "INIT",
228 "INIT_ERR",
229 "USCEO",
230 "UPEC0",
231 "VPFCO",
232 "CRCCO",
233 "HECO",
234 "TBRQ_W",
235 "TBRQ_NF",
236 "CTPQ_E",
237 "GFC_C0",
238 "PCI_FTL",
239 "CSQ_W",
240 "CSQ_NF",
241 "EXT_INT",
242 "RXDMA_S"
243 };
244
245
246 #define PHY_EOF -1
247 #define PHY_CLEARALL -2
248
249 struct reginit_item {
250 int reg, val;
251 };
252
253
254 static struct reginit_item PHY_NTC_INIT[] __devinitdata = {
255 { PHY_CLEARALL, 0x40 },
256 { 0x12, 0x0001 },
257 { 0x13, 0x7605 },
258 { 0x1A, 0x0001 },
259 { 0x1B, 0x0005 },
260 { 0x38, 0x0003 },
261 { 0x39, 0x0006 }, /* changed here to make loopback */
262 { 0x01, 0x5262 },
263 { 0x15, 0x0213 },
264 { 0x00, 0x0003 },
265 { PHY_EOF, 0}, /* -1 signals end of list */
266 };
267
268
269 /* Safetyfeature: If the card interrupts more than this number of times
270 in a jiffy (1/100th of a second) then we just disable the interrupt and
271 print a message. This prevents the system from hanging.
272
273 150000 packets per second is close to the limit a PC is going to have
274 anyway. We therefore have to disable this for production. -- REW */
275 #undef IRQ_RATE_LIMIT // 100
276
277 /* Interrupts work now. Unlike serial cards, ATM cards don't work all
278 that great without interrupts. -- REW */
279 #undef FS_POLL_FREQ // 100
280
281 /*
282 This driver can spew a whole lot of debugging output at you. If you
283 need maximum performance, you should disable the DEBUG define. To
284 aid in debugging in the field, I'm leaving the compile-time debug
285 features enabled, and disable them "runtime". That allows me to
286 instruct people with problems to enable debugging without requiring
287 them to recompile... -- REW
288 */
289 #define DEBUG
290
291 #ifdef DEBUG
292 #define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
293 #else
294 #define fs_dprintk(f, str...) /* nothing */
295 #endif
296
297
298 static int fs_keystream = 0;
299
300 #ifdef DEBUG
301 /* I didn't forget to set this to zero before shipping. Hit me with a stick
302 if you get this with the debug default not set to zero again. -- REW */
303 static int fs_debug = 0;
304 #else
305 #define fs_debug 0
306 #endif
307
308 #ifdef MODULE
309 #ifdef DEBUG
310 module_param(fs_debug, int, 0644);
311 #endif
312 module_param(loopback, int, 0);
313 module_param(num, int, 0);
314 module_param(fs_keystream, int, 0);
315 /* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
316 #endif
317
318
319 #define FS_DEBUG_FLOW 0x00000001
320 #define FS_DEBUG_OPEN 0x00000002
321 #define FS_DEBUG_QUEUE 0x00000004
322 #define FS_DEBUG_IRQ 0x00000008
323 #define FS_DEBUG_INIT 0x00000010
324 #define FS_DEBUG_SEND 0x00000020
325 #define FS_DEBUG_PHY 0x00000040
326 #define FS_DEBUG_CLEANUP 0x00000080
327 #define FS_DEBUG_QOS 0x00000100
328 #define FS_DEBUG_TXQ 0x00000200
329 #define FS_DEBUG_ALLOC 0x00000400
330 #define FS_DEBUG_TXMEM 0x00000800
331 #define FS_DEBUG_QSIZE 0x00001000
332
333
334 #define func_enter() fs_dprintk (FS_DEBUG_FLOW, "fs: enter %s\n", __FUNCTION__)
335 #define func_exit() fs_dprintk (FS_DEBUG_FLOW, "fs: exit %s\n", __FUNCTION__)
336
337
338 static struct fs_dev *fs_boards = NULL;
339
340 #ifdef DEBUG
341
342 static void my_hd (void *addr, int len)
343 {
344 int j, ch;
345 unsigned char *ptr = addr;
346
347 while (len > 0) {
348 printk ("%p ", ptr);
349 for (j=0;j < ((len < 16)?len:16);j++) {
350 printk ("%02x %s", ptr[j], (j==7)?" ":"");
351 }
352 for ( ;j < 16;j++) {
353 printk (" %s", (j==7)?" ":"");
354 }
355 for (j=0;j < ((len < 16)?len:16);j++) {
356 ch = ptr[j];
357 printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
358 }
359 printk ("\n");
360 ptr += 16;
361 len -= 16;
362 }
363 }
364 #else /* DEBUG */
365 static void my_hd (void *addr, int len){}
366 #endif /* DEBUG */
367
368 /********** free an skb (as per ATM device driver documentation) **********/
369
370 /* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
371 * I copied it over from the ambassador driver. -- REW */
372
373 static inline void fs_kfree_skb (struct sk_buff * skb)
374 {
375 if (ATM_SKB(skb)->vcc->pop)
376 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
377 else
378 dev_kfree_skb_any (skb);
379 }
380
381
382
383
384 /* It seems the ATM forum recommends this horribly complicated 16bit
385 * floating point format. Turns out the Ambassador uses the exact same
386 * encoding. I just copied it over. If Mitch agrees, I'll move it over
387 * to the atm_misc file or something like that. (and remove it from
388 * here and the ambassador driver) -- REW
389 */
390
391 /* The good thing about this format is that it is monotonic. So,
392 a conversion routine need not be very complicated. To be able to
393 round "nearest" we need to take along a few extra bits. Lets
394 put these after 16 bits, so that we can just return the top 16
395 bits of the 32bit number as the result:
396
397 int mr (unsigned int rate, int r)
398 {
399 int e = 16+9;
400 static int round[4]={0, 0, 0xffff, 0x8000};
401 if (!rate) return 0;
402 while (rate & 0xfc000000) {
403 rate >>= 1;
404 e++;
405 }
406 while (! (rate & 0xfe000000)) {
407 rate <<= 1;
408 e--;
409 }
410
411 // Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
412 rate &= ~0x02000000;
413 // Next add in the exponent
414 rate |= e << (16+9);
415 // And perform the rounding:
416 return (rate + round[r]) >> 16;
417 }
418
419 14 lines-of-code. Compare that with the 120 that the Ambassador
420 guys needed. (would be 8 lines shorter if I'd try to really reduce
421 the number of lines:
422
423 int mr (unsigned int rate, int r)
424 {
425 int e = 16+9;
426 static int round[4]={0, 0, 0xffff, 0x8000};
427 if (!rate) return 0;
428 for (; rate & 0xfc000000 ;rate >>= 1, e++);
429 for (;!(rate & 0xfe000000);rate <<= 1, e--);
430 return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
431 }
432
433 Exercise for the reader: Remove one more line-of-code, without
434 cheating. (Just joining two lines is cheating). (I know it's
435 possible, don't think you've beat me if you found it... If you
436 manage to lose two lines or more, keep me updated! ;-)
437
438 -- REW */
439
440
441 #define ROUND_UP 1
442 #define ROUND_DOWN 2
443 #define ROUND_NEAREST 3
444 /********** make rate (not quite as much fun as Horizon) **********/
445
446 static unsigned int make_rate (unsigned int rate, int r,
447 u16 * bits, unsigned int * actual)
448 {
449 unsigned char exp = -1; /* hush gcc */
450 unsigned int man = -1; /* hush gcc */
451
452 fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
453
454 /* rates in cells per second, ITU format (nasty 16-bit floating-point)
455 given 5-bit e and 9-bit m:
456 rate = EITHER (1+m/2^9)*2^e OR 0
457 bits = EITHER 1<<14 | e<<9 | m OR 0
458 (bit 15 is "reserved", bit 14 "non-zero")
459 smallest rate is 0 (special representation)
460 largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
461 smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
462 simple algorithm:
463 find position of top bit, this gives e
464 remove top bit and shift (rounding if feeling clever) by 9-e
465 */
466 /* Ambassador ucode bug: please don't set bit 14! so 0 rate not
467 representable. // This should move into the ambassador driver
468 when properly merged. -- REW */
469
470 if (rate > 0xffc00000U) {
471 /* larger than largest representable rate */
472
473 if (r == ROUND_UP) {
474 return -EINVAL;
475 } else {
476 exp = 31;
477 man = 511;
478 }
479
480 } else if (rate) {
481 /* representable rate */
482
483 exp = 31;
484 man = rate;
485
486 /* invariant: rate = man*2^(exp-31) */
487 while (!(man & (1<<31))) {
488 exp = exp - 1;
489 man = man<<1;
490 }
491
492 /* man has top bit set
493 rate = (2^31+(man-2^31))*2^(exp-31)
494 rate = (1+(man-2^31)/2^31)*2^exp
495 */
496 man = man<<1;
497 man &= 0xffffffffU; /* a nop on 32-bit systems */
498 /* rate = (1+man/2^32)*2^exp
499
500 exp is in the range 0 to 31, man is in the range 0 to 2^32-1
501 time to lose significance... we want m in the range 0 to 2^9-1
502 rounding presents a minor problem... we first decide which way
503 we are rounding (based on given rounding direction and possibly
504 the bits of the mantissa that are to be discarded).
505 */
506
507 switch (r) {
508 case ROUND_DOWN: {
509 /* just truncate */
510 man = man>>(32-9);
511 break;
512 }
513 case ROUND_UP: {
514 /* check all bits that we are discarding */
515 if (man & (~0U>>9)) {
516 man = (man>>(32-9)) + 1;
517 if (man == (1<<9)) {
518 /* no need to check for round up outside of range */
519 man = 0;
520 exp += 1;
521 }
522 } else {
523 man = (man>>(32-9));
524 }
525 break;
526 }
527 case ROUND_NEAREST: {
528 /* check msb that we are discarding */
529 if (man & (1<<(32-9-1))) {
530 man = (man>>(32-9)) + 1;
531 if (man == (1<<9)) {
532 /* no need to check for round up outside of range */
533 man = 0;
534 exp += 1;
535 }
536 } else {
537 man = (man>>(32-9));
538 }
539 break;
540 }
541 }
542
543 } else {
544 /* zero rate - not representable */
545
546 if (r == ROUND_DOWN) {
547 return -EINVAL;
548 } else {
549 exp = 0;
550 man = 0;
551 }
552 }
553
554 fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
555
556 if (bits)
557 *bits = /* (1<<14) | */ (exp<<9) | man;
558
559 if (actual)
560 *actual = (exp >= 9)
561 ? (1 << exp) + (man << (exp-9))
562 : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
563
564 return 0;
565 }
566
567
568
569
570 /* FireStream access routines */
571 /* For DEEP-DOWN debugging these can be rigged to intercept accesses to
572 certain registers or to just log all accesses. */
573
574 static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
575 {
576 writel (val, dev->base + offset);
577 }
578
579
580 static inline u32 read_fs (struct fs_dev *dev, int offset)
581 {
582 return readl (dev->base + offset);
583 }
584
585
586
587 static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
588 {
589 return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
590 }
591
592
593 static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
594 {
595 u32 wp;
596 struct FS_QENTRY *cqe;
597
598 /* XXX Sanity check: the write pointer can be checked to be
599 still the same as the value passed as qe... -- REW */
600 /* udelay (5); */
601 while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
602 fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n",
603 q->offset);
604 schedule ();
605 }
606
607 wp &= ~0xf;
608 cqe = bus_to_virt (wp);
609 if (qe != cqe) {
610 fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
611 }
612
613 write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
614
615 {
616 static int c;
617 if (!(c++ % 100))
618 {
619 int rp, wp;
620 rp = read_fs (dev, Q_RP(q->offset));
621 wp = read_fs (dev, Q_WP(q->offset));
622 fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n",
623 q->offset, rp, wp, wp-rp);
624 }
625 }
626 }
627
628 #ifdef DEBUG_EXTRA
629 static struct FS_QENTRY pq[60];
630 static int qp;
631
632 static struct FS_BPENTRY dq[60];
633 static int qd;
634 static void *da[60];
635 #endif
636
637 static void submit_queue (struct fs_dev *dev, struct queue *q,
638 u32 cmd, u32 p1, u32 p2, u32 p3)
639 {
640 struct FS_QENTRY *qe;
641
642 qe = get_qentry (dev, q);
643 qe->cmd = cmd;
644 qe->p0 = p1;
645 qe->p1 = p2;
646 qe->p2 = p3;
647 submit_qentry (dev, q, qe);
648
649 #ifdef DEBUG_EXTRA
650 pq[qp].cmd = cmd;
651 pq[qp].p0 = p1;
652 pq[qp].p1 = p2;
653 pq[qp].p2 = p3;
654 qp++;
655 if (qp >= 60) qp = 0;
656 #endif
657 }
658
659 /* Test the "other" way one day... -- REW */
660 #if 1
661 #define submit_command submit_queue
662 #else
663
664 static void submit_command (struct fs_dev *dev, struct queue *q,
665 u32 cmd, u32 p1, u32 p2, u32 p3)
666 {
667 write_fs (dev, CMDR0, cmd);
668 write_fs (dev, CMDR1, p1);
669 write_fs (dev, CMDR2, p2);
670 write_fs (dev, CMDR3, p3);
671 }
672 #endif
673
674
675
676 static void process_return_queue (struct fs_dev *dev, struct queue *q)
677 {
678 long rq;
679 struct FS_QENTRY *qe;
680 void *tc;
681
682 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
683 fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq);
684 qe = bus_to_virt (rq);
685
686 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n",
687 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
688
689 switch (STATUS_CODE (qe)) {
690 case 5:
691 tc = bus_to_virt (qe->p0);
692 fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
693 kfree (tc);
694 break;
695 }
696
697 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
698 }
699 }
700
701
702 static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
703 {
704 long rq;
705 long tmp;
706 struct FS_QENTRY *qe;
707 struct sk_buff *skb;
708 struct FS_BPENTRY *td;
709
710 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
711 fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq);
712 qe = bus_to_virt (rq);
713
714 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n",
715 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
716
717 if (STATUS_CODE (qe) != 2)
718 fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n",
719 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
720
721
722 switch (STATUS_CODE (qe)) {
723 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
724 /* Fall through */
725 case 0x02:
726 /* Process a real txdone entry. */
727 tmp = qe->p0;
728 if (tmp & 0x0f)
729 printk (KERN_WARNING "td not aligned: %ld\n", tmp);
730 tmp &= ~0x0f;
731 td = bus_to_virt (tmp);
732
733 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n",
734 td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
735
736 skb = td->skb;
737 if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
738 wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
739 FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
740 }
741 td->dev->ntxpckts--;
742
743 {
744 static int c=0;
745
746 if (!(c++ % 100)) {
747 fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
748 }
749 }
750
751 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
752
753 fs_dprintk (FS_DEBUG_TXMEM, "i");
754 fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
755 fs_kfree_skb (skb);
756
757 fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td);
758 memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
759 kfree (td);
760 break;
761 default:
762 /* Here we get the tx purge inhibit command ... */
763 /* Action, I believe, is "don't do anything". -- REW */
764 ;
765 }
766
767 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
768 }
769 }
770
771
772 static void process_incoming (struct fs_dev *dev, struct queue *q)
773 {
774 long rq;
775 struct FS_QENTRY *qe;
776 struct FS_BPENTRY *pe;
777 struct sk_buff *skb;
778 unsigned int channo;
779 struct atm_vcc *atm_vcc;
780
781 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
782 fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq);
783 qe = bus_to_virt (rq);
784
785 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. ",
786 qe->cmd, qe->p0, qe->p1, qe->p2);
787
788 fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n",
789 STATUS_CODE (qe),
790 res_strings[STATUS_CODE(qe)]);
791
792 pe = bus_to_virt (qe->p0);
793 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n",
794 pe->flags, pe->next, pe->bsa, pe->aal_bufsize,
795 pe->skb, pe->fp);
796
797 channo = qe->cmd & 0xffff;
798
799 if (channo < dev->nchannels)
800 atm_vcc = dev->atm_vccs[channo];
801 else
802 atm_vcc = NULL;
803
804 /* Single buffer packet */
805 switch (STATUS_CODE (qe)) {
806 case 0x1:
807 /* Fall through for streaming mode */
808 case 0x2:/* Packet received OK.... */
809 if (atm_vcc) {
810 skb = pe->skb;
811 pe->fp->n--;
812 #if 0
813 fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
814 if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
815 #endif
816 skb_put (skb, qe->p1 & 0xffff);
817 ATM_SKB(skb)->vcc = atm_vcc;
818 atomic_inc(&atm_vcc->stats->rx);
819 __net_timestamp(skb);
820 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
821 atm_vcc->push (atm_vcc, skb);
822 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
823 kfree (pe);
824 } else {
825 printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
826 }
827 break;
828 case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
829 has been consumed and needs to be processed. -- REW */
830 if (qe->p1 & 0xffff) {
831 pe = bus_to_virt (qe->p0);
832 pe->fp->n--;
833 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
834 dev_kfree_skb_any (pe->skb);
835 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
836 kfree (pe);
837 }
838 if (atm_vcc)
839 atomic_inc(&atm_vcc->stats->rx_drop);
840 break;
841 case 0x1f: /* Reassembly abort: no buffers. */
842 /* Silently increment error counter. */
843 if (atm_vcc)
844 atomic_inc(&atm_vcc->stats->rx_drop);
845 break;
846 default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
847 printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n",
848 STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
849 }
850 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
851 }
852 }
853
854
855
856 #define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
857
858 static int fs_open(struct atm_vcc *atm_vcc)
859 {
860 struct fs_dev *dev;
861 struct fs_vcc *vcc;
862 struct fs_transmit_config *tc;
863 struct atm_trafprm * txtp;
864 struct atm_trafprm * rxtp;
865 /* struct fs_receive_config *rc;*/
866 /* struct FS_QENTRY *qe; */
867 int error;
868 int bfp;
869 int to;
870 unsigned short tmc0;
871 short vpi = atm_vcc->vpi;
872 int vci = atm_vcc->vci;
873
874 func_enter ();
875
876 dev = FS_DEV(atm_vcc->dev);
877 fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n",
878 dev, atm_vcc);
879
880 if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
881 set_bit(ATM_VF_ADDR, &atm_vcc->flags);
882
883 if ((atm_vcc->qos.aal != ATM_AAL5) &&
884 (atm_vcc->qos.aal != ATM_AAL2))
885 return -EINVAL; /* XXX AAL0 */
886
887 fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n",
888 atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);
889
890 /* XXX handle qos parameters (rate limiting) ? */
891
892 vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
893 fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%Zd)\n", vcc, sizeof(struct fs_vcc));
894 if (!vcc) {
895 clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
896 return -ENOMEM;
897 }
898
899 atm_vcc->dev_data = vcc;
900 vcc->last_skb = NULL;
901
902 init_waitqueue_head (&vcc->close_wait);
903
904 txtp = &atm_vcc->qos.txtp;
905 rxtp = &atm_vcc->qos.rxtp;
906
907 if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
908 if (IS_FS50(dev)) {
909 /* Increment the channel numer: take a free one next time. */
910 for (to=33;to;to--, dev->channo++) {
911 /* We only have 32 channels */
912 if (dev->channo >= 32)
913 dev->channo = 0;
914 /* If we need to do RX, AND the RX is inuse, try the next */
915 if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
916 continue;
917 /* If we need to do TX, AND the TX is inuse, try the next */
918 if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
919 continue;
920 /* Ok, both are free! (or not needed) */
921 break;
922 }
923 if (!to) {
924 printk ("No more free channels for FS50..\n");
925 return -EBUSY;
926 }
927 vcc->channo = dev->channo;
928 dev->channo &= dev->channel_mask;
929
930 } else {
931 vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
932 if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
933 ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
934 printk ("Channel is in use for FS155.\n");
935 return -EBUSY;
936 }
937 }
938 fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n",
939 vcc->channo, vcc->channo);
940 }
941
942 if (DO_DIRECTION (txtp)) {
943 tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
944 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%Zd)\n",
945 tc, sizeof (struct fs_transmit_config));
946 if (!tc) {
947 fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
948 return -ENOMEM;
949 }
950
951 /* Allocate the "open" entry from the high priority txq. This makes
952 it most likely that the chip will notice it. It also prevents us
953 from having to wait for completion. On the other hand, we may
954 need to wait for completion anyway, to see if it completed
955 successfully. */
956
957 switch (atm_vcc->qos.aal) {
958 case ATM_AAL2:
959 case ATM_AAL0:
960 tc->flags = 0
961 | TC_FLAGS_TRANSPARENT_PAYLOAD
962 | TC_FLAGS_PACKET
963 | (1 << 28)
964 | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
965 | TC_FLAGS_CAL0;
966 break;
967 case ATM_AAL5:
968 tc->flags = 0
969 | TC_FLAGS_AAL5
970 | TC_FLAGS_PACKET /* ??? */
971 | TC_FLAGS_TYPE_CBR
972 | TC_FLAGS_CAL0;
973 break;
974 default:
975 printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
976 tc->flags = 0;
977 }
978 /* Docs are vague about this atm_hdr field. By the way, the FS
979 * chip makes odd errors if lower bits are set.... -- REW */
980 tc->atm_hdr = (vpi << 20) | (vci << 4);
981 {
982 int pcr = atm_pcr_goal (txtp);
983
984 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
985
986 /* XXX Hmm. officially we're only allowed to do this if rounding
987 is round_down -- REW */
988 if (IS_FS50(dev)) {
989 if (pcr > 51840000/53/8) pcr = 51840000/53/8;
990 } else {
991 if (pcr > 155520000/53/8) pcr = 155520000/53/8;
992 }
993 if (!pcr) {
994 /* no rate cap */
995 tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
996 } else {
997 int r;
998 if (pcr < 0) {
999 r = ROUND_DOWN;
1000 pcr = -pcr;
1001 } else {
1002 r = ROUND_UP;
1003 }
1004 error = make_rate (pcr, r, &tmc0, NULL);
1005 if (error) {
1006 kfree(tc);
1007 return error;
1008 }
1009 }
1010 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
1011 }
1012
1013 tc->TMC[0] = tmc0 | 0x4000;
1014 tc->TMC[1] = 0; /* Unused */
1015 tc->TMC[2] = 0; /* Unused */
1016 tc->TMC[3] = 0; /* Unused */
1017
1018 tc->spec = 0; /* UTOPIA address, UDF, HEC: Unused -> 0 */
1019 tc->rtag[0] = 0; /* What should I do with routing tags???
1020 -- Not used -- AS -- Thanks -- REW*/
1021 tc->rtag[1] = 0;
1022 tc->rtag[2] = 0;
1023
1024 if (fs_debug & FS_DEBUG_OPEN) {
1025 fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
1026 my_hd (tc, sizeof (*tc));
1027 }
1028
1029 /* We now use the "submit_command" function to submit commands to
1030 the firestream. There is a define up near the definition of
1031 that routine that switches this routine between immediate write
1032 to the immediate comamnd registers and queuing the commands in
1033 the HPTXQ for execution. This last technique might be more
1034 efficient if we know we're going to submit a whole lot of
1035 commands in one go, but this driver is not setup to be able to
1036 use such a construct. So it probably doen't matter much right
1037 now. -- REW */
1038
1039 /* The command is IMMediate and INQueue. The parameters are out-of-line.. */
1040 submit_command (dev, &dev->hp_txq,
1041 QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
1042 virt_to_bus (tc), 0, 0);
1043
1044 submit_command (dev, &dev->hp_txq,
1045 QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
1046 0, 0, 0);
1047 set_bit (vcc->channo, dev->tx_inuse);
1048 }
1049
1050 if (DO_DIRECTION (rxtp)) {
1051 dev->atm_vccs[vcc->channo] = atm_vcc;
1052
1053 for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
1054 if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
1055 if (bfp >= FS_NR_FREE_POOLS) {
1056 fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n",
1057 atm_vcc->qos.rxtp.max_sdu);
1058 /* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
1059
1060 /* XXX clear tx inuse. Close TX part? */
1061 dev->atm_vccs[vcc->channo] = NULL;
1062 kfree (vcc);
1063 return -EINVAL;
1064 }
1065
1066 switch (atm_vcc->qos.aal) {
1067 case ATM_AAL0:
1068 case ATM_AAL2:
1069 submit_command (dev, &dev->hp_txq,
1070 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1071 RC_FLAGS_TRANSP |
1072 RC_FLAGS_BFPS_BFP * bfp |
1073 RC_FLAGS_RXBM_PSB, 0, 0);
1074 break;
1075 case ATM_AAL5:
1076 submit_command (dev, &dev->hp_txq,
1077 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1078 RC_FLAGS_AAL5 |
1079 RC_FLAGS_BFPS_BFP * bfp |
1080 RC_FLAGS_RXBM_PSB, 0, 0);
1081 break;
1082 };
1083 if (IS_FS50 (dev)) {
1084 submit_command (dev, &dev->hp_txq,
1085 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1086 0x80 + vcc->channo,
1087 (vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
1088 }
1089 submit_command (dev, &dev->hp_txq,
1090 QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
1091 0, 0, 0);
1092 }
1093
1094 /* Indicate we're done! */
1095 set_bit(ATM_VF_READY, &atm_vcc->flags);
1096
1097 func_exit ();
1098 return 0;
1099 }
1100
1101
1102 static void fs_close(struct atm_vcc *atm_vcc)
1103 {
1104 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1105 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1106 struct atm_trafprm * txtp;
1107 struct atm_trafprm * rxtp;
1108
1109 func_enter ();
1110
1111 clear_bit(ATM_VF_READY, &atm_vcc->flags);
1112
1113 fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
1114 if (vcc->last_skb) {
1115 fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n",
1116 vcc->last_skb);
1117 /* We're going to wait for the last packet to get sent on this VC. It would
1118 be impolite not to send them don't you think?
1119 XXX
1120 We don't know which packets didn't get sent. So if we get interrupted in
1121 this sleep_on, we'll lose any reference to these packets. Memory leak!
1122 On the other hand, it's awfully convenient that we can abort a "close" that
1123 is taking too long. Maybe just use non-interruptible sleep on? -- REW */
1124 interruptible_sleep_on (& vcc->close_wait);
1125 }
1126
1127 txtp = &atm_vcc->qos.txtp;
1128 rxtp = &atm_vcc->qos.rxtp;
1129
1130
1131 /* See App note XXX (Unpublished as of now) for the reason for the
1132 removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
1133
1134 if (DO_DIRECTION (txtp)) {
1135 submit_command (dev, &dev->hp_txq,
1136 QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
1137 clear_bit (vcc->channo, dev->tx_inuse);
1138 }
1139
1140 if (DO_DIRECTION (rxtp)) {
1141 submit_command (dev, &dev->hp_txq,
1142 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1143 dev->atm_vccs [vcc->channo] = NULL;
1144
1145 /* This means that this is configured as a receive channel */
1146 if (IS_FS50 (dev)) {
1147 /* Disable the receive filter. Is 0/0 indeed an invalid receive
1148 channel? -- REW. Yes it is. -- Hang. Ok. I'll use -1
1149 (0xfff...) -- REW */
1150 submit_command (dev, &dev->hp_txq,
1151 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1152 0x80 + vcc->channo, -1, 0 );
1153 }
1154 }
1155
1156 fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
1157 kfree (vcc);
1158
1159 func_exit ();
1160 }
1161
1162
1163 static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
1164 {
1165 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1166 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1167 struct FS_BPENTRY *td;
1168
1169 func_enter ();
1170
1171 fs_dprintk (FS_DEBUG_TXMEM, "I");
1172 fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n",
1173 atm_vcc, skb, vcc, dev);
1174
1175 fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
1176
1177 ATM_SKB(skb)->vcc = atm_vcc;
1178
1179 vcc->last_skb = skb;
1180
1181 td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
1182 fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%Zd)\n", td, sizeof (struct FS_BPENTRY));
1183 if (!td) {
1184 /* Oops out of mem */
1185 return -ENOMEM;
1186 }
1187
1188 fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n",
1189 *(int *) skb->data);
1190
1191 td->flags = TD_EPI | TD_DATA | skb->len;
1192 td->next = 0;
1193 td->bsa = virt_to_bus (skb->data);
1194 td->skb = skb;
1195 td->dev = dev;
1196 dev->ntxpckts++;
1197
1198 #ifdef DEBUG_EXTRA
1199 da[qd] = td;
1200 dq[qd].flags = td->flags;
1201 dq[qd].next = td->next;
1202 dq[qd].bsa = td->bsa;
1203 dq[qd].skb = td->skb;
1204 dq[qd].dev = td->dev;
1205 qd++;
1206 if (qd >= 60) qd = 0;
1207 #endif
1208
1209 submit_queue (dev, &dev->hp_txq,
1210 QE_TRANSMIT_DE | vcc->channo,
1211 virt_to_bus (td), 0,
1212 virt_to_bus (td));
1213
1214 fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n",
1215 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1216 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1217 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1218 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1219
1220 func_exit ();
1221 return 0;
1222 }
1223
1224
1225 /* Some function placeholders for functions we don't yet support. */
1226
1227 #if 0
1228 static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1229 {
1230 func_enter ();
1231 func_exit ();
1232 return -ENOIOCTLCMD;
1233 }
1234
1235
1236 static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
1237 void __user *optval,int optlen)
1238 {
1239 func_enter ();
1240 func_exit ();
1241 return 0;
1242 }
1243
1244
1245 static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
1246 void __user *optval,int optlen)
1247 {
1248 func_enter ();
1249 func_exit ();
1250 return 0;
1251 }
1252
1253
1254 static void fs_phy_put(struct atm_dev *dev,unsigned char value,
1255 unsigned long addr)
1256 {
1257 func_enter ();
1258 func_exit ();
1259 }
1260
1261
1262 static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
1263 {
1264 func_enter ();
1265 func_exit ();
1266 return 0;
1267 }
1268
1269
1270 static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1271 {
1272 func_enter ();
1273 func_exit ();
1274 return 0;
1275 };
1276
1277 #endif
1278
1279
1280 static const struct atmdev_ops ops = {
1281 .open = fs_open,
1282 .close = fs_close,
1283 .send = fs_send,
1284 .owner = THIS_MODULE,
1285 /* ioctl: fs_ioctl, */
1286 /* getsockopt: fs_getsockopt, */
1287 /* setsockopt: fs_setsockopt, */
1288 /* change_qos: fs_change_qos, */
1289
1290 /* For now implement these internally here... */
1291 /* phy_put: fs_phy_put, */
1292 /* phy_get: fs_phy_get, */
1293 };
1294
1295
1296 static void __devinit undocumented_pci_fix (struct pci_dev *pdev)
1297 {
1298 u32 tint;
1299
1300 /* The Windows driver says: */
1301 /* Switch off FireStream Retry Limit Threshold
1302 */
1303
1304 /* The register at 0x28 is documented as "reserved", no further
1305 comments. */
1306
1307 pci_read_config_dword (pdev, 0x28, &tint);
1308 if (tint != 0x80) {
1309 tint = 0x80;
1310 pci_write_config_dword (pdev, 0x28, tint);
1311 }
1312 }
1313
1314
1315
1316 /**************************************************************************
1317 * PHY routines *
1318 **************************************************************************/
1319
1320 static void __devinit write_phy (struct fs_dev *dev, int regnum, int val)
1321 {
1322 submit_command (dev, &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
1323 regnum, val, 0);
1324 }
1325
1326 static int __devinit init_phy (struct fs_dev *dev, struct reginit_item *reginit)
1327 {
1328 int i;
1329
1330 func_enter ();
1331 while (reginit->reg != PHY_EOF) {
1332 if (reginit->reg == PHY_CLEARALL) {
1333 /* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
1334 for (i=0;i<reginit->val;i++) {
1335 write_phy (dev, i, 0);
1336 }
1337 } else {
1338 write_phy (dev, reginit->reg, reginit->val);
1339 }
1340 reginit++;
1341 }
1342 func_exit ();
1343 return 0;
1344 }
1345
1346 static void reset_chip (struct fs_dev *dev)
1347 {
1348 int i;
1349
1350 write_fs (dev, SARMODE0, SARMODE0_SRTS0);
1351
1352 /* Undocumented delay */
1353 udelay (128);
1354
1355 /* The "internal registers are documented to all reset to zero, but
1356 comments & code in the Windows driver indicates that the pools are
1357 NOT reset. */
1358 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1359 write_fs (dev, FP_CNF (RXB_FP(i)), 0);
1360 write_fs (dev, FP_SA (RXB_FP(i)), 0);
1361 write_fs (dev, FP_EA (RXB_FP(i)), 0);
1362 write_fs (dev, FP_CNT (RXB_FP(i)), 0);
1363 write_fs (dev, FP_CTU (RXB_FP(i)), 0);
1364 }
1365
1366 /* The same goes for the match channel registers, although those are
1367 NOT documented that way in the Windows driver. -- REW */
1368 /* The Windows driver DOES write 0 to these registers somewhere in
1369 the init sequence. However, a small hardware-feature, will
1370 prevent reception of data on VPI/VCI = 0/0 (Unless the channel
1371 allocated happens to have no disabled channels that have a lower
1372 number. -- REW */
1373
1374 /* Clear the match channel registers. */
1375 if (IS_FS50 (dev)) {
1376 for (i=0;i<FS50_NR_CHANNELS;i++) {
1377 write_fs (dev, 0x200 + i * 4, -1);
1378 }
1379 }
1380 }
1381
1382 static void __devinit *aligned_kmalloc (int size, gfp_t flags, int alignment)
1383 {
1384 void *t;
1385
1386 if (alignment <= 0x10) {
1387 t = kmalloc (size, flags);
1388 if ((unsigned long)t & (alignment-1)) {
1389 printk ("Kmalloc doesn't align things correctly! %p\n", t);
1390 kfree (t);
1391 return aligned_kmalloc (size, flags, alignment * 4);
1392 }
1393 return t;
1394 }
1395 printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
1396 return NULL;
1397 }
1398
1399 static int __devinit init_q (struct fs_dev *dev,
1400 struct queue *txq, int queue, int nentries, int is_rq)
1401 {
1402 int sz = nentries * sizeof (struct FS_QENTRY);
1403 struct FS_QENTRY *p;
1404
1405 func_enter ();
1406
1407 fs_dprintk (FS_DEBUG_INIT, "Inititing queue at %x: %d entries:\n",
1408 queue, nentries);
1409
1410 p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
1411 fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
1412
1413 if (!p) return 0;
1414
1415 write_fs (dev, Q_SA(queue), virt_to_bus(p));
1416 write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
1417 write_fs (dev, Q_WP(queue), virt_to_bus(p));
1418 write_fs (dev, Q_RP(queue), virt_to_bus(p));
1419 if (is_rq) {
1420 /* Configuration for the receive queue: 0: interrupt immediately,
1421 no pre-warning to empty queues: We do our best to keep the
1422 queue filled anyway. */
1423 write_fs (dev, Q_CNF(queue), 0 );
1424 }
1425
1426 txq->sa = p;
1427 txq->ea = p;
1428 txq->offset = queue;
1429
1430 func_exit ();
1431 return 1;
1432 }
1433
1434
1435 static int __devinit init_fp (struct fs_dev *dev,
1436 struct freepool *fp, int queue, int bufsize, int nr_buffers)
1437 {
1438 func_enter ();
1439
1440 fs_dprintk (FS_DEBUG_INIT, "Inititing free pool at %x:\n", queue);
1441
1442 write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
1443 write_fs (dev, FP_SA(queue), 0);
1444 write_fs (dev, FP_EA(queue), 0);
1445 write_fs (dev, FP_CTU(queue), 0);
1446 write_fs (dev, FP_CNT(queue), 0);
1447
1448 fp->offset = queue;
1449 fp->bufsize = bufsize;
1450 fp->nr_buffers = nr_buffers;
1451
1452 func_exit ();
1453 return 1;
1454 }
1455
1456
1457 static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
1458 {
1459 #if 0
1460 /* This seems to be unreliable.... */
1461 return read_fs (dev, FP_CNT (fp->offset));
1462 #else
1463 return fp->n;
1464 #endif
1465 }
1466
1467
1468 /* Check if this gets going again if a pool ever runs out. -- Yes, it
1469 does. I've seen "receive abort: no buffers" and things started
1470 working again after that... -- REW */
1471
1472 static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
1473 gfp_t gfp_flags)
1474 {
1475 struct FS_BPENTRY *qe, *ne;
1476 struct sk_buff *skb;
1477 int n = 0;
1478 u32 qe_tmp;
1479
1480 fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n",
1481 fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n,
1482 fp->nr_buffers);
1483 while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
1484
1485 skb = alloc_skb (fp->bufsize, gfp_flags);
1486 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
1487 if (!skb) break;
1488 ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
1489 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%Zd)\n", ne, sizeof (struct FS_BPENTRY));
1490 if (!ne) {
1491 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
1492 dev_kfree_skb_any (skb);
1493 break;
1494 }
1495
1496 fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ",
1497 skb, ne, skb->data, skb->head);
1498 n++;
1499 ne->flags = FP_FLAGS_EPI | fp->bufsize;
1500 ne->next = virt_to_bus (NULL);
1501 ne->bsa = virt_to_bus (skb->data);
1502 ne->aal_bufsize = fp->bufsize;
1503 ne->skb = skb;
1504 ne->fp = fp;
1505
1506 /*
1507 * FIXME: following code encodes and decodes
1508 * machine pointers (could be 64-bit) into a
1509 * 32-bit register.
1510 */
1511
1512 qe_tmp = read_fs (dev, FP_EA(fp->offset));
1513 fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
1514 if (qe_tmp) {
1515 qe = bus_to_virt ((long) qe_tmp);
1516 qe->next = virt_to_bus(ne);
1517 qe->flags &= ~FP_FLAGS_EPI;
1518 } else
1519 write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
1520
1521 write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
1522 fp->n++; /* XXX Atomic_inc? */
1523 write_fs (dev, FP_CTU(fp->offset), 1);
1524 }
1525
1526 fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
1527 }
1528
1529 static void __devexit free_queue (struct fs_dev *dev, struct queue *txq)
1530 {
1531 func_enter ();
1532
1533 write_fs (dev, Q_SA(txq->offset), 0);
1534 write_fs (dev, Q_EA(txq->offset), 0);
1535 write_fs (dev, Q_RP(txq->offset), 0);
1536 write_fs (dev, Q_WP(txq->offset), 0);
1537 /* Configuration ? */
1538
1539 fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
1540 kfree (txq->sa);
1541
1542 func_exit ();
1543 }
1544
1545 static void __devexit free_freepool (struct fs_dev *dev, struct freepool *fp)
1546 {
1547 func_enter ();
1548
1549 write_fs (dev, FP_CNF(fp->offset), 0);
1550 write_fs (dev, FP_SA (fp->offset), 0);
1551 write_fs (dev, FP_EA (fp->offset), 0);
1552 write_fs (dev, FP_CNT(fp->offset), 0);
1553 write_fs (dev, FP_CTU(fp->offset), 0);
1554
1555 func_exit ();
1556 }
1557
1558
1559
1560 static irqreturn_t fs_irq (int irq, void *dev_id)
1561 {
1562 int i;
1563 u32 status;
1564 struct fs_dev *dev = dev_id;
1565
1566 status = read_fs (dev, ISR);
1567 if (!status)
1568 return IRQ_NONE;
1569
1570 func_enter ();
1571
1572 #ifdef IRQ_RATE_LIMIT
1573 /* Aaargh! I'm ashamed. This costs more lines-of-code than the actual
1574 interrupt routine!. (Well, used to when I wrote that comment) -- REW */
1575 {
1576 static int lastjif;
1577 static int nintr=0;
1578
1579 if (lastjif == jiffies) {
1580 if (++nintr > IRQ_RATE_LIMIT) {
1581 free_irq (dev->irq, dev_id);
1582 printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n",
1583 dev->irq);
1584 }
1585 } else {
1586 lastjif = jiffies;
1587 nintr = 0;
1588 }
1589 }
1590 #endif
1591 fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n",
1592 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1593 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1594 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1595 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1596
1597 /* print the bits in the ISR register. */
1598 if (fs_debug & FS_DEBUG_IRQ) {
1599 /* The FS_DEBUG things are unnecessary here. But this way it is
1600 clear for grep that these are debug prints. */
1601 fs_dprintk (FS_DEBUG_IRQ, "IRQ status:");
1602 for (i=0;i<27;i++)
1603 if (status & (1 << i))
1604 fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
1605 fs_dprintk (FS_DEBUG_IRQ, "\n");
1606 }
1607
1608 if (status & ISR_RBRQ0_W) {
1609 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
1610 process_incoming (dev, &dev->rx_rq[0]);
1611 /* items mentioned on RBRQ0 are from FP 0 or 1. */
1612 top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
1613 top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
1614 }
1615
1616 if (status & ISR_RBRQ1_W) {
1617 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
1618 process_incoming (dev, &dev->rx_rq[1]);
1619 top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
1620 top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
1621 }
1622
1623 if (status & ISR_RBRQ2_W) {
1624 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
1625 process_incoming (dev, &dev->rx_rq[2]);
1626 top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
1627 top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
1628 }
1629
1630 if (status & ISR_RBRQ3_W) {
1631 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
1632 process_incoming (dev, &dev->rx_rq[3]);
1633 top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
1634 top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
1635 }
1636
1637 if (status & ISR_CSQ_W) {
1638 fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
1639 process_return_queue (dev, &dev->st_q);
1640 }
1641
1642 if (status & ISR_TBRQ_W) {
1643 fs_dprintk (FS_DEBUG_IRQ, "Data tramsitted!\n");
1644 process_txdone_queue (dev, &dev->tx_relq);
1645 }
1646
1647 func_exit ();
1648 return IRQ_HANDLED;
1649 }
1650
1651
1652 #ifdef FS_POLL_FREQ
1653 static void fs_poll (unsigned long data)
1654 {
1655 struct fs_dev *dev = (struct fs_dev *) data;
1656
1657 fs_irq (0, dev);
1658 dev->timer.expires = jiffies + FS_POLL_FREQ;
1659 add_timer (&dev->timer);
1660 }
1661 #endif
1662
1663 static int __devinit fs_init (struct fs_dev *dev)
1664 {
1665 struct pci_dev *pci_dev;
1666 int isr, to;
1667 int i;
1668
1669 func_enter ();
1670 pci_dev = dev->pci_dev;
1671
1672 printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
1673 IS_FS50(dev)?50:155,
1674 (unsigned long long)pci_resource_start(pci_dev, 0),
1675 dev->pci_dev->irq);
1676
1677 if (fs_debug & FS_DEBUG_INIT)
1678 my_hd ((unsigned char *) dev, sizeof (*dev));
1679
1680 undocumented_pci_fix (pci_dev);
1681
1682 dev->hw_base = pci_resource_start(pci_dev, 0);
1683
1684 dev->base = ioremap(dev->hw_base, 0x1000);
1685
1686 reset_chip (dev);
1687
1688 write_fs (dev, SARMODE0, 0
1689 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1690 | (1 * SARMODE0_INTMODE_READCLEAR)
1691 | (1 * SARMODE0_CWRE)
1692 | IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1693 SARMODE0_PRPWT_FS155_3
1694 | (1 * SARMODE0_CALSUP_1)
1695 | IS_FS50 (dev)?(0
1696 | SARMODE0_RXVCS_32
1697 | SARMODE0_ABRVCS_32
1698 | SARMODE0_TXVCS_32):
1699 (0
1700 | SARMODE0_RXVCS_1k
1701 | SARMODE0_ABRVCS_1k
1702 | SARMODE0_TXVCS_1k));
1703
1704 /* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
1705 1ms. */
1706 to = 100;
1707 while (--to) {
1708 isr = read_fs (dev, ISR);
1709
1710 /* This bit is documented as "RESERVED" */
1711 if (isr & ISR_INIT_ERR) {
1712 printk (KERN_ERR "Error initializing the FS... \n");
1713 goto unmap;
1714 }
1715 if (isr & ISR_INIT) {
1716 fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
1717 break;
1718 }
1719
1720 /* Try again after 10ms. */
1721 msleep(10);
1722 }
1723
1724 if (!to) {
1725 printk (KERN_ERR "timeout initializing the FS... \n");
1726 goto unmap;
1727 }
1728
1729 /* XXX fix for fs155 */
1730 dev->channel_mask = 0x1f;
1731 dev->channo = 0;
1732
1733 /* AN3: 10 */
1734 write_fs (dev, SARMODE1, 0
1735 | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
1736 | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
1737 | (1 * SARMODE1_DCRM)
1738 | (1 * SARMODE1_DCOAM)
1739 | (0 * SARMODE1_OAMCRC)
1740 | (0 * SARMODE1_DUMPE)
1741 | (0 * SARMODE1_GPLEN)
1742 | (0 * SARMODE1_GNAM)
1743 | (0 * SARMODE1_GVAS)
1744 | (0 * SARMODE1_GPAS)
1745 | (1 * SARMODE1_GPRI)
1746 | (0 * SARMODE1_PMS)
1747 | (0 * SARMODE1_GFCR)
1748 | (1 * SARMODE1_HECM2)
1749 | (1 * SARMODE1_HECM1)
1750 | (1 * SARMODE1_HECM0)
1751 | (1 << 12) /* That's what hang's driver does. Program to 0 */
1752 | (0 * 0xff) /* XXX FS155 */);
1753
1754
1755 /* Cal prescale etc */
1756
1757 /* AN3: 11 */
1758 write_fs (dev, TMCONF, 0x0000000f);
1759 write_fs (dev, CALPRESCALE, 0x01010101 * num);
1760 write_fs (dev, 0x80, 0x000F00E4);
1761
1762 /* AN3: 12 */
1763 write_fs (dev, CELLOSCONF, 0
1764 | ( 0 * CELLOSCONF_CEN)
1765 | ( CELLOSCONF_SC1)
1766 | (0x80 * CELLOSCONF_COBS)
1767 | (num * CELLOSCONF_COPK) /* Changed from 0xff to 0x5a */
1768 | (num * CELLOSCONF_COST));/* after a hint from Hang.
1769 * performance jumped 50->70... */
1770
1771 /* Magic value by Hang */
1772 write_fs (dev, CELLOSCONF_COST, 0x0B809191);
1773
1774 if (IS_FS50 (dev)) {
1775 write_fs (dev, RAS0, RAS0_DCD_XHLT);
1776 dev->atm_dev->ci_range.vpi_bits = 12;
1777 dev->atm_dev->ci_range.vci_bits = 16;
1778 dev->nchannels = FS50_NR_CHANNELS;
1779 } else {
1780 write_fs (dev, RAS0, RAS0_DCD_XHLT
1781 | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
1782 | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
1783 /* We can chose the split arbitarily. We might be able to
1784 support more. Whatever. This should do for now. */
1785 dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
1786 dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
1787
1788 /* Address bits we can't use should be compared to 0. */
1789 write_fs (dev, RAC, 0);
1790
1791 /* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
1792 * too. I can't find ASF1 anywhere. Anyway, we AND with just the
1793 * other bits, then compare with 0, which is exactly what we
1794 * want. */
1795 write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
1796 dev->nchannels = FS155_NR_CHANNELS;
1797 }
1798 dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
1799 GFP_KERNEL);
1800 fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%Zd)\n",
1801 dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
1802
1803 if (!dev->atm_vccs) {
1804 printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
1805 /* XXX Clean up..... */
1806 goto unmap;
1807 }
1808
1809 dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
1810 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n",
1811 dev->atm_vccs, dev->nchannels / 8);
1812
1813 if (!dev->tx_inuse) {
1814 printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
1815 /* XXX Clean up..... */
1816 goto unmap;
1817 }
1818 /* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
1819 /* -- RAS2 : FS50 only: Default is OK. */
1820
1821 /* DMAMODE, default should be OK. -- REW */
1822 write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
1823
1824 init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
1825 init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
1826 init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
1827 init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
1828
1829 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1830 init_fp (dev, &dev->rx_fp[i], RXB_FP(i),
1831 rx_buf_sizes[i], rx_pool_sizes[i]);
1832 top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
1833 }
1834
1835
1836 for (i=0;i < FS_NR_RX_QUEUES;i++)
1837 init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
1838
1839 dev->irq = pci_dev->irq;
1840 if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
1841 printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
1842 /* XXX undo all previous stuff... */
1843 goto unmap;
1844 }
1845 fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
1846
1847 /* We want to be notified of most things. Just the statistics count
1848 overflows are not interesting */
1849 write_fs (dev, IMR, 0
1850 | ISR_RBRQ0_W
1851 | ISR_RBRQ1_W
1852 | ISR_RBRQ2_W
1853 | ISR_RBRQ3_W
1854 | ISR_TBRQ_W
1855 | ISR_CSQ_W);
1856
1857 write_fs (dev, SARMODE0, 0
1858 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1859 | (1 * SARMODE0_GINT)
1860 | (1 * SARMODE0_INTMODE_READCLEAR)
1861 | (0 * SARMODE0_CWRE)
1862 | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1863 SARMODE0_PRPWT_FS155_3)
1864 | (1 * SARMODE0_CALSUP_1)
1865 | (IS_FS50 (dev)?(0
1866 | SARMODE0_RXVCS_32
1867 | SARMODE0_ABRVCS_32
1868 | SARMODE0_TXVCS_32):
1869 (0
1870 | SARMODE0_RXVCS_1k
1871 | SARMODE0_ABRVCS_1k
1872 | SARMODE0_TXVCS_1k))
1873 | (1 * SARMODE0_RUN));
1874
1875 init_phy (dev, PHY_NTC_INIT);
1876
1877 if (loopback == 2) {
1878 write_phy (dev, 0x39, 0x000e);
1879 }
1880
1881 #ifdef FS_POLL_FREQ
1882 init_timer (&dev->timer);
1883 dev->timer.data = (unsigned long) dev;
1884 dev->timer.function = fs_poll;
1885 dev->timer.expires = jiffies + FS_POLL_FREQ;
1886 add_timer (&dev->timer);
1887 #endif
1888
1889 dev->atm_dev->dev_data = dev;
1890
1891 func_exit ();
1892 return 0;
1893 unmap:
1894 iounmap(dev->base);
1895 return 1;
1896 }
1897
1898 static int __devinit firestream_init_one (struct pci_dev *pci_dev,
1899 const struct pci_device_id *ent)
1900 {
1901 struct atm_dev *atm_dev;
1902 struct fs_dev *fs_dev;
1903
1904 if (pci_enable_device(pci_dev))
1905 goto err_out;
1906
1907 fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
1908 fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%Zd)\n",
1909 fs_dev, sizeof (struct fs_dev));
1910 if (!fs_dev)
1911 goto err_out;
1912 atm_dev = atm_dev_register("fs", &ops, -1, NULL);
1913 if (!atm_dev)
1914 goto err_out_free_fs_dev;
1915
1916 fs_dev->pci_dev = pci_dev;
1917 fs_dev->atm_dev = atm_dev;
1918 fs_dev->flags = ent->driver_data;
1919
1920 if (fs_init(fs_dev))
1921 goto err_out_free_atm_dev;
1922
1923 fs_dev->next = fs_boards;
1924 fs_boards = fs_dev;
1925 return 0;
1926
1927 err_out_free_atm_dev:
1928 atm_dev_deregister(atm_dev);
1929 err_out_free_fs_dev:
1930 kfree(fs_dev);
1931 err_out:
1932 return -ENODEV;
1933 }
1934
1935 static void __devexit firestream_remove_one (struct pci_dev *pdev)
1936 {
1937 int i;
1938 struct fs_dev *dev, *nxtdev;
1939 struct fs_vcc *vcc;
1940 struct FS_BPENTRY *fp, *nxt;
1941
1942 func_enter ();
1943
1944 #if 0
1945 printk ("hptxq:\n");
1946 for (i=0;i<60;i++) {
1947 printk ("%d: %08x %08x %08x %08x \n",
1948 i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
1949 qp++;
1950 if (qp >= 60) qp = 0;
1951 }
1952
1953 printk ("descriptors:\n");
1954 for (i=0;i<60;i++) {
1955 printk ("%d: %p: %08x %08x %p %p\n",
1956 i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
1957 qd++;
1958 if (qd >= 60) qd = 0;
1959 }
1960 #endif
1961
1962 for (dev = fs_boards;dev != NULL;dev=nxtdev) {
1963 fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
1964
1965 /* XXX Hit all the tx channels too! */
1966
1967 for (i=0;i < dev->nchannels;i++) {
1968 if (dev->atm_vccs[i]) {
1969 vcc = FS_VCC (dev->atm_vccs[i]);
1970 submit_command (dev, &dev->hp_txq,
1971 QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1972 submit_command (dev, &dev->hp_txq,
1973 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1974
1975 }
1976 }
1977
1978 /* XXX Wait a while for the chip to release all buffers. */
1979
1980 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1981 for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
1982 !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
1983 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1984 dev_kfree_skb_any (fp->skb);
1985 nxt = bus_to_virt (fp->next);
1986 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1987 kfree (fp);
1988 }
1989 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1990 dev_kfree_skb_any (fp->skb);
1991 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1992 kfree (fp);
1993 }
1994
1995 /* Hang the chip in "reset", prevent it clobbering memory that is
1996 no longer ours. */
1997 reset_chip (dev);
1998
1999 fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
2000 free_irq (dev->irq, dev);
2001 del_timer (&dev->timer);
2002
2003 atm_dev_deregister(dev->atm_dev);
2004 free_queue (dev, &dev->hp_txq);
2005 free_queue (dev, &dev->lp_txq);
2006 free_queue (dev, &dev->tx_relq);
2007 free_queue (dev, &dev->st_q);
2008
2009 fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
2010 kfree (dev->atm_vccs);
2011
2012 for (i=0;i< FS_NR_FREE_POOLS;i++)
2013 free_freepool (dev, &dev->rx_fp[i]);
2014
2015 for (i=0;i < FS_NR_RX_QUEUES;i++)
2016 free_queue (dev, &dev->rx_rq[i]);
2017
2018 iounmap(dev->base);
2019 fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
2020 nxtdev = dev->next;
2021 kfree (dev);
2022 }
2023
2024 func_exit ();
2025 }
2026
2027 static struct pci_device_id firestream_pci_tbl[] = {
2028 { PCI_VENDOR_ID_FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50,
2029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FS_IS50},
2030 { PCI_VENDOR_ID_FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155,
2031 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FS_IS155},
2032 { 0, }
2033 };
2034
2035 MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
2036
2037 static struct pci_driver firestream_driver = {
2038 .name = "firestream",
2039 .id_table = firestream_pci_tbl,
2040 .probe = firestream_init_one,
2041 .remove = __devexit_p(firestream_remove_one),
2042 };
2043
2044 static int __init firestream_init_module (void)
2045 {
2046 int error;
2047
2048 func_enter ();
2049 error = pci_register_driver(&firestream_driver);
2050 func_exit ();
2051 return error;
2052 }
2053
2054 static void __exit firestream_cleanup_module(void)
2055 {
2056 pci_unregister_driver(&firestream_driver);
2057 }
2058
2059 module_init(firestream_init_module);
2060 module_exit(firestream_cleanup_module);
2061
2062 MODULE_LICENSE("GPL");
2063
2064
2065
WRT350N Kernel Patches