include/asm-i386/pgtable-3level.h

   1 #ifndef _I386_PGTABLE_3LEVEL_H
   2 #define _I386_PGTABLE_3LEVEL_H
   3
   4 /*
   5  * Intel Physical Address Extension (PAE) Mode - three-level page
   6  * tables on PPro+ CPUs.
   7  *
   8  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
   9  */
  10
  11 #define pte_ERROR(e) \
  12         printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
  13 #define pmd_ERROR(e) \
  14         printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
  15 #define pgd_ERROR(e) \
  16         printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
  17
  18 #define pud_none(pud)                           0
  19 #define pud_bad(pud)                            0
  20 #define pud_present(pud)                        1
  21
  22 /*
  23  * Is the pte executable?
  24  */
  25 static inline int pte_x(pte_t pte)
  26 {
  27         return !(pte_val(pte) & _PAGE_NX);
  28 }
  29
  30 /*
  31  * All present user-pages with !NX bit are user-executable:
  32  */
  33 static inline int pte_exec(pte_t pte)
  34 {
  35         return pte_user(pte) && pte_x(pte);
  36 }
  37 /*
  38  * All present pages with !NX bit are kernel-executable:
  39  */
  40 static inline int pte_exec_kernel(pte_t pte)
  41 {
  42         return pte_x(pte);
  43 }
  44
  45 #ifndef CONFIG_PARAVIRT
  46 /* Rules for using set_pte: the pte being assigned *must* be
  47  * either not present or in a state where the hardware will
  48  * not attempt to update the pte.  In places where this is
  49  * not possible, use pte_get_and_clear to obtain the old pte
  50  * value and then use set_pte to update it.  -ben
  51  */
  52 static inline void set_pte(pte_t *ptep, pte_t pte)
  53 {
  54         ptep->pte_high = pte.pte_high;
  55         smp_wmb();
  56         ptep->pte_low = pte.pte_low;
  57 }
  58 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
  59
  60 /*
  61  * Since this is only called on user PTEs, and the page fault handler
  62  * must handle the already racy situation of simultaneous page faults,
  63  * we are justified in merely clearing the PTE present bit, followed
  64  * by a set.  The ordering here is important.
  65  */
  66 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
  67 {
  68         ptep->pte_low = 0;
  69         smp_wmb();
  70         ptep->pte_high = pte.pte_high;
  71         smp_wmb();
  72         ptep->pte_low = pte.pte_low;
  73 }
  74
  75 #define set_pte_atomic(pteptr,pteval) \
  76                 set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
  77 #define set_pmd(pmdptr,pmdval) \
  78                 set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
  79 #define set_pud(pudptr,pudval) \
  80                 (*(pudptr) = (pudval))
  81
  82 /*
  83  * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
  84  * entry, so clear the bottom half first and enforce ordering with a compiler
  85  * barrier.
  86  */
  87 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
  88 {
  89         ptep->pte_low = 0;
  90         smp_wmb();
  91         ptep->pte_high = 0;
  92 }
  93
  94 static inline void pmd_clear(pmd_t *pmd)
  95 {
  96         u32 *tmp = (u32 *)pmd;
  97         *tmp = 0;
  98         smp_wmb();
  99         *(tmp + 1) = 0;
 100 }
 101 #endif
 102
 103 /*
 104  * Pentium-II erratum A13: in PAE mode we explicitly have to flush
 105  * the TLB via cr3 if the top-level pgd is changed...
 106  * We do not let the generic code free and clear pgd entries due to
 107  * this erratum.
 108  */
 109 static inline void pud_clear (pud_t * pud) { }
 110
 111 #define pud_page(pud) \
 112 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
 113
 114 #define pud_page_vaddr(pud) \
 115 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
 116
 117
 118 /* Find an entry in the second-level page table.. */
 119 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
 120                         pmd_index(address))
 121
 122 static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
 123 {
 124         pte_t res;
 125
 126         /* xchg acts as a barrier before the setting of the high bits */
 127         res.pte_low = xchg(&ptep->pte_low, 0);
 128         res.pte_high = ptep->pte_high;
 129         ptep->pte_high = 0;
 130
 131         return res;
 132 }
 133
 134 #define __HAVE_ARCH_PTE_SAME
 135 static inline int pte_same(pte_t a, pte_t b)
 136 {
 137         return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
 138 }
 139
 140 #define pte_page(x)     pfn_to_page(pte_pfn(x))
 141
 142 static inline int pte_none(pte_t pte)
 143 {
 144         return !pte.pte_low && !pte.pte_high;
 145 }
 146
 147 static inline unsigned long pte_pfn(pte_t pte)
 148 {
 149         return (pte.pte_low >> PAGE_SHIFT) |
 150                 (pte.pte_high << (32 - PAGE_SHIFT));
 151 }
 152
 153 extern unsigned long long __supported_pte_mask;
 154
 155 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
 156 {
 157         pte_t pte;
 158
 159         pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
 160                                         (pgprot_val(pgprot) >> 32);
 161         pte.pte_high &= (__supported_pte_mask >> 32);
 162         pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
 163                                                         __supported_pte_mask;
 164         return pte;
 165 }
 166
 167 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
 168 {
 169         return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
 170                         pgprot_val(pgprot)) & __supported_pte_mask);
 171 }
 172
 173 /*
 174  * Bits 0, 6 and 7 are taken in the low part of the pte,
 175  * put the 32 bits of offset into the high part.
 176  */
 177 #define pte_to_pgoff(pte) ((pte).pte_high)
 178 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
 179 #define PTE_FILE_MAX_BITS       32
 180
 181 /* Encode and de-code a swap entry */
 182 #define __swp_type(x)                   (((x).val) & 0x1f)
 183 #define __swp_offset(x)                 ((x).val >> 5)
 184 #define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) << 5})
 185 #define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
 186 #define __swp_entry_to_pte(x)           ((pte_t){ 0, (x).val })
 187
 188 #define __pmd_free_tlb(tlb, x)          do { } while (0)
 189
 190 #define vmalloc_sync_all() ((void)0)
 191
 192 #endif /* _I386_PGTABLE_3LEVEL_H */