include/asm-i386/pgtable.h

   1 #ifndef _I386_PGTABLE_H
   2 #define _I386_PGTABLE_H
   3
   4
   5 /*
   6  * The Linux memory management assumes a three-level page table setup. On
   7  * the i386, we use that, but "fold" the mid level into the top-level page
   8  * table, so that we physically have the same two-level page table as the
   9  * i386 mmu expects.
  10  *
  11  * This file contains the functions and defines necessary to modify and use
  12  * the i386 page table tree.
  13  */
  14 #ifndef __ASSEMBLY__
  15 #include <asm/processor.h>
  16 #include <asm/fixmap.h>
  17 #include <linux/threads.h>
  18 #include <asm/paravirt.h>
  19
  20 #ifndef _I386_BITOPS_H
  21 #include <asm/bitops.h>
  22 #endif
  23
  24 #include <linux/slab.h>
  25 #include <linux/list.h>
  26 #include <linux/spinlock.h>
  27
  28 struct mm_struct;
  29 struct vm_area_struct;
  30
  31 /*
  32  * ZERO_PAGE is a global shared page that is always zero: used
  33  * for zero-mapped memory areas etc..
  34  */
  35 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  36 extern unsigned long empty_zero_page[1024];
  37 extern pgd_t swapper_pg_dir[1024];
  38 extern struct kmem_cache *pgd_cache;
  39 extern struct kmem_cache *pmd_cache;
  40 extern spinlock_t pgd_lock;
  41 extern struct page *pgd_list;
  42
  43 void pmd_ctor(void *, struct kmem_cache *, unsigned long);
  44 void pgd_ctor(void *, struct kmem_cache *, unsigned long);
  45 void pgd_dtor(void *, struct kmem_cache *, unsigned long);
  46 void pgtable_cache_init(void);
  47 void paging_init(void);
  48
  49 /*
  50  * The Linux x86 paging architecture is 'compile-time dual-mode', it
  51  * implements both the traditional 2-level x86 page tables and the
  52  * newer 3-level PAE-mode page tables.
  53  */
  54 #ifdef CONFIG_X86_PAE
  55 # include <asm/pgtable-3level-defs.h>
  56 # define PMD_SIZE       (1UL << PMD_SHIFT)
  57 # define PMD_MASK       (~(PMD_SIZE-1))
  58 #else
  59 # include <asm/pgtable-2level-defs.h>
  60 #endif
  61
  62 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  63 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  64
  65 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  66 #define FIRST_USER_ADDRESS      0
  67
  68 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
  69 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
  70
  71 #define TWOLEVEL_PGDIR_SHIFT    22
  72 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
  73 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
  74
  75 /* Just any arbitrary offset to the start of the vmalloc VM area: the
  76  * current 8MB value just means that there will be a 8MB "hole" after the
  77  * physical memory until the kernel virtual memory starts.  That means that
  78  * any out-of-bounds memory accesses will hopefully be caught.
  79  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  80  * area for the same reason. ;)
  81  */
  82 #define VMALLOC_OFFSET  (8*1024*1024)
  83 #define VMALLOC_START   (((unsigned long) high_memory + vmalloc_earlyreserve + \
  84                         2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
  85 #ifdef CONFIG_HIGHMEM
  86 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
  87 #else
  88 # define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
  89 #endif
  90
  91 /*
  92  * _PAGE_PSE set in the page directory entry just means that
  93  * the page directory entry points directly to a 4MB-aligned block of
  94  * memory.
  95  */
  96 #define _PAGE_BIT_PRESENT       0
  97 #define _PAGE_BIT_RW            1
  98 #define _PAGE_BIT_USER          2
  99 #define _PAGE_BIT_PWT           3
 100 #define _PAGE_BIT_PCD           4
 101 #define _PAGE_BIT_ACCESSED      5
 102 #define _PAGE_BIT_DIRTY         6
 103 #define _PAGE_BIT_PSE           7       /* 4 MB (or 2MB) page, Pentium+, if present.. */
 104 #define _PAGE_BIT_GLOBAL        8       /* Global TLB entry PPro+ */
 105 #define _PAGE_BIT_UNUSED1       9       /* available for programmer */
 106 #define _PAGE_BIT_UNUSED2       10
 107 #define _PAGE_BIT_UNUSED3       11
 108 #define _PAGE_BIT_NX            63
 109
 110 #define _PAGE_PRESENT   0x001
 111 #define _PAGE_RW        0x002
 112 #define _PAGE_USER      0x004
 113 #define _PAGE_PWT       0x008
 114 #define _PAGE_PCD       0x010
 115 #define _PAGE_ACCESSED  0x020
 116 #define _PAGE_DIRTY     0x040
 117 #define _PAGE_PSE       0x080   /* 4 MB (or 2MB) page, Pentium+, if present.. */
 118 #define _PAGE_GLOBAL    0x100   /* Global TLB entry PPro+ */
 119 #define _PAGE_UNUSED1   0x200   /* available for programmer */
 120 #define _PAGE_UNUSED2   0x400
 121 #define _PAGE_UNUSED3   0x800
 122
 123 /* If _PAGE_PRESENT is clear, we use these: */
 124 #define _PAGE_FILE      0x040   /* nonlinear file mapping, saved PTE; unset:swap */
 125 #define _PAGE_PROTNONE  0x080   /* if the user mapped it with PROT_NONE;
 126                                    pte_present gives true */
 127 #ifdef CONFIG_X86_PAE
 128 #define _PAGE_NX        (1ULL<<_PAGE_BIT_NX)
 129 #else
 130 #define _PAGE_NX        0
 131 #endif
 132
 133 #define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
 134 #define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
 135 #define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 136
 137 #define PAGE_NONE \
 138         __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
 139 #define PAGE_SHARED \
 140         __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
 141
 142 #define PAGE_SHARED_EXEC \
 143         __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
 144 #define PAGE_COPY_NOEXEC \
 145         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
 146 #define PAGE_COPY_EXEC \
 147         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 148 #define PAGE_COPY \
 149         PAGE_COPY_NOEXEC
 150 #define PAGE_READONLY \
 151         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
 152 #define PAGE_READONLY_EXEC \
 153         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 154
 155 #define _PAGE_KERNEL \
 156         (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
 157 #define _PAGE_KERNEL_EXEC \
 158         (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
 159
 160 extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
 161 #define __PAGE_KERNEL_RO                (__PAGE_KERNEL & ~_PAGE_RW)
 162 #define __PAGE_KERNEL_NOCACHE           (__PAGE_KERNEL | _PAGE_PCD)
 163 #define __PAGE_KERNEL_LARGE             (__PAGE_KERNEL | _PAGE_PSE)
 164 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
 165
 166 #define PAGE_KERNEL             __pgprot(__PAGE_KERNEL)
 167 #define PAGE_KERNEL_RO          __pgprot(__PAGE_KERNEL_RO)
 168 #define PAGE_KERNEL_EXEC        __pgprot(__PAGE_KERNEL_EXEC)
 169 #define PAGE_KERNEL_NOCACHE     __pgprot(__PAGE_KERNEL_NOCACHE)
 170 #define PAGE_KERNEL_LARGE       __pgprot(__PAGE_KERNEL_LARGE)
 171 #define PAGE_KERNEL_LARGE_EXEC  __pgprot(__PAGE_KERNEL_LARGE_EXEC)
 172
 173 /*
 174  * The i386 can't do page protection for execute, and considers that
 175  * the same are read. Also, write permissions imply read permissions.
 176  * This is the closest we can get..
 177  */
 178 #define __P000  PAGE_NONE
 179 #define __P001  PAGE_READONLY
 180 #define __P010  PAGE_COPY
 181 #define __P011  PAGE_COPY
 182 #define __P100  PAGE_READONLY_EXEC
 183 #define __P101  PAGE_READONLY_EXEC
 184 #define __P110  PAGE_COPY_EXEC
 185 #define __P111  PAGE_COPY_EXEC
 186
 187 #define __S000  PAGE_NONE
 188 #define __S001  PAGE_READONLY
 189 #define __S010  PAGE_SHARED
 190 #define __S011  PAGE_SHARED
 191 #define __S100  PAGE_READONLY_EXEC
 192 #define __S101  PAGE_READONLY_EXEC
 193 #define __S110  PAGE_SHARED_EXEC
 194 #define __S111  PAGE_SHARED_EXEC
 195
 196 /*
 197  * Define this if things work differently on an i386 and an i486:
 198  * it will (on an i486) warn about kernel memory accesses that are
 199  * done without a 'access_ok(VERIFY_WRITE,..)'
 200  */
 201 #undef TEST_ACCESS_OK
 202
 203 /* The boot page tables (all created as a single array) */
 204 extern unsigned long pg0[];
 205
 206 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
 207
 208 /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
 209 #define pmd_none(x)     (!(unsigned long)pmd_val(x))
 210 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 211 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
 212
 213
 214 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
 215
 216 /*
 217  * The following only work if pte_present() is true.
 218  * Undefined behaviour if not..
 219  */
 220 static inline int pte_user(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
 221 static inline int pte_read(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
 222 static inline int pte_dirty(pte_t pte)          { return (pte).pte_low & _PAGE_DIRTY; }
 223 static inline int pte_young(pte_t pte)          { return (pte).pte_low & _PAGE_ACCESSED; }
 224 static inline int pte_write(pte_t pte)          { return (pte).pte_low & _PAGE_RW; }
 225 static inline int pte_huge(pte_t pte)           { return (pte).pte_low & _PAGE_PSE; }
 226
 227 /*
 228  * The following only works if pte_present() is not true.
 229  */
 230 static inline int pte_file(pte_t pte)           { return (pte).pte_low & _PAGE_FILE; }
 231
 232 static inline pte_t pte_rdprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_USER; return pte; }
 233 static inline pte_t pte_exprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_USER; return pte; }
 234 static inline pte_t pte_mkclean(pte_t pte)      { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
 235 static inline pte_t pte_mkold(pte_t pte)        { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
 236 static inline pte_t pte_wrprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_RW; return pte; }
 237 static inline pte_t pte_mkread(pte_t pte)       { (pte).pte_low |= _PAGE_USER; return pte; }
 238 static inline pte_t pte_mkexec(pte_t pte)       { (pte).pte_low |= _PAGE_USER; return pte; }
 239 static inline pte_t pte_mkdirty(pte_t pte)      { (pte).pte_low |= _PAGE_DIRTY; return pte; }
 240 static inline pte_t pte_mkyoung(pte_t pte)      { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
 241 static inline pte_t pte_mkwrite(pte_t pte)      { (pte).pte_low |= _PAGE_RW; return pte; }
 242 static inline pte_t pte_mkhuge(pte_t pte)       { (pte).pte_low |= _PAGE_PSE; return pte; }
 243
 244 #ifdef CONFIG_X86_PAE
 245 # include <asm/pgtable-3level.h>
 246 #else
 247 # include <asm/pgtable-2level.h>
 248 #endif
 249
 250 #ifndef CONFIG_PARAVIRT
 251 /*
 252  * Rules for using pte_update - it must be called after any PTE update which
 253  * has not been done using the set_pte / clear_pte interfaces.  It is used by
 254  * shadow mode hypervisors to resynchronize the shadow page tables.  Kernel PTE
 255  * updates should either be sets, clears, or set_pte_atomic for P->P
 256  * transitions, which means this hook should only be called for user PTEs.
 257  * This hook implies a P->P protection or access change has taken place, which
 258  * requires a subsequent TLB flush.  The notification can optionally be delayed
 259  * until the TLB flush event by using the pte_update_defer form of the
 260  * interface, but care must be taken to assure that the flush happens while
 261  * still holding the same page table lock so that the shadow and primary pages
 262  * do not become out of sync on SMP.
 263  */
 264 #define pte_update(mm, addr, ptep)              do { } while (0)
 265 #define pte_update_defer(mm, addr, ptep)        do { } while (0)
 266 #endif
 267
 268 /*
 269  * We only update the dirty/accessed state if we set
 270  * the dirty bit by hand in the kernel, since the hardware
 271  * will do the accessed bit for us, and we don't want to
 272  * race with other CPU's that might be updating the dirty
 273  * bit at the same time.
 274  */
 275 #define  __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 276 #define ptep_set_access_flags(vma, address, ptep, entry, dirty)         \
 277 do {                                                                    \
 278         if (dirty) {                                                    \
 279                 (ptep)->pte_low = (entry).pte_low;                      \
 280                 pte_update_defer((vma)->vm_mm, (address), (ptep));      \
 281                 flush_tlb_page(vma, address);                           \
 282         }                                                               \
 283 } while (0)
 284
 285 /*
 286  * We don't actually have these, but we want to advertise them so that
 287  * we can encompass the flush here.
 288  */
 289 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 290 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 291
 292 /*
 293  * Rules for using ptep_establish: the pte MUST be a user pte, and
 294  * must be a present->present transition.
 295  */
 296 #define __HAVE_ARCH_PTEP_ESTABLISH
 297 #define ptep_establish(vma, address, ptep, pteval)                      \
 298 do {                                                                    \
 299         set_pte_present((vma)->vm_mm, address, ptep, pteval);           \
 300         flush_tlb_page(vma, address);                                   \
 301 } while (0)
 302
 303 #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
 304 #define ptep_clear_flush_dirty(vma, address, ptep)                      \
 305 ({                                                                      \
 306         int __dirty;                                                    \
 307         __dirty = pte_dirty(*(ptep));                                   \
 308         if (__dirty) {                                                  \
 309                 clear_bit(_PAGE_BIT_DIRTY, &(ptep)->pte_low);           \
 310                 pte_update_defer((vma)->vm_mm, (address), (ptep));      \
 311                 flush_tlb_page(vma, address);                           \
 312         }                                                               \
 313         __dirty;                                                        \
 314 })
 315
 316 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 317 #define ptep_clear_flush_young(vma, address, ptep)                      \
 318 ({                                                                      \
 319         int __young;                                                    \
 320         __young = pte_young(*(ptep));                                   \
 321         if (__young) {                                                  \
 322                 clear_bit(_PAGE_BIT_ACCESSED, &(ptep)->pte_low);        \
 323                 pte_update_defer((vma)->vm_mm, (address), (ptep));      \
 324                 flush_tlb_page(vma, address);                           \
 325         }                                                               \
 326         __young;                                                        \
 327 })
 328
 329 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 330 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 331 {
 332         pte_t pte = raw_ptep_get_and_clear(ptep);
 333         pte_update(mm, addr, ptep);
 334         return pte;
 335 }
 336
 337 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 338 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
 339 {
 340         pte_t pte;
 341         if (full) {
 342                 pte = *ptep;
 343                 pte_clear(mm, addr, ptep);
 344         } else {
 345                 pte = ptep_get_and_clear(mm, addr, ptep);
 346         }
 347         return pte;
 348 }
 349
 350 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 351 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 352 {
 353         clear_bit(_PAGE_BIT_RW, &ptep->pte_low);
 354         pte_update(mm, addr, ptep);
 355 }
 356
 357 /*
 358  * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
 359  *
 360  *  dst - pointer to pgd range anwhere on a pgd page
 361  *  src - ""
 362  *  count - the number of pgds to copy.
 363  *
 364  * dst and src can be on the same page, but the range must not overlap,
 365  * and must not cross a page boundary.
 366  */
 367 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
 368 {
 369        memcpy(dst, src, count * sizeof(pgd_t));
 370 }
 371
 372 /*
 373  * Macro to mark a page protection value as "uncacheable".  On processors which do not support
 374  * it, this is a no-op.
 375  */
 376 #define pgprot_noncached(prot)  ((boot_cpu_data.x86 > 3)                                          \
 377                                  ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
 378
 379 /*
 380  * Conversion functions: convert a page and protection to a page entry,
 381  * and a page entry and page directory to the page they refer to.
 382  */
 383
 384 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 385
 386 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 387 {
 388         pte.pte_low &= _PAGE_CHG_MASK;
 389         pte.pte_low |= pgprot_val(newprot);
 390 #ifdef CONFIG_X86_PAE
 391         /*
 392          * Chop off the NX bit (if present), and add the NX portion of
 393          * the newprot (if present):
 394          */
 395         pte.pte_high &= ~(1 << (_PAGE_BIT_NX - 32));
 396         pte.pte_high |= (pgprot_val(newprot) >> 32) & \
 397                                         (__supported_pte_mask >> 32);
 398 #endif
 399         return pte;
 400 }
 401
 402 #define pmd_large(pmd) \
 403 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
 404
 405 /*
 406  * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
 407  *
 408  * this macro returns the index of the entry in the pgd page which would
 409  * control the given virtual address
 410  */
 411 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 412 #define pgd_index_k(addr) pgd_index(addr)
 413
 414 /*
 415  * pgd_offset() returns a (pgd_t *)
 416  * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
 417  */
 418 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
 419
 420 /*
 421  * a shortcut which implies the use of the kernel's pgd, instead
 422  * of a process's
 423  */
 424 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 425
 426 /*
 427  * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
 428  *
 429  * this macro returns the index of the entry in the pmd page which would
 430  * control the given virtual address
 431  */
 432 #define pmd_index(address) \
 433                 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 434
 435 /*
 436  * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
 437  *
 438  * this macro returns the index of the entry in the pte page which would
 439  * control the given virtual address
 440  */
 441 #define pte_index(address) \
 442                 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 443 #define pte_offset_kernel(dir, address) \
 444         ((pte_t *) pmd_page_vaddr(*(dir)) +  pte_index(address))
 445
 446 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 447
 448 #define pmd_page_vaddr(pmd) \
 449                 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 450
 451 /*
 452  * Helper function that returns the kernel pagetable entry controlling
 453  * the virtual address 'address'. NULL means no pagetable entry present.
 454  * NOTE: the return type is pte_t but if the pmd is PSE then we return it
 455  * as a pte too.
 456  */
 457 extern pte_t *lookup_address(unsigned long address);
 458
 459 /*
 460  * Make a given kernel text page executable/non-executable.
 461  * Returns the previous executability setting of that page (which
 462  * is used to restore the previous state). Used by the SMP bootup code.
 463  * NOTE: this is an __init function for security reasons.
 464  */
 465 #ifdef CONFIG_X86_PAE
 466  extern int set_kernel_exec(unsigned long vaddr, int enable);
 467 #else
 468  static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;}
 469 #endif
 470
 471 #if defined(CONFIG_HIGHPTE)
 472 #define pte_offset_map(dir, address) \
 473         ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
 474 #define pte_offset_map_nested(dir, address) \
 475         ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
 476 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
 477 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
 478 #else
 479 #define pte_offset_map(dir, address) \
 480         ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
 481 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
 482 #define pte_unmap(pte) do { } while (0)
 483 #define pte_unmap_nested(pte) do { } while (0)
 484 #endif
 485
 486 /* Clear a kernel PTE and flush it from the TLB */
 487 #define kpte_clear_flush(ptep, vaddr)                                   \
 488 do {                                                                    \
 489         pte_clear(&init_mm, vaddr, ptep);                               \
 490         __flush_tlb_one(vaddr);                                         \
 491 } while (0)
 492
 493 /*
 494  * The i386 doesn't have any external MMU info: the kernel page
 495  * tables contain all the necessary information.
 496  */
 497 #define update_mmu_cache(vma,address,pte) do { } while (0)
 498 #endif /* !__ASSEMBLY__ */
 499
 500 #ifdef CONFIG_FLATMEM
 501 #define kern_addr_valid(addr)   (1)
 502 #endif /* CONFIG_FLATMEM */
 503
 504 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 505                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 506
 507 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 508 #define GET_IOSPACE(pfn)                0
 509 #define GET_PFN(pfn)                    (pfn)
 510
 511 #include <asm-generic/pgtable.h>
 512
 513 #endif /* _I386_PGTABLE_H */