include/asm-ia64/sn/pcibr_provider.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
   9 #define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
  10
  11 #include <asm/sn/intr.h>
  12 #include <asm/sn/pcibus_provider_defs.h>
  13
  14 /* Workarounds */
  15 #define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
  16
  17 #define BUSTYPE_MASK                    0x1
  18
  19 /* Macros given a pcibus structure */
  20 #define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
  21 #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
  22                 asic == PCIIO_ASIC_TYPE_TIOCP)
  23 #define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
  24
  25
  26 /*
  27  * The different PCI Bridge types supported on the SGI Altix platforms
  28  */
  29 #define PCIBR_BRIDGETYPE_UNKNOWN       -1
  30 #define PCIBR_BRIDGETYPE_PIC            2
  31 #define PCIBR_BRIDGETYPE_TIOCP          3
  32
  33 /*
  34  * Bridge 64bit Direct Map Attributes
  35  */
  36 #define PCI64_ATTR_PREF                 (1ull << 59)
  37 #define PCI64_ATTR_PREC                 (1ull << 58)
  38 #define PCI64_ATTR_VIRTUAL              (1ull << 57)
  39 #define PCI64_ATTR_BAR                  (1ull << 56)
  40 #define PCI64_ATTR_SWAP                 (1ull << 55)
  41 #define PCI64_ATTR_VIRTUAL1             (1ull << 54)
  42
  43 #define PCI32_LOCAL_BASE                0
  44 #define PCI32_MAPPED_BASE               0x40000000
  45 #define PCI32_DIRECT_BASE               0x80000000
  46
  47 #define IS_PCI32_MAPPED(x)              ((u64)(x) < PCI32_DIRECT_BASE && \
  48                                          (u64)(x) >= PCI32_MAPPED_BASE)
  49 #define IS_PCI32_DIRECT(x)              ((u64)(x) >= PCI32_MAPPED_BASE)
  50
  51
  52 /*
  53  * Bridge PMU Address Transaltion Entry Attibutes
  54  */
  55 #define PCI32_ATE_V                     (0x1 << 0)
  56 #define PCI32_ATE_CO                    (0x1 << 1)
  57 #define PCI32_ATE_PREC                  (0x1 << 2)
  58 #define PCI32_ATE_MSI                   (0x1 << 2)
  59 #define PCI32_ATE_PREF                  (0x1 << 3)
  60 #define PCI32_ATE_BAR                   (0x1 << 4)
  61 #define PCI32_ATE_ADDR_SHFT             12
  62
  63 #define MINIMAL_ATES_REQUIRED(addr, size) \
  64         (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
  65
  66 #define MINIMAL_ATE_FLAG(addr, size) \
  67         (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
  68
  69 /* bit 29 of the pci address is the SWAP bit */
  70 #define ATE_SWAPSHIFT                   29
  71 #define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
  72 #define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
  73
  74 /*
  75  * I/O page size
  76  */
  77 #if PAGE_SIZE < 16384
  78 #define IOPFNSHIFT                      12      /* 4K per mapped page */
  79 #else
  80 #define IOPFNSHIFT                      14      /* 16K per mapped page */
  81 #endif
  82
  83 #define IOPGSIZE                        (1 << IOPFNSHIFT)
  84 #define IOPG(x)                         ((x) >> IOPFNSHIFT)
  85 #define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
  86
  87 #define PCIBR_DEV_SWAP_DIR              (1ull << 19)
  88 #define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
  89
  90 /*
  91  * PMU resources.
  92  */
  93 struct ate_resource{
  94         u64 *ate;
  95         u64 num_ate;
  96         u64 lowest_free_index;
  97 };
  98
  99 struct pcibus_info {
 100         struct pcibus_bussoft   pbi_buscommon;   /* common header */
 101         u32                pbi_moduleid;
 102         short                   pbi_bridge_type;
 103         short                   pbi_bridge_mode;
 104
 105         struct ate_resource     pbi_int_ate_resource;
 106         u64                pbi_int_ate_size;
 107
 108         u64                pbi_dir_xbase;
 109         char                    pbi_hub_xid;
 110
 111         u64                pbi_devreg[8];
 112
 113         u32             pbi_valid_devices;
 114         u32             pbi_enabled_devices;
 115
 116         spinlock_t              pbi_lock;
 117 };
 118
 119 extern int  pcibr_init_provider(void);
 120 extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
 121 extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
 122 extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
 123 extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
 124
 125 /*
 126  * prototypes for the bridge asic register access routines in pcibr_reg.c
 127  */
 128 extern void             pcireg_control_bit_clr(struct pcibus_info *, u64);
 129 extern void             pcireg_control_bit_set(struct pcibus_info *, u64);
 130 extern u64         pcireg_tflush_get(struct pcibus_info *);
 131 extern u64         pcireg_intr_status_get(struct pcibus_info *);
 132 extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
 133 extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
 134 extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
 135 extern void             pcireg_force_intr_set(struct pcibus_info *, int);
 136 extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
 137 extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
 138 extern u64 __iomem *    pcireg_int_ate_addr(struct pcibus_info *, int);
 139 extern void             pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
 140 extern void             pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
 141 extern int              pcibr_ate_alloc(struct pcibus_info *, int);
 142 extern void             pcibr_ate_free(struct pcibus_info *, int);
 143 extern void             ate_write(struct pcibus_info *, int, int, u64);
 144 extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
 145                                  void *resp, char **ssdt);
 146 extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
 147                                   int action, void *resp);
 148 extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
 149 #endif