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async_tx: avoid the async xor_zero_sum path when src_cnt > device->max_xor
[wrt350n-kernel.git] / drivers / infiniband / hw / mlx4 / qp.c
blob958e205b6d7c7d5894b419ac6327b7483b900236
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/log2.h>
34
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_pack.h>
37
38 #include <linux/mlx4/qp.h>
39
40 #include "mlx4_ib.h"
41 #include "user.h"
42
43 enum {
44 MLX4_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
50 };
51
52 enum {
53 /*
54 * Largest possible UD header: send with GRH and immediate data.
55 */
56 MLX4_IB_UD_HEADER_SIZE = 72
57 };
58
59 struct mlx4_ib_sqp {
60 struct mlx4_ib_qp qp;
61 int pkey_index;
62 u32 qkey;
63 u32 send_psn;
64 struct ib_ud_header ud_header;
65 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
66 };
67
68 enum {
69 MLX4_IB_MIN_SQ_STRIDE = 6
70 };
71
72 static const __be32 mlx4_ib_opcode[] = {
73 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
74 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
75 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
76 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
77 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
78 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
79 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
80 };
81
82 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
83 {
84 return container_of(mqp, struct mlx4_ib_sqp, qp);
85 }
86
87 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
88 {
89 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
90 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
91 }
92
93 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
94 {
95 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
96 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
97 }
98
99 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
100 {
101 return mlx4_buf_offset(&qp->buf, offset);
102 }
103
104 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
105 {
106 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
107 }
108
109 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
110 {
111 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
112 }
113
114 /*
115 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
116 * first four bytes of every 64 byte chunk with
117 * 0x7FFFFFF | (invalid_ownership_value << 31).
118 *
119 * When the max work request size is less than or equal to the WQE
120 * basic block size, as an optimization, we can stamp all WQEs with
121 * 0xffffffff, and skip the very first chunk of each WQE.
122 */
123 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
124 {
125 u32 *wqe;
126 int i;
127 int s;
128 int ind;
129 void *buf;
130 __be32 stamp;
131
132 s = roundup(size, 1U << qp->sq.wqe_shift);
133 if (qp->sq_max_wqes_per_wr > 1) {
134 for (i = 0; i < s; i += 64) {
135 ind = (i >> qp->sq.wqe_shift) + n;
136 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
137 cpu_to_be32(0xffffffff);
138 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
139 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
140 *wqe = stamp;
141 }
142 } else {
143 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
144 for (i = 64; i < s; i += 64) {
145 wqe = buf + i;
146 *wqe = 0xffffffff;
147 }
148 }
149 }
150
151 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
152 {
153 struct mlx4_wqe_ctrl_seg *ctrl;
154 struct mlx4_wqe_inline_seg *inl;
155 void *wqe;
156 int s;
157
158 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
159 s = sizeof(struct mlx4_wqe_ctrl_seg);
160
161 if (qp->ibqp.qp_type == IB_QPT_UD) {
162 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
163 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
164 memset(dgram, 0, sizeof *dgram);
165 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
166 s += sizeof(struct mlx4_wqe_datagram_seg);
167 }
168
169 /* Pad the remainder of the WQE with an inline data segment. */
170 if (size > s) {
171 inl = wqe + s;
172 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
173 }
174 ctrl->srcrb_flags = 0;
175 ctrl->fence_size = size / 16;
176 /*
177 * Make sure descriptor is fully written before setting ownership bit
178 * (because HW can start executing as soon as we do).
179 */
180 wmb();
181
182 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
183 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
184
185 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
186 }
187
188 /* Post NOP WQE to prevent wrap-around in the middle of WR */
189 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
190 {
191 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
192 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
193 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
194 ind += s;
195 }
196 return ind;
197 }
198
199 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
200 {
201 struct ib_event event;
202 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
203
204 if (type == MLX4_EVENT_TYPE_PATH_MIG)
205 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
206
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
210 switch (type) {
211 case MLX4_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
213 break;
214 case MLX4_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
216 break;
217 case MLX4_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
219 break;
220 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
222 break;
223 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
225 break;
226 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
228 break;
229 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
231 break;
232 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
234 break;
235 default:
236 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
237 "on QP %06x\n", type, qp->qpn);
238 return;
239 }
240
241 ibqp->event_handler(&event, ibqp->qp_context);
242 }
243 }
244
245 static int send_wqe_overhead(enum ib_qp_type type)
246 {
247 /*
248 * UD WQEs must have a datagram segment.
249 * RC and UC WQEs might have a remote address segment.
250 * MLX WQEs need two extra inline data segments (for the UD
251 * header and space for the ICRC).
252 */
253 switch (type) {
254 case IB_QPT_UD:
255 return sizeof (struct mlx4_wqe_ctrl_seg) +
256 sizeof (struct mlx4_wqe_datagram_seg);
257 case IB_QPT_UC:
258 return sizeof (struct mlx4_wqe_ctrl_seg) +
259 sizeof (struct mlx4_wqe_raddr_seg);
260 case IB_QPT_RC:
261 return sizeof (struct mlx4_wqe_ctrl_seg) +
262 sizeof (struct mlx4_wqe_atomic_seg) +
263 sizeof (struct mlx4_wqe_raddr_seg);
264 case IB_QPT_SMI:
265 case IB_QPT_GSI:
266 return sizeof (struct mlx4_wqe_ctrl_seg) +
267 ALIGN(MLX4_IB_UD_HEADER_SIZE +
268 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
269 MLX4_INLINE_ALIGN) *
270 sizeof (struct mlx4_wqe_inline_seg),
271 sizeof (struct mlx4_wqe_data_seg)) +
272 ALIGN(4 +
273 sizeof (struct mlx4_wqe_inline_seg),
274 sizeof (struct mlx4_wqe_data_seg));
275 default:
276 return sizeof (struct mlx4_wqe_ctrl_seg);
277 }
278 }
279
280 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
281 int is_user, int has_srq, struct mlx4_ib_qp *qp)
282 {
283 /* Sanity check RQ size before proceeding */
284 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
285 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
286 return -EINVAL;
287
288 if (has_srq) {
289 /* QPs attached to an SRQ should have no RQ */
290 if (cap->max_recv_wr)
291 return -EINVAL;
292
293 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
294 } else {
295 /* HW requires >= 1 RQ entry with >= 1 gather entry */
296 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
297 return -EINVAL;
298
299 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
300 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
301 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
302 }
303
304 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
305 cap->max_recv_sge = qp->rq.max_gs;
306
307 return 0;
308 }
309
310 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
311 enum ib_qp_type type, struct mlx4_ib_qp *qp)
312 {
313 int s;
314
315 /* Sanity check SQ size before proceeding */
316 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
317 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
318 cap->max_inline_data + send_wqe_overhead(type) +
319 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
320 return -EINVAL;
321
322 /*
323 * For MLX transport we need 2 extra S/G entries:
324 * one for the header and one for the checksum at the end
325 */
326 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
327 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
328 return -EINVAL;
329
330 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
331 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
332 send_wqe_overhead(type);
333
334 /*
335 * Hermon supports shrinking WQEs, such that a single work
336 * request can include multiple units of 1 << wqe_shift. This
337 * way, work requests can differ in size, and do not have to
338 * be a power of 2 in size, saving memory and speeding up send
339 * WR posting. Unfortunately, if we do this then the
340 * wqe_index field in CQEs can't be used to look up the WR ID
341 * anymore, so we do this only if selective signaling is off.
342 *
343 * Further, on 32-bit platforms, we can't use vmap() to make
344 * the QP buffer virtually contigious. Thus we have to use
345 * constant-sized WRs to make sure a WR is always fully within
346 * a single page-sized chunk.
347 *
348 * Finally, we use NOP work requests to pad the end of the
349 * work queue, to avoid wrap-around in the middle of WR. We
350 * set NEC bit to avoid getting completions with error for
351 * these NOP WRs, but since NEC is only supported starting
352 * with firmware 2.2.232, we use constant-sized WRs for older
353 * firmware.
354 *
355 * And, since MLX QPs only support SEND, we use constant-sized
356 * WRs in this case.
357 *
358 * We look for the smallest value of wqe_shift such that the
359 * resulting number of wqes does not exceed device
360 * capabilities.
361 *
362 * We set WQE size to at least 64 bytes, this way stamping
363 * invalidates each WQE.
364 */
365 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
366 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
367 type != IB_QPT_SMI && type != IB_QPT_GSI)
368 qp->sq.wqe_shift = ilog2(64);
369 else
370 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
371
372 for (;;) {
373 if (1 << qp->sq.wqe_shift > dev->dev->caps.max_sq_desc_sz)
374 return -EINVAL;
375
376 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
377
378 /*
379 * We need to leave 2 KB + 1 WR of headroom in the SQ to
380 * allow HW to prefetch.
381 */
382 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
383 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
384 qp->sq_max_wqes_per_wr +
385 qp->sq_spare_wqes);
386
387 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
388 break;
389
390 if (qp->sq_max_wqes_per_wr <= 1)
391 return -EINVAL;
392
393 ++qp->sq.wqe_shift;
394 }
395
396 qp->sq.max_gs = ((qp->sq_max_wqes_per_wr << qp->sq.wqe_shift) -
397 send_wqe_overhead(type)) / sizeof (struct mlx4_wqe_data_seg);
398
399 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
400 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
401 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
402 qp->rq.offset = 0;
403 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
404 } else {
405 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
406 qp->sq.offset = 0;
407 }
408
409 cap->max_send_wr = qp->sq.max_post =
410 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
411 cap->max_send_sge = qp->sq.max_gs;
412 /* We don't support inline sends for kernel QPs (yet) */
413 cap->max_inline_data = 0;
414
415 return 0;
416 }
417
418 static int set_user_sq_size(struct mlx4_ib_dev *dev,
419 struct mlx4_ib_qp *qp,
420 struct mlx4_ib_create_qp *ucmd)
421 {
422 /* Sanity check SQ size before proceeding */
423 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
424 ucmd->log_sq_stride >
425 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
426 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
427 return -EINVAL;
428
429 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
430 qp->sq.wqe_shift = ucmd->log_sq_stride;
431
432 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
433 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
434
435 return 0;
436 }
437
438 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
439 struct ib_qp_init_attr *init_attr,
440 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
441 {
442 int err;
443
444 mutex_init(&qp->mutex);
445 spin_lock_init(&qp->sq.lock);
446 spin_lock_init(&qp->rq.lock);
447
448 qp->state = IB_QPS_RESET;
449 qp->atomic_rd_en = 0;
450 qp->resp_depth = 0;
451
452 qp->rq.head = 0;
453 qp->rq.tail = 0;
454 qp->sq.head = 0;
455 qp->sq.tail = 0;
456 qp->sq_next_wqe = 0;
457
458 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
459 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
460 else
461 qp->sq_signal_bits = 0;
462
463 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
464 if (err)
465 goto err;
466
467 if (pd->uobject) {
468 struct mlx4_ib_create_qp ucmd;
469
470 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
471 err = -EFAULT;
472 goto err;
473 }
474
475 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
476
477 err = set_user_sq_size(dev, qp, &ucmd);
478 if (err)
479 goto err;
480
481 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
482 qp->buf_size, 0);
483 if (IS_ERR(qp->umem)) {
484 err = PTR_ERR(qp->umem);
485 goto err;
486 }
487
488 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
489 ilog2(qp->umem->page_size), &qp->mtt);
490 if (err)
491 goto err_buf;
492
493 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
494 if (err)
495 goto err_mtt;
496
497 if (!init_attr->srq) {
498 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
499 ucmd.db_addr, &qp->db);
500 if (err)
501 goto err_mtt;
502 }
503 } else {
504 qp->sq_no_prefetch = 0;
505
506 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
507 if (err)
508 goto err;
509
510 if (!init_attr->srq) {
511 err = mlx4_ib_db_alloc(dev, &qp->db, 0);
512 if (err)
513 goto err;
514
515 *qp->db.db = 0;
516 }
517
518 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
519 err = -ENOMEM;
520 goto err_db;
521 }
522
523 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
524 &qp->mtt);
525 if (err)
526 goto err_buf;
527
528 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
529 if (err)
530 goto err_mtt;
531
532 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
533 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
534
535 if (!qp->sq.wrid || !qp->rq.wrid) {
536 err = -ENOMEM;
537 goto err_wrid;
538 }
539 }
540
541 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
542 if (err)
543 goto err_wrid;
544
545 /*
546 * Hardware wants QPN written in big-endian order (after
547 * shifting) for send doorbell. Precompute this value to save
548 * a little bit when posting sends.
549 */
550 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
551
552 qp->mqp.event = mlx4_ib_qp_event;
553
554 return 0;
555
556 err_wrid:
557 if (pd->uobject) {
558 if (!init_attr->srq)
559 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
560 &qp->db);
561 } else {
562 kfree(qp->sq.wrid);
563 kfree(qp->rq.wrid);
564 }
565
566 err_mtt:
567 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
568
569 err_buf:
570 if (pd->uobject)
571 ib_umem_release(qp->umem);
572 else
573 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
574
575 err_db:
576 if (!pd->uobject && !init_attr->srq)
577 mlx4_ib_db_free(dev, &qp->db);
578
579 err:
580 return err;
581 }
582
583 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
584 {
585 switch (state) {
586 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
587 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
588 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
589 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
590 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
591 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
592 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
593 default: return -1;
594 }
595 }
596
597 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
598 {
599 if (send_cq == recv_cq)
600 spin_lock_irq(&send_cq->lock);
601 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
602 spin_lock_irq(&send_cq->lock);
603 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
604 } else {
605 spin_lock_irq(&recv_cq->lock);
606 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
607 }
608 }
609
610 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
611 {
612 if (send_cq == recv_cq)
613 spin_unlock_irq(&send_cq->lock);
614 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
615 spin_unlock(&recv_cq->lock);
616 spin_unlock_irq(&send_cq->lock);
617 } else {
618 spin_unlock(&send_cq->lock);
619 spin_unlock_irq(&recv_cq->lock);
620 }
621 }
622
623 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
624 int is_user)
625 {
626 struct mlx4_ib_cq *send_cq, *recv_cq;
627
628 if (qp->state != IB_QPS_RESET)
629 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
630 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
631 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
632 qp->mqp.qpn);
633
634 send_cq = to_mcq(qp->ibqp.send_cq);
635 recv_cq = to_mcq(qp->ibqp.recv_cq);
636
637 mlx4_ib_lock_cqs(send_cq, recv_cq);
638
639 if (!is_user) {
640 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
641 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
642 if (send_cq != recv_cq)
643 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
644 }
645
646 mlx4_qp_remove(dev->dev, &qp->mqp);
647
648 mlx4_ib_unlock_cqs(send_cq, recv_cq);
649
650 mlx4_qp_free(dev->dev, &qp->mqp);
651 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
652
653 if (is_user) {
654 if (!qp->ibqp.srq)
655 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
656 &qp->db);
657 ib_umem_release(qp->umem);
658 } else {
659 kfree(qp->sq.wrid);
660 kfree(qp->rq.wrid);
661 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
662 if (!qp->ibqp.srq)
663 mlx4_ib_db_free(dev, &qp->db);
664 }
665 }
666
667 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
668 struct ib_qp_init_attr *init_attr,
669 struct ib_udata *udata)
670 {
671 struct mlx4_ib_dev *dev = to_mdev(pd->device);
672 struct mlx4_ib_sqp *sqp;
673 struct mlx4_ib_qp *qp;
674 int err;
675
676 switch (init_attr->qp_type) {
677 case IB_QPT_RC:
678 case IB_QPT_UC:
679 case IB_QPT_UD:
680 {
681 qp = kmalloc(sizeof *qp, GFP_KERNEL);
682 if (!qp)
683 return ERR_PTR(-ENOMEM);
684
685 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
686 if (err) {
687 kfree(qp);
688 return ERR_PTR(err);
689 }
690
691 qp->ibqp.qp_num = qp->mqp.qpn;
692
693 break;
694 }
695 case IB_QPT_SMI:
696 case IB_QPT_GSI:
697 {
698 /* Userspace is not allowed to create special QPs: */
699 if (pd->uobject)
700 return ERR_PTR(-EINVAL);
701
702 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
703 if (!sqp)
704 return ERR_PTR(-ENOMEM);
705
706 qp = &sqp->qp;
707
708 err = create_qp_common(dev, pd, init_attr, udata,
709 dev->dev->caps.sqp_start +
710 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
711 init_attr->port_num - 1,
712 qp);
713 if (err) {
714 kfree(sqp);
715 return ERR_PTR(err);
716 }
717
718 qp->port = init_attr->port_num;
719 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
720
721 break;
722 }
723 default:
724 /* Don't support raw QPs */
725 return ERR_PTR(-EINVAL);
726 }
727
728 return &qp->ibqp;
729 }
730
731 int mlx4_ib_destroy_qp(struct ib_qp *qp)
732 {
733 struct mlx4_ib_dev *dev = to_mdev(qp->device);
734 struct mlx4_ib_qp *mqp = to_mqp(qp);
735
736 if (is_qp0(dev, mqp))
737 mlx4_CLOSE_PORT(dev->dev, mqp->port);
738
739 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
740
741 if (is_sqp(dev, mqp))
742 kfree(to_msqp(mqp));
743 else
744 kfree(mqp);
745
746 return 0;
747 }
748
749 static int to_mlx4_st(enum ib_qp_type type)
750 {
751 switch (type) {
752 case IB_QPT_RC: return MLX4_QP_ST_RC;
753 case IB_QPT_UC: return MLX4_QP_ST_UC;
754 case IB_QPT_UD: return MLX4_QP_ST_UD;
755 case IB_QPT_SMI:
756 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
757 default: return -1;
758 }
759 }
760
761 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
762 int attr_mask)
763 {
764 u8 dest_rd_atomic;
765 u32 access_flags;
766 u32 hw_access_flags = 0;
767
768 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
769 dest_rd_atomic = attr->max_dest_rd_atomic;
770 else
771 dest_rd_atomic = qp->resp_depth;
772
773 if (attr_mask & IB_QP_ACCESS_FLAGS)
774 access_flags = attr->qp_access_flags;
775 else
776 access_flags = qp->atomic_rd_en;
777
778 if (!dest_rd_atomic)
779 access_flags &= IB_ACCESS_REMOTE_WRITE;
780
781 if (access_flags & IB_ACCESS_REMOTE_READ)
782 hw_access_flags |= MLX4_QP_BIT_RRE;
783 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
784 hw_access_flags |= MLX4_QP_BIT_RAE;
785 if (access_flags & IB_ACCESS_REMOTE_WRITE)
786 hw_access_flags |= MLX4_QP_BIT_RWE;
787
788 return cpu_to_be32(hw_access_flags);
789 }
790
791 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
792 int attr_mask)
793 {
794 if (attr_mask & IB_QP_PKEY_INDEX)
795 sqp->pkey_index = attr->pkey_index;
796 if (attr_mask & IB_QP_QKEY)
797 sqp->qkey = attr->qkey;
798 if (attr_mask & IB_QP_SQ_PSN)
799 sqp->send_psn = attr->sq_psn;
800 }
801
802 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
803 {
804 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
805 }
806
807 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
808 struct mlx4_qp_path *path, u8 port)
809 {
810 path->grh_mylmc = ah->src_path_bits & 0x7f;
811 path->rlid = cpu_to_be16(ah->dlid);
812 if (ah->static_rate) {
813 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
814 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
815 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
816 --path->static_rate;
817 } else
818 path->static_rate = 0;
819 path->counter_index = 0xff;
820
821 if (ah->ah_flags & IB_AH_GRH) {
822 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
823 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
824 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
825 return -1;
826 }
827
828 path->grh_mylmc |= 1 << 7;
829 path->mgid_index = ah->grh.sgid_index;
830 path->hop_limit = ah->grh.hop_limit;
831 path->tclass_flowlabel =
832 cpu_to_be32((ah->grh.traffic_class << 20) |
833 (ah->grh.flow_label));
834 memcpy(path->rgid, ah->grh.dgid.raw, 16);
835 }
836
837 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
838 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
839
840 return 0;
841 }
842
843 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
844 const struct ib_qp_attr *attr, int attr_mask,
845 enum ib_qp_state cur_state, enum ib_qp_state new_state)
846 {
847 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
848 struct mlx4_ib_qp *qp = to_mqp(ibqp);
849 struct mlx4_qp_context *context;
850 enum mlx4_qp_optpar optpar = 0;
851 int sqd_event;
852 int err = -EINVAL;
853
854 context = kzalloc(sizeof *context, GFP_KERNEL);
855 if (!context)
856 return -ENOMEM;
857
858 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
859 (to_mlx4_st(ibqp->qp_type) << 16));
860 context->flags |= cpu_to_be32(1 << 8); /* DE? */
861
862 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
863 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
864 else {
865 optpar |= MLX4_QP_OPTPAR_PM_STATE;
866 switch (attr->path_mig_state) {
867 case IB_MIG_MIGRATED:
868 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
869 break;
870 case IB_MIG_REARM:
871 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
872 break;
873 case IB_MIG_ARMED:
874 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
875 break;
876 }
877 }
878
879 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
880 ibqp->qp_type == IB_QPT_UD)
881 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
882 else if (attr_mask & IB_QP_PATH_MTU) {
883 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
884 printk(KERN_ERR "path MTU (%u) is invalid\n",
885 attr->path_mtu);
886 goto out;
887 }
888 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
889 }
890
891 if (qp->rq.wqe_cnt)
892 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
893 context->rq_size_stride |= qp->rq.wqe_shift - 4;
894
895 if (qp->sq.wqe_cnt)
896 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
897 context->sq_size_stride |= qp->sq.wqe_shift - 4;
898
899 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
900 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
901
902 if (qp->ibqp.uobject)
903 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
904 else
905 context->usr_page = cpu_to_be32(dev->priv_uar.index);
906
907 if (attr_mask & IB_QP_DEST_QPN)
908 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
909
910 if (attr_mask & IB_QP_PORT) {
911 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
912 !(attr_mask & IB_QP_AV)) {
913 mlx4_set_sched(&context->pri_path, attr->port_num);
914 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
915 }
916 }
917
918 if (attr_mask & IB_QP_PKEY_INDEX) {
919 context->pri_path.pkey_index = attr->pkey_index;
920 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
921 }
922
923 if (attr_mask & IB_QP_AV) {
924 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
925 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
926 goto out;
927
928 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
929 MLX4_QP_OPTPAR_SCHED_QUEUE);
930 }
931
932 if (attr_mask & IB_QP_TIMEOUT) {
933 context->pri_path.ackto = attr->timeout << 3;
934 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
935 }
936
937 if (attr_mask & IB_QP_ALT_PATH) {
938 if (attr->alt_port_num == 0 ||
939 attr->alt_port_num > dev->dev->caps.num_ports)
940 goto out;
941
942 if (attr->alt_pkey_index >=
943 dev->dev->caps.pkey_table_len[attr->alt_port_num])
944 goto out;
945
946 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
947 attr->alt_port_num))
948 goto out;
949
950 context->alt_path.pkey_index = attr->alt_pkey_index;
951 context->alt_path.ackto = attr->alt_timeout << 3;
952 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
953 }
954
955 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
956 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
957
958 if (attr_mask & IB_QP_RNR_RETRY) {
959 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
960 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
961 }
962
963 if (attr_mask & IB_QP_RETRY_CNT) {
964 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
965 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
966 }
967
968 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
969 if (attr->max_rd_atomic)
970 context->params1 |=
971 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
972 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
973 }
974
975 if (attr_mask & IB_QP_SQ_PSN)
976 context->next_send_psn = cpu_to_be32(attr->sq_psn);
977
978 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
979
980 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
981 if (attr->max_dest_rd_atomic)
982 context->params2 |=
983 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
984 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
985 }
986
987 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
988 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
989 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
990 }
991
992 if (ibqp->srq)
993 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
994
995 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
996 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
997 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
998 }
999 if (attr_mask & IB_QP_RQ_PSN)
1000 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1001
1002 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1003
1004 if (attr_mask & IB_QP_QKEY) {
1005 context->qkey = cpu_to_be32(attr->qkey);
1006 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1007 }
1008
1009 if (ibqp->srq)
1010 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1011
1012 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1013 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1014
1015 if (cur_state == IB_QPS_INIT &&
1016 new_state == IB_QPS_RTR &&
1017 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1018 ibqp->qp_type == IB_QPT_UD)) {
1019 context->pri_path.sched_queue = (qp->port - 1) << 6;
1020 if (is_qp0(dev, qp))
1021 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1022 else
1023 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1024 }
1025
1026 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1027 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1028 sqd_event = 1;
1029 else
1030 sqd_event = 0;
1031
1032 /*
1033 * Before passing a kernel QP to the HW, make sure that the
1034 * ownership bits of the send queue are set and the SQ
1035 * headroom is stamped so that the hardware doesn't start
1036 * processing stale work requests.
1037 */
1038 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1039 struct mlx4_wqe_ctrl_seg *ctrl;
1040 int i;
1041
1042 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1043 ctrl = get_send_wqe(qp, i);
1044 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1045
1046 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1047 }
1048 }
1049
1050 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1051 to_mlx4_state(new_state), context, optpar,
1052 sqd_event, &qp->mqp);
1053 if (err)
1054 goto out;
1055
1056 qp->state = new_state;
1057
1058 if (attr_mask & IB_QP_ACCESS_FLAGS)
1059 qp->atomic_rd_en = attr->qp_access_flags;
1060 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1061 qp->resp_depth = attr->max_dest_rd_atomic;
1062 if (attr_mask & IB_QP_PORT)
1063 qp->port = attr->port_num;
1064 if (attr_mask & IB_QP_ALT_PATH)
1065 qp->alt_port = attr->alt_port_num;
1066
1067 if (is_sqp(dev, qp))
1068 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1069
1070 /*
1071 * If we moved QP0 to RTR, bring the IB link up; if we moved
1072 * QP0 to RESET or ERROR, bring the link back down.
1073 */
1074 if (is_qp0(dev, qp)) {
1075 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1076 if (mlx4_INIT_PORT(dev->dev, qp->port))
1077 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1078 qp->port);
1079
1080 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1081 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1082 mlx4_CLOSE_PORT(dev->dev, qp->port);
1083 }
1084
1085 /*
1086 * If we moved a kernel QP to RESET, clean up all old CQ
1087 * entries and reinitialize the QP.
1088 */
1089 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1090 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1091 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1092 if (ibqp->send_cq != ibqp->recv_cq)
1093 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1094
1095 qp->rq.head = 0;
1096 qp->rq.tail = 0;
1097 qp->sq.head = 0;
1098 qp->sq.tail = 0;
1099 qp->sq_next_wqe = 0;
1100 if (!ibqp->srq)
1101 *qp->db.db = 0;
1102 }
1103
1104 out:
1105 kfree(context);
1106 return err;
1107 }
1108
1109 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
1110 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
1111 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
1112 IB_QP_PORT |
1113 IB_QP_QKEY),
1114 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
1115 IB_QP_PORT |
1116 IB_QP_ACCESS_FLAGS),
1117 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
1118 IB_QP_PORT |
1119 IB_QP_ACCESS_FLAGS),
1120 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
1121 IB_QP_QKEY),
1122 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
1123 IB_QP_QKEY),
1124 };
1125
1126 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1127 int attr_mask, struct ib_udata *udata)
1128 {
1129 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1130 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1131 enum ib_qp_state cur_state, new_state;
1132 int err = -EINVAL;
1133
1134 mutex_lock(&qp->mutex);
1135
1136 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1137 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1138
1139 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1140 goto out;
1141
1142 if ((attr_mask & IB_QP_PORT) &&
1143 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1144 goto out;
1145 }
1146
1147 if (attr_mask & IB_QP_PKEY_INDEX) {
1148 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1149 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1150 goto out;
1151 }
1152
1153 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1154 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1155 goto out;
1156 }
1157
1158 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1159 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1160 goto out;
1161 }
1162
1163 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1164 err = 0;
1165 goto out;
1166 }
1167
1168 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1169 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1170 mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1171 IB_QPS_RESET, IB_QPS_INIT);
1172 if (err)
1173 goto out;
1174 cur_state = IB_QPS_INIT;
1175 }
1176
1177 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1178
1179 out:
1180 mutex_unlock(&qp->mutex);
1181 return err;
1182 }
1183
1184 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1185 void *wqe)
1186 {
1187 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1188 struct mlx4_wqe_mlx_seg *mlx = wqe;
1189 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1190 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1191 u16 pkey;
1192 int send_size;
1193 int header_size;
1194 int spc;
1195 int i;
1196
1197 send_size = 0;
1198 for (i = 0; i < wr->num_sge; ++i)
1199 send_size += wr->sg_list[i].length;
1200
1201 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1202
1203 sqp->ud_header.lrh.service_level =
1204 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1205 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1206 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1207 if (mlx4_ib_ah_grh_present(ah)) {
1208 sqp->ud_header.grh.traffic_class =
1209 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1210 sqp->ud_header.grh.flow_label =
1211 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1212 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
1213 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1214 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1215 memcpy(sqp->ud_header.grh.destination_gid.raw,
1216 ah->av.dgid, 16);
1217 }
1218
1219 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1220 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1221 (sqp->ud_header.lrh.destination_lid ==
1222 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1223 (sqp->ud_header.lrh.service_level << 8));
1224 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1225
1226 switch (wr->opcode) {
1227 case IB_WR_SEND:
1228 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1229 sqp->ud_header.immediate_present = 0;
1230 break;
1231 case IB_WR_SEND_WITH_IMM:
1232 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1233 sqp->ud_header.immediate_present = 1;
1234 sqp->ud_header.immediate_data = wr->imm_data;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1241 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1242 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1243 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1244 if (!sqp->qp.ibqp.qp_num)
1245 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1246 else
1247 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1248 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1249 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1250 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1251 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1252 sqp->qkey : wr->wr.ud.remote_qkey);
1253 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1254
1255 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1256
1257 if (0) {
1258 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1259 for (i = 0; i < header_size / 4; ++i) {
1260 if (i % 8 == 0)
1261 printk(" [%02x] ", i * 4);
1262 printk(" %08x",
1263 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1264 if ((i + 1) % 8 == 0)
1265 printk("\n");
1266 }
1267 printk("\n");
1268 }
1269
1270 /*
1271 * Inline data segments may not cross a 64 byte boundary. If
1272 * our UD header is bigger than the space available up to the
1273 * next 64 byte boundary in the WQE, use two inline data
1274 * segments to hold the UD header.
1275 */
1276 spc = MLX4_INLINE_ALIGN -
1277 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1278 if (header_size <= spc) {
1279 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1280 memcpy(inl + 1, sqp->header_buf, header_size);
1281 i = 1;
1282 } else {
1283 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1284 memcpy(inl + 1, sqp->header_buf, spc);
1285
1286 inl = (void *) (inl + 1) + spc;
1287 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1288 /*
1289 * Need a barrier here to make sure all the data is
1290 * visible before the byte_count field is set.
1291 * Otherwise the HCA prefetcher could grab the 64-byte
1292 * chunk with this inline segment and get a valid (!=
1293 * 0xffffffff) byte count but stale data, and end up
1294 * generating a packet with bad headers.
1295 *
1296 * The first inline segment's byte_count field doesn't
1297 * need a barrier, because it comes after a
1298 * control/MLX segment and therefore is at an offset
1299 * of 16 mod 64.
1300 */
1301 wmb();
1302 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1303 i = 2;
1304 }
1305
1306 return ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1307 }
1308
1309 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1310 {
1311 unsigned cur;
1312 struct mlx4_ib_cq *cq;
1313
1314 cur = wq->head - wq->tail;
1315 if (likely(cur + nreq < wq->max_post))
1316 return 0;
1317
1318 cq = to_mcq(ib_cq);
1319 spin_lock(&cq->lock);
1320 cur = wq->head - wq->tail;
1321 spin_unlock(&cq->lock);
1322
1323 return cur + nreq >= wq->max_post;
1324 }
1325
1326 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1327 u64 remote_addr, u32 rkey)
1328 {
1329 rseg->raddr = cpu_to_be64(remote_addr);
1330 rseg->rkey = cpu_to_be32(rkey);
1331 rseg->reserved = 0;
1332 }
1333
1334 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1335 {
1336 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1337 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1338 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1339 } else {
1340 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1341 aseg->compare = 0;
1342 }
1343
1344 }
1345
1346 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1347 struct ib_send_wr *wr)
1348 {
1349 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1350 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1351 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1352 }
1353
1354 static void set_mlx_icrc_seg(void *dseg)
1355 {
1356 u32 *t = dseg;
1357 struct mlx4_wqe_inline_seg *iseg = dseg;
1358
1359 t[1] = 0;
1360
1361 /*
1362 * Need a barrier here before writing the byte_count field to
1363 * make sure that all the data is visible before the
1364 * byte_count field is set. Otherwise, if the segment begins
1365 * a new cacheline, the HCA prefetcher could grab the 64-byte
1366 * chunk and get a valid (!= * 0xffffffff) byte count but
1367 * stale data, and end up sending the wrong data.
1368 */
1369 wmb();
1370
1371 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1372 }
1373
1374 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1375 {
1376 dseg->lkey = cpu_to_be32(sg->lkey);
1377 dseg->addr = cpu_to_be64(sg->addr);
1378
1379 /*
1380 * Need a barrier here before writing the byte_count field to
1381 * make sure that all the data is visible before the
1382 * byte_count field is set. Otherwise, if the segment begins
1383 * a new cacheline, the HCA prefetcher could grab the 64-byte
1384 * chunk and get a valid (!= * 0xffffffff) byte count but
1385 * stale data, and end up sending the wrong data.
1386 */
1387 wmb();
1388
1389 dseg->byte_count = cpu_to_be32(sg->length);
1390 }
1391
1392 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1393 {
1394 dseg->byte_count = cpu_to_be32(sg->length);
1395 dseg->lkey = cpu_to_be32(sg->lkey);
1396 dseg->addr = cpu_to_be64(sg->addr);
1397 }
1398
1399 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1400 struct ib_send_wr **bad_wr)
1401 {
1402 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1403 void *wqe;
1404 struct mlx4_wqe_ctrl_seg *ctrl;
1405 struct mlx4_wqe_data_seg *dseg;
1406 unsigned long flags;
1407 int nreq;
1408 int err = 0;
1409 unsigned ind;
1410 int uninitialized_var(stamp);
1411 int uninitialized_var(size);
1412 int i;
1413
1414 spin_lock_irqsave(&qp->sq.lock, flags);
1415
1416 ind = qp->sq_next_wqe;
1417
1418 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1419 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1420 err = -ENOMEM;
1421 *bad_wr = wr;
1422 goto out;
1423 }
1424
1425 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1426 err = -EINVAL;
1427 *bad_wr = wr;
1428 goto out;
1429 }
1430
1431 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1432 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1433
1434 ctrl->srcrb_flags =
1435 (wr->send_flags & IB_SEND_SIGNALED ?
1436 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1437 (wr->send_flags & IB_SEND_SOLICITED ?
1438 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1439 qp->sq_signal_bits;
1440
1441 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1442 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1443 ctrl->imm = wr->imm_data;
1444 else
1445 ctrl->imm = 0;
1446
1447 wqe += sizeof *ctrl;
1448 size = sizeof *ctrl / 16;
1449
1450 switch (ibqp->qp_type) {
1451 case IB_QPT_RC:
1452 case IB_QPT_UC:
1453 switch (wr->opcode) {
1454 case IB_WR_ATOMIC_CMP_AND_SWP:
1455 case IB_WR_ATOMIC_FETCH_AND_ADD:
1456 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1457 wr->wr.atomic.rkey);
1458 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1459
1460 set_atomic_seg(wqe, wr);
1461 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1462
1463 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1464 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1465
1466 break;
1467
1468 case IB_WR_RDMA_READ:
1469 case IB_WR_RDMA_WRITE:
1470 case IB_WR_RDMA_WRITE_WITH_IMM:
1471 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1472 wr->wr.rdma.rkey);
1473 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1474 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1475 break;
1476
1477 default:
1478 /* No extra segments required for sends */
1479 break;
1480 }
1481 break;
1482
1483 case IB_QPT_UD:
1484 set_datagram_seg(wqe, wr);
1485 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1486 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1487 break;
1488
1489 case IB_QPT_SMI:
1490 case IB_QPT_GSI:
1491 err = build_mlx_header(to_msqp(qp), wr, ctrl);
1492 if (err < 0) {
1493 *bad_wr = wr;
1494 goto out;
1495 }
1496 wqe += err;
1497 size += err / 16;
1498
1499 err = 0;
1500 break;
1501
1502 default:
1503 break;
1504 }
1505
1506 /*
1507 * Write data segments in reverse order, so as to
1508 * overwrite cacheline stamp last within each
1509 * cacheline. This avoids issues with WQE
1510 * prefetching.
1511 */
1512
1513 dseg = wqe;
1514 dseg += wr->num_sge - 1;
1515 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1516
1517 /* Add one more inline data segment for ICRC for MLX sends */
1518 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1519 qp->ibqp.qp_type == IB_QPT_GSI)) {
1520 set_mlx_icrc_seg(dseg + 1);
1521 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1522 }
1523
1524 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1525 set_data_seg(dseg, wr->sg_list + i);
1526
1527 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1528 MLX4_WQE_CTRL_FENCE : 0) | size;
1529
1530 /*
1531 * Make sure descriptor is fully written before
1532 * setting ownership bit (because HW can start
1533 * executing as soon as we do).
1534 */
1535 wmb();
1536
1537 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1538 err = -EINVAL;
1539 goto out;
1540 }
1541
1542 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1543 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1544
1545 stamp = ind + qp->sq_spare_wqes;
1546 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1547
1548 /*
1549 * We can improve latency by not stamping the last
1550 * send queue WQE until after ringing the doorbell, so
1551 * only stamp here if there are still more WQEs to post.
1552 *
1553 * Same optimization applies to padding with NOP wqe
1554 * in case of WQE shrinking (used to prevent wrap-around
1555 * in the middle of WR).
1556 */
1557 if (wr->next) {
1558 stamp_send_wqe(qp, stamp, size * 16);
1559 ind = pad_wraparound(qp, ind);
1560 }
1561
1562 }
1563
1564 out:
1565 if (likely(nreq)) {
1566 qp->sq.head += nreq;
1567
1568 /*
1569 * Make sure that descriptors are written before
1570 * doorbell record.
1571 */
1572 wmb();
1573
1574 writel(qp->doorbell_qpn,
1575 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1576
1577 /*
1578 * Make sure doorbells don't leak out of SQ spinlock
1579 * and reach the HCA out of order.
1580 */
1581 mmiowb();
1582
1583 stamp_send_wqe(qp, stamp, size * 16);
1584
1585 ind = pad_wraparound(qp, ind);
1586 qp->sq_next_wqe = ind;
1587 }
1588
1589 spin_unlock_irqrestore(&qp->sq.lock, flags);
1590
1591 return err;
1592 }
1593
1594 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1595 struct ib_recv_wr **bad_wr)
1596 {
1597 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1598 struct mlx4_wqe_data_seg *scat;
1599 unsigned long flags;
1600 int err = 0;
1601 int nreq;
1602 int ind;
1603 int i;
1604
1605 spin_lock_irqsave(&qp->rq.lock, flags);
1606
1607 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1608
1609 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1610 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1611 err = -ENOMEM;
1612 *bad_wr = wr;
1613 goto out;
1614 }
1615
1616 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1617 err = -EINVAL;
1618 *bad_wr = wr;
1619 goto out;
1620 }
1621
1622 scat = get_recv_wqe(qp, ind);
1623
1624 for (i = 0; i < wr->num_sge; ++i)
1625 __set_data_seg(scat + i, wr->sg_list + i);
1626
1627 if (i < qp->rq.max_gs) {
1628 scat[i].byte_count = 0;
1629 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1630 scat[i].addr = 0;
1631 }
1632
1633 qp->rq.wrid[ind] = wr->wr_id;
1634
1635 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1636 }
1637
1638 out:
1639 if (likely(nreq)) {
1640 qp->rq.head += nreq;
1641
1642 /*
1643 * Make sure that descriptors are written before
1644 * doorbell record.
1645 */
1646 wmb();
1647
1648 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1649 }
1650
1651 spin_unlock_irqrestore(&qp->rq.lock, flags);
1652
1653 return err;
1654 }
1655
1656 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1657 {
1658 switch (mlx4_state) {
1659 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1660 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1661 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1662 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1663 case MLX4_QP_STATE_SQ_DRAINING:
1664 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1665 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1666 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1667 default: return -1;
1668 }
1669 }
1670
1671 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1672 {
1673 switch (mlx4_mig_state) {
1674 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1675 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1676 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1677 default: return -1;
1678 }
1679 }
1680
1681 static int to_ib_qp_access_flags(int mlx4_flags)
1682 {
1683 int ib_flags = 0;
1684
1685 if (mlx4_flags & MLX4_QP_BIT_RRE)
1686 ib_flags |= IB_ACCESS_REMOTE_READ;
1687 if (mlx4_flags & MLX4_QP_BIT_RWE)
1688 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1689 if (mlx4_flags & MLX4_QP_BIT_RAE)
1690 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1691
1692 return ib_flags;
1693 }
1694
1695 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1696 struct mlx4_qp_path *path)
1697 {
1698 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1699 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1700
1701 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1702 return;
1703
1704 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1705 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1706 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1707 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1708 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1709 if (ib_ah_attr->ah_flags) {
1710 ib_ah_attr->grh.sgid_index = path->mgid_index;
1711 ib_ah_attr->grh.hop_limit = path->hop_limit;
1712 ib_ah_attr->grh.traffic_class =
1713 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1714 ib_ah_attr->grh.flow_label =
1715 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1716 memcpy(ib_ah_attr->grh.dgid.raw,
1717 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1718 }
1719 }
1720
1721 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1722 struct ib_qp_init_attr *qp_init_attr)
1723 {
1724 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1725 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1726 struct mlx4_qp_context context;
1727 int mlx4_state;
1728 int err;
1729
1730 if (qp->state == IB_QPS_RESET) {
1731 qp_attr->qp_state = IB_QPS_RESET;
1732 goto done;
1733 }
1734
1735 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1736 if (err)
1737 return -EINVAL;
1738
1739 mlx4_state = be32_to_cpu(context.flags) >> 28;
1740
1741 qp_attr->qp_state = to_ib_qp_state(mlx4_state);
1742 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1743 qp_attr->path_mig_state =
1744 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1745 qp_attr->qkey = be32_to_cpu(context.qkey);
1746 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1747 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1748 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1749 qp_attr->qp_access_flags =
1750 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1751
1752 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1753 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1754 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1755 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1756 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1757 }
1758
1759 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1760 if (qp_attr->qp_state == IB_QPS_INIT)
1761 qp_attr->port_num = qp->port;
1762 else
1763 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1764
1765 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1766 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1767
1768 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1769
1770 qp_attr->max_dest_rd_atomic =
1771 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1772 qp_attr->min_rnr_timer =
1773 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1774 qp_attr->timeout = context.pri_path.ackto >> 3;
1775 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1776 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1777 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1778
1779 done:
1780 qp_attr->cur_qp_state = qp_attr->qp_state;
1781 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1782 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1783
1784 if (!ibqp->uobject) {
1785 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1786 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1787 } else {
1788 qp_attr->cap.max_send_wr = 0;
1789 qp_attr->cap.max_send_sge = 0;
1790 }
1791
1792 /*
1793 * We don't support inline sends for kernel QPs (yet), and we
1794 * don't know what userspace's value should be.
1795 */
1796 qp_attr->cap.max_inline_data = 0;
1797
1798 qp_init_attr->cap = qp_attr->cap;
1799
1800 return 0;
1801 }
1802
WRT350N Kernel Patches