?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: delay CPA self-test and repeat it
[wrt350n-kernel.git] / drivers / ata / sata_qstor.c
blob91cc12c82040d0bb4117649737c46dcc75f7bb31
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.09"
43
44 enum {
45 QS_MMIO_BAR = 4,
46
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_qc_prep(struct ata_queued_cmd *qc);
120 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
121 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
122 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
123 static u8 qs_bmdma_status(struct ata_port *ap);
124 static void qs_irq_clear(struct ata_port *ap);
125 static void qs_freeze(struct ata_port *ap);
126 static void qs_thaw(struct ata_port *ap);
127 static void qs_error_handler(struct ata_port *ap);
128
129 static struct scsi_host_template qs_ata_sht = {
130 .module = THIS_MODULE,
131 .name = DRV_NAME,
132 .ioctl = ata_scsi_ioctl,
133 .queuecommand = ata_scsi_queuecmd,
134 .can_queue = ATA_DEF_QUEUE,
135 .this_id = ATA_SHT_THIS_ID,
136 .sg_tablesize = QS_MAX_PRD,
137 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
138 .emulated = ATA_SHT_EMULATED,
139 .use_clustering = ENABLE_CLUSTERING,
140 .proc_name = DRV_NAME,
141 .dma_boundary = QS_DMA_BOUNDARY,
142 .slave_configure = ata_scsi_slave_config,
143 .slave_destroy = ata_scsi_slave_destroy,
144 .bios_param = ata_std_bios_param,
145 };
146
147 static const struct ata_port_operations qs_ata_ops = {
148 .tf_load = ata_tf_load,
149 .tf_read = ata_tf_read,
150 .check_status = ata_check_status,
151 .check_atapi_dma = qs_check_atapi_dma,
152 .exec_command = ata_exec_command,
153 .dev_select = ata_std_dev_select,
154 .qc_prep = qs_qc_prep,
155 .qc_issue = qs_qc_issue,
156 .data_xfer = ata_data_xfer,
157 .freeze = qs_freeze,
158 .thaw = qs_thaw,
159 .error_handler = qs_error_handler,
160 .irq_clear = qs_irq_clear,
161 .irq_on = ata_irq_on,
162 .scr_read = qs_scr_read,
163 .scr_write = qs_scr_write,
164 .port_start = qs_port_start,
165 .host_stop = qs_host_stop,
166 .bmdma_stop = qs_bmdma_stop,
167 .bmdma_status = qs_bmdma_status,
168 };
169
170 static const struct ata_port_info qs_port_info[] = {
171 /* board_2068_idx */
172 {
173 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
174 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
175 .pio_mask = 0x10, /* pio4 */
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &qs_ata_ops,
178 },
179 };
180
181 static const struct pci_device_id qs_ata_pci_tbl[] = {
182 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
183
184 { } /* terminate list */
185 };
186
187 static struct pci_driver qs_ata_pci_driver = {
188 .name = DRV_NAME,
189 .id_table = qs_ata_pci_tbl,
190 .probe = qs_ata_init_one,
191 .remove = ata_pci_remove_one,
192 };
193
194 static void __iomem *qs_mmio_base(struct ata_host *host)
195 {
196 return host->iomap[QS_MMIO_BAR];
197 }
198
199 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
200 {
201 return 1; /* ATAPI DMA not supported */
202 }
203
204 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
205 {
206 /* nothing */
207 }
208
209 static u8 qs_bmdma_status(struct ata_port *ap)
210 {
211 return 0;
212 }
213
214 static void qs_irq_clear(struct ata_port *ap)
215 {
216 /* nothing */
217 }
218
219 static inline void qs_enter_reg_mode(struct ata_port *ap)
220 {
221 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
222 struct qs_port_priv *pp = ap->private_data;
223
224 pp->state = qs_state_mmio;
225 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
226 readb(chan + QS_CCT_CTR0); /* flush */
227 }
228
229 static inline void qs_reset_channel_logic(struct ata_port *ap)
230 {
231 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
232
233 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
234 readb(chan + QS_CCT_CTR0); /* flush */
235 qs_enter_reg_mode(ap);
236 }
237
238 static void qs_freeze(struct ata_port *ap)
239 {
240 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
241
242 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
243 qs_enter_reg_mode(ap);
244 }
245
246 static void qs_thaw(struct ata_port *ap)
247 {
248 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
249
250 qs_enter_reg_mode(ap);
251 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
252 }
253
254 static int qs_prereset(struct ata_link *link, unsigned long deadline)
255 {
256 struct ata_port *ap = link->ap;
257
258 qs_reset_channel_logic(ap);
259 return ata_std_prereset(link, deadline);
260 }
261
262 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
263 {
264 if (sc_reg > SCR_CONTROL)
265 return -EINVAL;
266 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
267 return 0;
268 }
269
270 static void qs_error_handler(struct ata_port *ap)
271 {
272 qs_enter_reg_mode(ap);
273 ata_do_eh(ap, qs_prereset, NULL, sata_std_hardreset,
274 ata_std_postreset);
275 }
276
277 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
278 {
279 if (sc_reg > SCR_CONTROL)
280 return -EINVAL;
281 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
282 return 0;
283 }
284
285 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
286 {
287 struct scatterlist *sg;
288 struct ata_port *ap = qc->ap;
289 struct qs_port_priv *pp = ap->private_data;
290 u8 *prd = pp->pkt + QS_CPB_BYTES;
291 unsigned int si;
292
293 for_each_sg(qc->sg, sg, qc->n_elem, si) {
294 u64 addr;
295 u32 len;
296
297 addr = sg_dma_address(sg);
298 *(__le64 *)prd = cpu_to_le64(addr);
299 prd += sizeof(u64);
300
301 len = sg_dma_len(sg);
302 *(__le32 *)prd = cpu_to_le32(len);
303 prd += sizeof(u64);
304
305 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
306 (unsigned long long)addr, len);
307 }
308
309 return si;
310 }
311
312 static void qs_qc_prep(struct ata_queued_cmd *qc)
313 {
314 struct qs_port_priv *pp = qc->ap->private_data;
315 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
316 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
317 u64 addr;
318 unsigned int nelem;
319
320 VPRINTK("ENTER\n");
321
322 qs_enter_reg_mode(qc->ap);
323 if (qc->tf.protocol != ATA_PROT_DMA) {
324 ata_qc_prep(qc);
325 return;
326 }
327
328 nelem = qs_fill_sg(qc);
329
330 if ((qc->tf.flags & ATA_TFLAG_WRITE))
331 hflags |= QS_HF_DIRO;
332 if ((qc->tf.flags & ATA_TFLAG_LBA48))
333 dflags |= QS_DF_ELBA;
334
335 /* host control block (HCB) */
336 buf[ 0] = QS_HCB_HDR;
337 buf[ 1] = hflags;
338 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
339 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
340 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
341 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
342
343 /* device control block (DCB) */
344 buf[24] = QS_DCB_HDR;
345 buf[28] = dflags;
346
347 /* frame information structure (FIS) */
348 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
349 }
350
351 static inline void qs_packet_start(struct ata_queued_cmd *qc)
352 {
353 struct ata_port *ap = qc->ap;
354 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
355
356 VPRINTK("ENTER, ap %p\n", ap);
357
358 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
359 wmb(); /* flush PRDs and pkt to memory */
360 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
361 readl(chan + QS_CCT_CFF); /* flush */
362 }
363
364 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
365 {
366 struct qs_port_priv *pp = qc->ap->private_data;
367
368 switch (qc->tf.protocol) {
369 case ATA_PROT_DMA:
370 pp->state = qs_state_pkt;
371 qs_packet_start(qc);
372 return 0;
373
374 case ATAPI_PROT_DMA:
375 BUG();
376 break;
377
378 default:
379 break;
380 }
381
382 pp->state = qs_state_mmio;
383 return ata_qc_issue_prot(qc);
384 }
385
386 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
387 {
388 qc->err_mask |= ac_err_mask(status);
389
390 if (!qc->err_mask) {
391 ata_qc_complete(qc);
392 } else {
393 struct ata_port *ap = qc->ap;
394 struct ata_eh_info *ehi = &ap->link.eh_info;
395
396 ata_ehi_clear_desc(ehi);
397 ata_ehi_push_desc(ehi, "status 0x%02X", status);
398
399 if (qc->err_mask == AC_ERR_DEV)
400 ata_port_abort(ap);
401 else
402 ata_port_freeze(ap);
403 }
404 }
405
406 static inline unsigned int qs_intr_pkt(struct ata_host *host)
407 {
408 unsigned int handled = 0;
409 u8 sFFE;
410 u8 __iomem *mmio_base = qs_mmio_base(host);
411
412 do {
413 u32 sff0 = readl(mmio_base + QS_HST_SFF);
414 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
415 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
416 sFFE = sff1 >> 31; /* empty flag */
417
418 if (sEVLD) {
419 u8 sDST = sff0 >> 16; /* dev status */
420 u8 sHST = sff1 & 0x3f; /* host status */
421 unsigned int port_no = (sff1 >> 8) & 0x03;
422 struct ata_port *ap = host->ports[port_no];
423
424 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
425 sff1, sff0, port_no, sHST, sDST);
426 handled = 1;
427 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
428 struct ata_queued_cmd *qc;
429 struct qs_port_priv *pp = ap->private_data;
430 if (!pp || pp->state != qs_state_pkt)
431 continue;
432 qc = ata_qc_from_tag(ap, ap->link.active_tag);
433 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
434 switch (sHST) {
435 case 0: /* successful CPB */
436 case 3: /* device error */
437 qs_enter_reg_mode(qc->ap);
438 qs_do_or_die(qc, sDST);
439 break;
440 default:
441 break;
442 }
443 }
444 }
445 }
446 } while (!sFFE);
447 return handled;
448 }
449
450 static inline unsigned int qs_intr_mmio(struct ata_host *host)
451 {
452 unsigned int handled = 0, port_no;
453
454 for (port_no = 0; port_no < host->n_ports; ++port_no) {
455 struct ata_port *ap;
456 ap = host->ports[port_no];
457 if (ap &&
458 !(ap->flags & ATA_FLAG_DISABLED)) {
459 struct ata_queued_cmd *qc;
460 struct qs_port_priv *pp;
461 qc = ata_qc_from_tag(ap, ap->link.active_tag);
462 if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
463 /*
464 * The qstor hardware generates spurious
465 * interrupts from time to time when switching
466 * in and out of packet mode.
467 * There's no obvious way to know if we're
468 * here now due to that, so just ack the irq
469 * and pretend we knew it was ours.. (ugh).
470 * This does not affect packet mode.
471 */
472 ata_check_status(ap);
473 handled = 1;
474 continue;
475 }
476 pp = ap->private_data;
477 if (!pp || pp->state != qs_state_mmio)
478 continue;
479 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
480 handled |= ata_host_intr(ap, qc);
481 }
482 }
483 return handled;
484 }
485
486 static irqreturn_t qs_intr(int irq, void *dev_instance)
487 {
488 struct ata_host *host = dev_instance;
489 unsigned int handled = 0;
490 unsigned long flags;
491
492 VPRINTK("ENTER\n");
493
494 spin_lock_irqsave(&host->lock, flags);
495 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
496 spin_unlock_irqrestore(&host->lock, flags);
497
498 VPRINTK("EXIT\n");
499
500 return IRQ_RETVAL(handled);
501 }
502
503 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
504 {
505 port->cmd_addr =
506 port->data_addr = base + 0x400;
507 port->error_addr =
508 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
509 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
510 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
511 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
512 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
513 port->device_addr = base + 0x430;
514 port->status_addr =
515 port->command_addr = base + 0x438;
516 port->altstatus_addr =
517 port->ctl_addr = base + 0x440;
518 port->scr_addr = base + 0xc00;
519 }
520
521 static int qs_port_start(struct ata_port *ap)
522 {
523 struct device *dev = ap->host->dev;
524 struct qs_port_priv *pp;
525 void __iomem *mmio_base = qs_mmio_base(ap->host);
526 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
527 u64 addr;
528 int rc;
529
530 rc = ata_port_start(ap);
531 if (rc)
532 return rc;
533 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
534 if (!pp)
535 return -ENOMEM;
536 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
537 GFP_KERNEL);
538 if (!pp->pkt)
539 return -ENOMEM;
540 memset(pp->pkt, 0, QS_PKT_BYTES);
541 ap->private_data = pp;
542
543 qs_enter_reg_mode(ap);
544 addr = (u64)pp->pkt_dma;
545 writel((u32) addr, chan + QS_CCF_CPBA);
546 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
547 return 0;
548 }
549
550 static void qs_host_stop(struct ata_host *host)
551 {
552 void __iomem *mmio_base = qs_mmio_base(host);
553
554 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
555 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
556 }
557
558 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
559 {
560 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
561 unsigned int port_no;
562
563 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
564 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
565
566 /* reset each channel in turn */
567 for (port_no = 0; port_no < host->n_ports; ++port_no) {
568 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
569 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
570 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
571 readb(chan + QS_CCT_CTR0); /* flush */
572 }
573 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
574
575 for (port_no = 0; port_no < host->n_ports; ++port_no) {
576 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
577 /* set FIFO depths to same settings as Windows driver */
578 writew(32, chan + QS_CFC_HUFT);
579 writew(32, chan + QS_CFC_HDFT);
580 writew(10, chan + QS_CFC_DUFT);
581 writew( 8, chan + QS_CFC_DDFT);
582 /* set CPB size in bytes, as a power of two */
583 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
584 }
585 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
586 }
587
588 /*
589 * The QStor understands 64-bit buses, and uses 64-bit fields
590 * for DMA pointers regardless of bus width. We just have to
591 * make sure our DMA masks are set appropriately for whatever
592 * bridge lies between us and the QStor, and then the DMA mapping
593 * code will ensure we only ever "see" appropriate buffer addresses.
594 * If we're 32-bit limited somewhere, then our 64-bit fields will
595 * just end up with zeros in the upper 32-bits, without any special
596 * logic required outside of this routine (below).
597 */
598 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
599 {
600 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
601 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
602
603 if (have_64bit_bus &&
604 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
605 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
606 if (rc) {
607 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
608 if (rc) {
609 dev_printk(KERN_ERR, &pdev->dev,
610 "64-bit DMA enable failed\n");
611 return rc;
612 }
613 }
614 } else {
615 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
616 if (rc) {
617 dev_printk(KERN_ERR, &pdev->dev,
618 "32-bit DMA enable failed\n");
619 return rc;
620 }
621 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
622 if (rc) {
623 dev_printk(KERN_ERR, &pdev->dev,
624 "32-bit consistent DMA enable failed\n");
625 return rc;
626 }
627 }
628 return 0;
629 }
630
631 static int qs_ata_init_one(struct pci_dev *pdev,
632 const struct pci_device_id *ent)
633 {
634 static int printed_version;
635 unsigned int board_idx = (unsigned int) ent->driver_data;
636 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
637 struct ata_host *host;
638 int rc, port_no;
639
640 if (!printed_version++)
641 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
642
643 /* alloc host */
644 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
645 if (!host)
646 return -ENOMEM;
647
648 /* acquire resources and fill host */
649 rc = pcim_enable_device(pdev);
650 if (rc)
651 return rc;
652
653 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
654 return -ENODEV;
655
656 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
657 if (rc)
658 return rc;
659 host->iomap = pcim_iomap_table(pdev);
660
661 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
662 if (rc)
663 return rc;
664
665 for (port_no = 0; port_no < host->n_ports; ++port_no) {
666 struct ata_port *ap = host->ports[port_no];
667 unsigned int offset = port_no * 0x4000;
668 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
669
670 qs_ata_setup_port(&ap->ioaddr, chan);
671
672 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
673 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
674 }
675
676 /* initialize adapter */
677 qs_host_init(host, board_idx);
678
679 pci_set_master(pdev);
680 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
681 &qs_ata_sht);
682 }
683
684 static int __init qs_ata_init(void)
685 {
686 return pci_register_driver(&qs_ata_pci_driver);
687 }
688
689 static void __exit qs_ata_exit(void)
690 {
691 pci_unregister_driver(&qs_ata_pci_driver);
692 }
693
694 MODULE_AUTHOR("Mark Lord");
695 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
696 MODULE_LICENSE("GPL");
697 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
698 MODULE_VERSION(DRV_VERSION);
699
700 module_init(qs_ata_init);
701 module_exit(qs_ata_exit);
WRT350N Kernel Patches