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Initial commit
[wrt350n-kernel.git] / arch / arm / mach-s3c2410 / mach-bast.c
blob66175471fff30492ebf45e8a4518b20af5915344
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
21 #include <linux/dm9000.h>
22
23 #include <net/ax88796.h>
24
25 #include <asm/mach/arch.h>
26 #include <asm/mach/map.h>
27 #include <asm/mach/irq.h>
28
29 #include <asm/arch/bast-map.h>
30 #include <asm/arch/bast-irq.h>
31 #include <asm/arch/bast-cpld.h>
32
33 #include <asm/hardware.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/mach-types.h>
37
38 //#include <asm/debug-ll.h>
39 #include <asm/plat-s3c/regs-serial.h>
40 #include <asm/arch/regs-gpio.h>
41 #include <asm/arch/regs-mem.h>
42 #include <asm/arch/regs-lcd.h>
43
44 #include <asm/plat-s3c/nand.h>
45 #include <asm/plat-s3c/iic.h>
46 #include <asm/arch/fb.h>
47
48 #include <linux/mtd/mtd.h>
49 #include <linux/mtd/nand.h>
50 #include <linux/mtd/nand_ecc.h>
51 #include <linux/mtd/partitions.h>
52
53 #include <linux/serial_8250.h>
54
55 #include <asm/plat-s3c24xx/clock.h>
56 #include <asm/plat-s3c24xx/devs.h>
57 #include <asm/plat-s3c24xx/cpu.h>
58 #include "usb-simtec.h"
59
60 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
61
62 /* macros for virtual address mods for the io space entries */
63 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
64 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
65 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
66 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
67
68 /* macros to modify the physical addresses for io space */
69
70 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
71 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
72 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
73 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
74
75 static struct map_desc bast_iodesc[] __initdata = {
76 /* ISA IO areas */
77 {
78 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
79 .pfn = PA_CS2(BAST_PA_ISAIO),
80 .length = SZ_16M,
81 .type = MT_DEVICE,
82 }, {
83 .virtual = (u32)S3C24XX_VA_ISA_WORD,
84 .pfn = PA_CS3(BAST_PA_ISAIO),
85 .length = SZ_16M,
86 .type = MT_DEVICE,
87 },
88 /* bast CPLD control registers, and external interrupt controls */
89 {
90 .virtual = (u32)BAST_VA_CTRL1,
91 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
92 .length = SZ_1M,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (u32)BAST_VA_CTRL2,
96 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
97 .length = SZ_1M,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (u32)BAST_VA_CTRL3,
101 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
102 .length = SZ_1M,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (u32)BAST_VA_CTRL4,
106 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
107 .length = SZ_1M,
108 .type = MT_DEVICE,
109 },
110 /* PC104 IRQ mux */
111 {
112 .virtual = (u32)BAST_VA_PC104_IRQREQ,
113 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
114 .length = SZ_1M,
115 .type = MT_DEVICE,
116 }, {
117 .virtual = (u32)BAST_VA_PC104_IRQRAW,
118 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
119 .length = SZ_1M,
120 .type = MT_DEVICE,
121 }, {
122 .virtual = (u32)BAST_VA_PC104_IRQMASK,
123 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
124 .length = SZ_1M,
125 .type = MT_DEVICE,
126 },
127
128 /* peripheral space... one for each of fast/slow/byte/16bit */
129 /* note, ide is only decoded in word space, even though some registers
130 * are only 8bit */
131
132 /* slow, byte */
133 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
134 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
135 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
136 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
137 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
138 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
139 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
140
141 /* slow, word */
142 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
145 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
146 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
147 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
148 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
149
150 /* fast, byte */
151 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
152 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
153 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
154 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
155 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
156 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
157 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
158
159 /* fast, word */
160 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
161 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
162 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
163 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
164 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
165 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
166 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
167 };
168
169 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
170 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
171 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
172
173 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
174 [0] = {
175 .name = "uclk",
176 .divisor = 1,
177 .min_baud = 0,
178 .max_baud = 0,
179 },
180 [1] = {
181 .name = "pclk",
182 .divisor = 1,
183 .min_baud = 0,
184 .max_baud = 0,
185 }
186 };
187
188
189 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
190 [0] = {
191 .hwport = 0,
192 .flags = 0,
193 .ucon = UCON,
194 .ulcon = ULCON,
195 .ufcon = UFCON,
196 .clocks = bast_serial_clocks,
197 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
198 },
199 [1] = {
200 .hwport = 1,
201 .flags = 0,
202 .ucon = UCON,
203 .ulcon = ULCON,
204 .ufcon = UFCON,
205 .clocks = bast_serial_clocks,
206 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
207 },
208 /* port 2 is not actually used */
209 [2] = {
210 .hwport = 2,
211 .flags = 0,
212 .ucon = UCON,
213 .ulcon = ULCON,
214 .ufcon = UFCON,
215 .clocks = bast_serial_clocks,
216 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
217 }
218 };
219
220 /* NOR Flash on BAST board */
221
222 static struct resource bast_nor_resource[] = {
223 [0] = {
224 .start = S3C2410_CS1 + 0x4000000,
225 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
226 .flags = IORESOURCE_MEM,
227 }
228 };
229
230 static struct platform_device bast_device_nor = {
231 .name = "bast-nor",
232 .id = -1,
233 .num_resources = ARRAY_SIZE(bast_nor_resource),
234 .resource = bast_nor_resource,
235 };
236
237 /* NAND Flash on BAST board */
238
239
240 static int smartmedia_map[] = { 0 };
241 static int chip0_map[] = { 1 };
242 static int chip1_map[] = { 2 };
243 static int chip2_map[] = { 3 };
244
245 static struct mtd_partition bast_default_nand_part[] = {
246 [0] = {
247 .name = "Boot Agent",
248 .size = SZ_16K,
249 .offset = 0,
250 },
251 [1] = {
252 .name = "/boot",
253 .size = SZ_4M - SZ_16K,
254 .offset = SZ_16K,
255 },
256 [2] = {
257 .name = "user",
258 .offset = SZ_4M,
259 .size = MTDPART_SIZ_FULL,
260 }
261 };
262
263 /* the bast has 4 selectable slots for nand-flash, the three
264 * on-board chip areas, as well as the external SmartMedia
265 * slot.
266 *
267 * Note, there is no current hot-plug support for the SmartMedia
268 * socket.
269 */
270
271 static struct s3c2410_nand_set bast_nand_sets[] = {
272 [0] = {
273 .name = "SmartMedia",
274 .nr_chips = 1,
275 .nr_map = smartmedia_map,
276 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
277 .partitions = bast_default_nand_part,
278 },
279 [1] = {
280 .name = "chip0",
281 .nr_chips = 1,
282 .nr_map = chip0_map,
283 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
284 .partitions = bast_default_nand_part,
285 },
286 [2] = {
287 .name = "chip1",
288 .nr_chips = 1,
289 .nr_map = chip1_map,
290 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
291 .partitions = bast_default_nand_part,
292 },
293 [3] = {
294 .name = "chip2",
295 .nr_chips = 1,
296 .nr_map = chip2_map,
297 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
298 .partitions = bast_default_nand_part,
299 }
300 };
301
302 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
303 {
304 unsigned int tmp;
305
306 slot = set->nr_map[slot] & 3;
307
308 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
309 slot, set, set->nr_map);
310
311 tmp = __raw_readb(BAST_VA_CTRL2);
312 tmp &= BAST_CPLD_CTLR2_IDERST;
313 tmp |= slot;
314 tmp |= BAST_CPLD_CTRL2_WNAND;
315
316 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
317
318 __raw_writeb(tmp, BAST_VA_CTRL2);
319 }
320
321 static struct s3c2410_platform_nand bast_nand_info = {
322 .tacls = 30,
323 .twrph0 = 60,
324 .twrph1 = 60,
325 .nr_sets = ARRAY_SIZE(bast_nand_sets),
326 .sets = bast_nand_sets,
327 .select_chip = bast_nand_select,
328 };
329
330 /* DM9000 */
331
332 static struct resource bast_dm9k_resource[] = {
333 [0] = {
334 .start = S3C2410_CS5 + BAST_PA_DM9000,
335 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
336 .flags = IORESOURCE_MEM,
337 },
338 [1] = {
339 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
340 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
341 .flags = IORESOURCE_MEM,
342 },
343 [2] = {
344 .start = IRQ_DM9000,
345 .end = IRQ_DM9000,
346 .flags = IORESOURCE_IRQ,
347 }
348
349 };
350
351 /* for the moment we limit ourselves to 16bit IO until some
352 * better IO routines can be written and tested
353 */
354
355 static struct dm9000_plat_data bast_dm9k_platdata = {
356 .flags = DM9000_PLATF_16BITONLY,
357 };
358
359 static struct platform_device bast_device_dm9k = {
360 .name = "dm9000",
361 .id = 0,
362 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
363 .resource = bast_dm9k_resource,
364 .dev = {
365 .platform_data = &bast_dm9k_platdata,
366 }
367 };
368
369 /* serial devices */
370
371 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
372 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
373 #define SERIAL_CLK (1843200)
374
375 static struct plat_serial8250_port bast_sio_data[] = {
376 [0] = {
377 .mapbase = SERIAL_BASE + 0x2f8,
378 .irq = IRQ_PCSERIAL1,
379 .flags = SERIAL_FLAGS,
380 .iotype = UPIO_MEM,
381 .regshift = 0,
382 .uartclk = SERIAL_CLK,
383 },
384 [1] = {
385 .mapbase = SERIAL_BASE + 0x3f8,
386 .irq = IRQ_PCSERIAL2,
387 .flags = SERIAL_FLAGS,
388 .iotype = UPIO_MEM,
389 .regshift = 0,
390 .uartclk = SERIAL_CLK,
391 },
392 { }
393 };
394
395 static struct platform_device bast_sio = {
396 .name = "serial8250",
397 .id = PLAT8250_DEV_PLATFORM,
398 .dev = {
399 .platform_data = &bast_sio_data,
400 },
401 };
402
403 /* we have devices on the bus which cannot work much over the
404 * standard 100KHz i2c bus frequency
405 */
406
407 static struct s3c2410_platform_i2c bast_i2c_info = {
408 .flags = 0,
409 .slave_addr = 0x10,
410 .bus_freq = 100*1000,
411 .max_freq = 130*1000,
412 };
413
414 /* Asix AX88796 10/100 ethernet controller */
415
416 static struct ax_plat_data bast_asix_platdata = {
417 .flags = AXFLG_MAC_FROMDEV,
418 .wordlength = 2,
419 .dcr_val = 0x48,
420 .rcr_val = 0x40,
421 };
422
423 static struct resource bast_asix_resource[] = {
424 [0] = {
425 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
426 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
427 .flags = IORESOURCE_MEM,
428 },
429 [1] = {
430 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
431 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
432 .flags = IORESOURCE_MEM,
433 },
434 [2] = {
435 .start = IRQ_ASIX,
436 .end = IRQ_ASIX,
437 .flags = IORESOURCE_IRQ
438 }
439 };
440
441 static struct platform_device bast_device_asix = {
442 .name = "ax88796",
443 .id = 0,
444 .num_resources = ARRAY_SIZE(bast_asix_resource),
445 .resource = bast_asix_resource,
446 .dev = {
447 .platform_data = &bast_asix_platdata
448 }
449 };
450
451 /* Asix AX88796 10/100 ethernet controller parallel port */
452
453 static struct resource bast_asixpp_resource[] = {
454 [0] = {
455 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
456 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
457 .flags = IORESOURCE_MEM,
458 }
459 };
460
461 static struct platform_device bast_device_axpp = {
462 .name = "ax88796-pp",
463 .id = 0,
464 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
465 .resource = bast_asixpp_resource,
466 };
467
468 /* LCD/VGA controller */
469
470 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
471 {
472 .type = S3C2410_LCDCON1_TFT,
473 .width = 640,
474 .height = 480,
475
476 .pixclock = 33333,
477 .xres = 640,
478 .yres = 480,
479 .bpp = 4,
480 .left_margin = 40,
481 .right_margin = 20,
482 .hsync_len = 88,
483 .upper_margin = 30,
484 .lower_margin = 32,
485 .vsync_len = 3,
486
487 .lcdcon5 = 0x00014b02,
488 },
489 {
490 .type = S3C2410_LCDCON1_TFT,
491 .width = 640,
492 .height = 480,
493
494 .pixclock = 33333,
495 .xres = 640,
496 .yres = 480,
497 .bpp = 8,
498 .left_margin = 40,
499 .right_margin = 20,
500 .hsync_len = 88,
501 .upper_margin = 30,
502 .lower_margin = 32,
503 .vsync_len = 3,
504
505 .lcdcon5 = 0x00014b02,
506 },
507 {
508 .type = S3C2410_LCDCON1_TFT,
509 .width = 640,
510 .height = 480,
511
512 .pixclock = 33333,
513 .xres = 640,
514 .yres = 480,
515 .bpp = 16,
516 .left_margin = 40,
517 .right_margin = 20,
518 .hsync_len = 88,
519 .upper_margin = 30,
520 .lower_margin = 32,
521 .vsync_len = 3,
522
523 .lcdcon5 = 0x00014b02,
524 },
525 };
526
527 /* LCD/VGA controller */
528
529 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
530
531 .displays = bast_lcd_info,
532 .num_displays = ARRAY_SIZE(bast_lcd_info),
533 .default_display = 1,
534 };
535
536 /* Standard BAST devices */
537
538 static struct platform_device *bast_devices[] __initdata = {
539 &s3c_device_usb,
540 &s3c_device_lcd,
541 &s3c_device_wdt,
542 &s3c_device_i2c,
543 &s3c_device_rtc,
544 &s3c_device_nand,
545 &bast_device_nor,
546 &bast_device_dm9k,
547 &bast_device_asix,
548 &bast_device_axpp,
549 &bast_sio,
550 };
551
552 static struct clk *bast_clocks[] = {
553 &s3c24xx_dclk0,
554 &s3c24xx_dclk1,
555 &s3c24xx_clkout0,
556 &s3c24xx_clkout1,
557 &s3c24xx_uclk,
558 };
559
560 static void __init bast_map_io(void)
561 {
562 /* initialise the clocks */
563
564 s3c24xx_dclk0.parent = NULL;
565 s3c24xx_dclk0.rate = 12*1000*1000;
566
567 s3c24xx_dclk1.parent = NULL;
568 s3c24xx_dclk1.rate = 24*1000*1000;
569
570 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
571 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
572
573 s3c24xx_uclk.parent = &s3c24xx_clkout1;
574
575 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
576
577 s3c_device_nand.dev.platform_data = &bast_nand_info;
578 s3c_device_i2c.dev.platform_data = &bast_i2c_info;
579
580 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
581 s3c24xx_init_clocks(0);
582 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
583
584 usb_simtec_init();
585 }
586
587 static void __init bast_init(void)
588 {
589 s3c24xx_fb_set_platdata(&bast_fb_info);
590 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
591 }
592
593 MACHINE_START(BAST, "Simtec-BAST")
594 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
595 .phys_io = S3C2410_PA_UART,
596 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
597 .boot_params = S3C2410_SDRAM_PA + 0x100,
598 .map_io = bast_map_io,
599 .init_irq = s3c24xx_init_irq,
600 .init_machine = bast_init,
601 .timer = &s3c24xx_timer,
602 MACHINE_END
WRT350N Kernel Patches