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Initial commit
[wrt350n-kernel.git] / arch / blackfin / mach-bf561 / coreb.c
blob1b44e9e6dc3b6b44956f817d0a56bc622ea4f67b
1 /*
2 * File: arch/blackfin/mach-bf561/coreb.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: Handle CoreB on a BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30 #include <linux/mm.h>
31 #include <linux/miscdevice.h>
32 #include <linux/device.h>
33 #include <linux/ioport.h>
34 #include <linux/module.h>
35 #include <linux/uaccess.h>
36 #include <linux/fs.h>
37 #include <asm/dma.h>
38 #include <asm/cacheflush.h>
39
40 #define MODULE_VER "v0.1"
41
42 static spinlock_t coreb_lock;
43 static wait_queue_head_t coreb_dma_wait;
44
45 #define COREB_IS_OPEN 0x00000001
46 #define COREB_IS_RUNNING 0x00000010
47
48 #define CMD_COREB_INDEX 1
49 #define CMD_COREB_START 2
50 #define CMD_COREB_STOP 3
51 #define CMD_COREB_RESET 4
52
53 #define COREB_MINOR 229
54
55 static unsigned long coreb_status = 0;
56 static unsigned long coreb_base = 0xff600000;
57 static unsigned long coreb_size = 0x4000;
58 int coreb_dma_done;
59
60 static loff_t coreb_lseek(struct file *file, loff_t offset, int origin);
61 static ssize_t coreb_read(struct file *file, char *buf, size_t count,
62 loff_t * ppos);
63 static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
64 loff_t * ppos);
65 static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
66 unsigned long arg);
67 static int coreb_open(struct inode *inode, struct file *file);
68 static int coreb_release(struct inode *inode, struct file *file);
69
70 static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id)
71 {
72 clear_dma_irqstat(CH_MEM_STREAM2_DEST);
73 coreb_dma_done = 1;
74 wake_up_interruptible(&coreb_dma_wait);
75 return IRQ_HANDLED;
76 }
77
78 static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
79 loff_t * ppos)
80 {
81 unsigned long p = *ppos;
82 ssize_t wrote = 0;
83
84 if (p + count > coreb_size)
85 return -EFAULT;
86
87 while (count > 0) {
88 int len = count;
89
90 if (len > PAGE_SIZE)
91 len = PAGE_SIZE;
92
93 coreb_dma_done = 0;
94
95 flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
96 /* Source Channel */
97 set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
98 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
99 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
100 set_dma_config(CH_MEM_STREAM2_SRC, 0);
101 /* Destination Channel */
102 set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
103 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
104 set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
105 set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
106
107 enable_dma(CH_MEM_STREAM2_SRC);
108 enable_dma(CH_MEM_STREAM2_DEST);
109
110 wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
111
112 disable_dma(CH_MEM_STREAM2_SRC);
113 disable_dma(CH_MEM_STREAM2_DEST);
114
115 count -= len;
116 wrote += len;
117 buf += len;
118 p += len;
119 }
120 *ppos = p;
121 return wrote;
122 }
123
124 static ssize_t coreb_read(struct file *file, char *buf, size_t count,
125 loff_t * ppos)
126 {
127 unsigned long p = *ppos;
128 ssize_t read = 0;
129
130 if ((p + count) > coreb_size)
131 return -EFAULT;
132
133 while (count > 0) {
134 int len = count;
135
136 if (len > PAGE_SIZE)
137 len = PAGE_SIZE;
138
139 coreb_dma_done = 0;
140
141 invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
142 /* Source Channel */
143 set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
144 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
145 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
146 set_dma_config(CH_MEM_STREAM2_SRC, 0);
147 /* Destination Channel */
148 set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
149 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
150 set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
151 set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
152
153 enable_dma(CH_MEM_STREAM2_SRC);
154 enable_dma(CH_MEM_STREAM2_DEST);
155
156 wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
157
158 disable_dma(CH_MEM_STREAM2_SRC);
159 disable_dma(CH_MEM_STREAM2_DEST);
160
161 count -= len;
162 read += len;
163 buf += len;
164 p += len;
165 }
166
167 return read;
168 }
169
170 static loff_t coreb_lseek(struct file *file, loff_t offset, int origin)
171 {
172 loff_t ret;
173
174 mutex_lock(&file->f_dentry->d_inode->i_mutex);
175
176 switch (origin) {
177 case 0 /* SEEK_SET */ :
178 if (offset < coreb_size) {
179 file->f_pos = offset;
180 ret = file->f_pos;
181 } else
182 ret = -EINVAL;
183 break;
184 case 1 /* SEEK_CUR */ :
185 if ((offset + file->f_pos) < coreb_size) {
186 file->f_pos += offset;
187 ret = file->f_pos;
188 } else
189 ret = -EINVAL;
190 default:
191 ret = -EINVAL;
192 }
193 mutex_unlock(&file->f_dentry->d_inode->i_mutex);
194 return ret;
195 }
196
197 static int coreb_open(struct inode *inode, struct file *file)
198 {
199 spin_lock_irq(&coreb_lock);
200
201 if (coreb_status & COREB_IS_OPEN)
202 goto out_busy;
203
204 coreb_status |= COREB_IS_OPEN;
205
206 spin_unlock_irq(&coreb_lock);
207 return 0;
208
209 out_busy:
210 spin_unlock_irq(&coreb_lock);
211 return -EBUSY;
212 }
213
214 static int coreb_release(struct inode *inode, struct file *file)
215 {
216 spin_lock_irq(&coreb_lock);
217 coreb_status &= ~COREB_IS_OPEN;
218 spin_unlock_irq(&coreb_lock);
219 return 0;
220 }
221
222 static int coreb_ioctl(struct inode *inode, struct file *file,
223 unsigned int cmd, unsigned long arg)
224 {
225 int retval = 0;
226 int coreb_index = 0;
227
228 switch (cmd) {
229 case CMD_COREB_INDEX:
230 if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) {
231 retval = -EFAULT;
232 break;
233 }
234
235 spin_lock_irq(&coreb_lock);
236 switch (coreb_index) {
237 case 0:
238 coreb_base = 0xff600000;
239 coreb_size = 0x4000;
240 break;
241 case 1:
242 coreb_base = 0xff610000;
243 coreb_size = 0x4000;
244 break;
245 case 2:
246 coreb_base = 0xff500000;
247 coreb_size = 0x8000;
248 break;
249 case 3:
250 coreb_base = 0xff400000;
251 coreb_size = 0x8000;
252 break;
253 default:
254 retval = -EINVAL;
255 break;
256 }
257 spin_unlock_irq(&coreb_lock);
258
259 mutex_lock(&file->f_dentry->d_inode->i_mutex);
260 file->f_pos = 0;
261 mutex_unlock(&file->f_dentry->d_inode->i_mutex);
262 break;
263 case CMD_COREB_START:
264 spin_lock_irq(&coreb_lock);
265 if (coreb_status & COREB_IS_RUNNING) {
266 retval = -EBUSY;
267 break;
268 }
269 printk(KERN_INFO "Starting Core B\n");
270 coreb_status |= COREB_IS_RUNNING;
271 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
272 SSYNC();
273 spin_unlock_irq(&coreb_lock);
274 break;
275 #if defined(CONFIG_BF561_COREB_RESET)
276 case CMD_COREB_STOP:
277 spin_lock_irq(&coreb_lock);
278 printk(KERN_INFO "Stopping Core B\n");
279 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
280 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
281 coreb_status &= ~COREB_IS_RUNNING;
282 spin_unlock_irq(&coreb_lock);
283 break;
284 case CMD_COREB_RESET:
285 printk(KERN_INFO "Resetting Core B\n");
286 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
287 break;
288 #endif
289 }
290
291 return retval;
292 }
293
294 static struct file_operations coreb_fops = {
295 .owner = THIS_MODULE,
296 .llseek = coreb_lseek,
297 .read = coreb_read,
298 .write = coreb_write,
299 .ioctl = coreb_ioctl,
300 .open = coreb_open,
301 .release = coreb_release
302 };
303
304 static struct miscdevice coreb_dev = {
305 COREB_MINOR,
306 "coreb",
307 &coreb_fops
308 };
309
310 static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf)
311 {
312 return sprintf(buf,
313 "Base Address:\t0x%08lx\n"
314 "Core B is %s\n"
315 "SICA_SYSCR:\t%04x\n"
316 "SICB_SYSCR:\t%04x\n"
317 "\n"
318 "IRQ Status:\tCore A\t\tCore B\n"
319 "ISR0:\t\t%08x\t\t%08x\n"
320 "ISR1:\t\t%08x\t\t%08x\n"
321 "IMASK0:\t\t%08x\t\t%08x\n"
322 "IMASK1:\t\t%08x\t\t%08x\n",
323 coreb_base,
324 coreb_status & COREB_IS_RUNNING ? "running" : "stalled",
325 bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(),
326 bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(),
327 bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(),
328 bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(),
329 bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1());
330 }
331
332 static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL);
333
334 int __init bf561_coreb_init(void)
335 {
336 init_waitqueue_head(&coreb_dma_wait);
337
338 spin_lock_init(&coreb_lock);
339 /* Request the core memory regions for Core B */
340 if (request_mem_region(0xff600000, 0x4000,
341 "Core B - Instruction SRAM") == NULL)
342 goto exit;
343
344 if (request_mem_region(0xFF610000, 0x4000,
345 "Core B - Instruction SRAM") == NULL)
346 goto release_instruction_a_sram;
347
348 if (request_mem_region(0xFF500000, 0x8000,
349 "Core B - Data Bank B SRAM") == NULL)
350 goto release_instruction_b_sram;
351
352 if (request_mem_region(0xff400000, 0x8000,
353 "Core B - Data Bank A SRAM") == NULL)
354 goto release_data_b_sram;
355
356 if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0)
357 goto release_data_a_sram;
358
359 if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0)
360 goto release_dma_dest;
361
362 set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL);
363
364 misc_register(&coreb_dev);
365
366 if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status))
367 goto release_dma_src;
368
369 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
370 return 0;
371
372 release_dma_src:
373 free_dma(CH_MEM_STREAM2_SRC);
374 release_dma_dest:
375 free_dma(CH_MEM_STREAM2_DEST);
376 release_data_a_sram:
377 release_mem_region(0xff400000, 0x8000);
378 release_data_b_sram:
379 release_mem_region(0xff500000, 0x8000);
380 release_instruction_b_sram:
381 release_mem_region(0xff610000, 0x4000);
382 release_instruction_a_sram:
383 release_mem_region(0xff600000, 0x4000);
384 exit:
385 return -ENOMEM;
386 }
387
388 void __exit bf561_coreb_exit(void)
389 {
390 device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status);
391 misc_deregister(&coreb_dev);
392
393 release_mem_region(0xff610000, 0x4000);
394 release_mem_region(0xff600000, 0x4000);
395 release_mem_region(0xff500000, 0x8000);
396 release_mem_region(0xff400000, 0x8000);
397
398 free_dma(CH_MEM_STREAM2_DEST);
399 free_dma(CH_MEM_STREAM2_SRC);
400 }
401
402 module_init(bf561_coreb_init);
403 module_exit(bf561_coreb_exit);
404
405 MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
406 MODULE_DESCRIPTION("BF561 Core B Support");
WRT350N Kernel Patches