arch/mips/au1000/pb1000/board_setup.c

   1 /*
   2  * Copyright 2000 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ppopov@mvista.com or source@mvista.com
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  12  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  14  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  15  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  16  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  17  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  18  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  19  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  20  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  *
  22  *  You should have received a copy of the  GNU General Public License along
  23  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  24  *  675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26 #include <linux/init.h>
  27 #include <linux/sched.h>
  28 #include <linux/ioport.h>
  29 #include <linux/mm.h>
  30 #include <linux/console.h>
  31 #include <linux/delay.h>
  32
  33 #include <asm/cpu.h>
  34 #include <asm/bootinfo.h>
  35 #include <asm/irq.h>
  36 #include <asm/mipsregs.h>
  37 #include <asm/reboot.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/mach-au1x00/au1000.h>
  40 #include <asm/mach-pb1x00/pb1000.h>
  41
  42 void board_reset(void)
  43 {
  44 }
  45
  46 void __init board_setup(void)
  47 {
  48         u32 pin_func, static_cfg0;
  49         u32 sys_freqctrl, sys_clksrc;
  50         u32 prid = read_c0_prid();
  51
  52         // set AUX clock to 12MHz * 8 = 96 MHz
  53         au_writel(8, SYS_AUXPLL);
  54         au_writel(0, SYS_PINSTATERD);
  55         udelay(100);
  56
  57 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  58         /* zero and disable FREQ2 */
  59         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  60         sys_freqctrl &= ~0xFFF00000;
  61         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  62
  63         /* zero and disable USBH/USBD clocks */
  64         sys_clksrc = au_readl(SYS_CLKSRC);
  65         sys_clksrc &= ~0x00007FE0;
  66         au_writel(sys_clksrc, SYS_CLKSRC);
  67
  68         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  69         sys_freqctrl &= ~0xFFF00000;
  70
  71         sys_clksrc = au_readl(SYS_CLKSRC);
  72         sys_clksrc &= ~0x00007FE0;
  73
  74         switch (prid & 0x000000FF)
  75         {
  76         case 0x00: /* DA */
  77         case 0x01: /* HA */
  78         case 0x02: /* HB */
  79         /* CPU core freq to 48MHz to slow it way down... */
  80         au_writel(4, SYS_CPUPLL);
  81
  82         /*
  83          * Setup 48MHz FREQ2 from CPUPLL for USB Host
  84          */
  85         /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
  86         sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
  87         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  88
  89         /* CPU core freq to 384MHz */
  90         au_writel(0x20, SYS_CPUPLL);
  91
  92         printk("Au1000: 48MHz OHCI workaround enabled\n");
  93                 break;
  94
  95         default:  /* HC and newer */
  96         // FREQ2 = aux/2 = 48 MHz
  97         sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
  98         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  99                 break;
 100         }
 101
 102         /*
 103          * Route 48MHz FREQ2 into USB Host and/or Device
 104          */
 105 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 106         sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
 107 #endif
 108         au_writel(sys_clksrc, SYS_CLKSRC);
 109
 110         // configure pins GPIO[14:9] as GPIO
 111         pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
 112
 113         // 2nd USB port is USB host
 114         pin_func |= 0x8000;
 115
 116         au_writel(pin_func, SYS_PINFUNC);
 117         au_writel(0x2800, SYS_TRIOUTCLR);
 118         au_writel(0x0030, SYS_OUTPUTCLR);
 119 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 120
 121         // make gpio 15 an input (for interrupt line)
 122         pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
 123         // we don't need I2S, so make it available for GPIO[31:29]
 124         pin_func |= (1<<5);
 125         au_writel(pin_func, SYS_PINFUNC);
 126
 127         au_writel(0x8000, SYS_TRIOUTCLR);
 128
 129         static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
 130         au_writel(static_cfg0, MEM_STCFG0);
 131
 132         // configure RCE2* for LCD
 133         au_writel(0x00000004, MEM_STCFG2);
 134
 135         // MEM_STTIME2
 136         au_writel(0x09000000, MEM_STTIME2);
 137
 138         // Set 32-bit base address decoding for RCE2*
 139         au_writel(0x10003ff0, MEM_STADDR2);
 140
 141         // PCI CPLD setup
 142         // expand CE0 to cover PCI
 143         au_writel(0x11803e40, MEM_STADDR1);
 144
 145         // burst visibility on
 146         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 147
 148         au_writel(0x83, MEM_STCFG1);         // ewait enabled, flash timing
 149         au_writel(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
 150
 151         /* setup the static bus controller */
 152         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 153         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 154         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 155
 156 #ifdef CONFIG_PCI
 157         au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
 158         au_writel(0, SDRAM_MBAR);        // set mbar to 0
 159         au_writel(0x2, SDRAM_CMD);       // enable memory accesses
 160         au_sync_delay(1);
 161 #endif
 162
 163         /* Enable Au1000 BCLK switching - note: sed1356 must not use
 164          * its BCLK (Au1000 LCLK) for any timings */
 165         switch (prid & 0x000000FF)
 166         {
 167         case 0x00: /* DA */
 168         case 0x01: /* HA */
 169         case 0x02: /* HB */
 170                 break;
 171         default:  /* HC and newer */
 172                 /* Enable sys bus clock divider when IDLE state or no bus
 173                    activity. */
 174                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 175                 break;
 176         }
 177 }