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Initial commit
[wrt350n-kernel.git] / arch / powerpc / sysdev / mpic.c
blob6ffdda244bb1525f2fcd64413385997cb85e1954
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38
39 #include "mpic.h"
40
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
54 #else
55 #define distribute_irqs (0)
56 #endif
57 #endif
58
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
62 MPIC_GREG_BASE,
63 MPIC_GREG_FEATURE_0,
64 MPIC_GREG_GLOBAL_CONF_0,
65 MPIC_GREG_VENDOR_ID,
66 MPIC_GREG_IPI_VECTOR_PRI_0,
67 MPIC_GREG_IPI_STRIDE,
68 MPIC_GREG_SPURIOUS,
69 MPIC_GREG_TIMER_FREQ,
70
71 MPIC_TIMER_BASE,
72 MPIC_TIMER_STRIDE,
73 MPIC_TIMER_CURRENT_CNT,
74 MPIC_TIMER_BASE_CNT,
75 MPIC_TIMER_VECTOR_PRI,
76 MPIC_TIMER_DESTINATION,
77
78 MPIC_CPU_BASE,
79 MPIC_CPU_STRIDE,
80 MPIC_CPU_IPI_DISPATCH_0,
81 MPIC_CPU_IPI_DISPATCH_STRIDE,
82 MPIC_CPU_CURRENT_TASK_PRI,
83 MPIC_CPU_WHOAMI,
84 MPIC_CPU_INTACK,
85 MPIC_CPU_EOI,
86 MPIC_CPU_MCACK,
87
88 MPIC_IRQ_BASE,
89 MPIC_IRQ_STRIDE,
90 MPIC_IRQ_VECTOR_PRI,
91 MPIC_VECPRI_VECTOR_MASK,
92 MPIC_VECPRI_POLARITY_POSITIVE,
93 MPIC_VECPRI_POLARITY_NEGATIVE,
94 MPIC_VECPRI_SENSE_LEVEL,
95 MPIC_VECPRI_SENSE_EDGE,
96 MPIC_VECPRI_POLARITY_MASK,
97 MPIC_VECPRI_SENSE_MASK,
98 MPIC_IRQ_DESTINATION
99 },
100 [1] = { /* Tsi108/109 PIC */
101 TSI108_GREG_BASE,
102 TSI108_GREG_FEATURE_0,
103 TSI108_GREG_GLOBAL_CONF_0,
104 TSI108_GREG_VENDOR_ID,
105 TSI108_GREG_IPI_VECTOR_PRI_0,
106 TSI108_GREG_IPI_STRIDE,
107 TSI108_GREG_SPURIOUS,
108 TSI108_GREG_TIMER_FREQ,
109
110 TSI108_TIMER_BASE,
111 TSI108_TIMER_STRIDE,
112 TSI108_TIMER_CURRENT_CNT,
113 TSI108_TIMER_BASE_CNT,
114 TSI108_TIMER_VECTOR_PRI,
115 TSI108_TIMER_DESTINATION,
116
117 TSI108_CPU_BASE,
118 TSI108_CPU_STRIDE,
119 TSI108_CPU_IPI_DISPATCH_0,
120 TSI108_CPU_IPI_DISPATCH_STRIDE,
121 TSI108_CPU_CURRENT_TASK_PRI,
122 TSI108_CPU_WHOAMI,
123 TSI108_CPU_INTACK,
124 TSI108_CPU_EOI,
125 TSI108_CPU_MCACK,
126
127 TSI108_IRQ_BASE,
128 TSI108_IRQ_STRIDE,
129 TSI108_IRQ_VECTOR_PRI,
130 TSI108_VECPRI_VECTOR_MASK,
131 TSI108_VECPRI_POLARITY_POSITIVE,
132 TSI108_VECPRI_POLARITY_NEGATIVE,
133 TSI108_VECPRI_SENSE_LEVEL,
134 TSI108_VECPRI_SENSE_EDGE,
135 TSI108_VECPRI_POLARITY_MASK,
136 TSI108_VECPRI_SENSE_MASK,
137 TSI108_IRQ_DESTINATION
138 },
139 };
140
141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
142
143 #else /* CONFIG_MPIC_WEIRD */
144
145 #define MPIC_INFO(name) MPIC_##name
146
147 #endif /* CONFIG_MPIC_WEIRD */
148
149 /*
150 * Register accessor functions
151 */
152
153
154 static inline u32 _mpic_read(enum mpic_reg_type type,
155 struct mpic_reg_bank *rb,
156 unsigned int reg)
157 {
158 switch(type) {
159 #ifdef CONFIG_PPC_DCR
160 case mpic_access_dcr:
161 return dcr_read(rb->dhost, reg);
162 #endif
163 case mpic_access_mmio_be:
164 return in_be32(rb->base + (reg >> 2));
165 case mpic_access_mmio_le:
166 default:
167 return in_le32(rb->base + (reg >> 2));
168 }
169 }
170
171 static inline void _mpic_write(enum mpic_reg_type type,
172 struct mpic_reg_bank *rb,
173 unsigned int reg, u32 value)
174 {
175 switch(type) {
176 #ifdef CONFIG_PPC_DCR
177 case mpic_access_dcr:
178 return dcr_write(rb->dhost, reg, value);
179 #endif
180 case mpic_access_mmio_be:
181 return out_be32(rb->base + (reg >> 2), value);
182 case mpic_access_mmio_le:
183 default:
184 return out_le32(rb->base + (reg >> 2), value);
185 }
186 }
187
188 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
189 {
190 enum mpic_reg_type type = mpic->reg_type;
191 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
192 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
193
194 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
195 type = mpic_access_mmio_be;
196 return _mpic_read(type, &mpic->gregs, offset);
197 }
198
199 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
200 {
201 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
202 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
203
204 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
205 }
206
207 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
208 {
209 unsigned int cpu = 0;
210
211 if (mpic->flags & MPIC_PRIMARY)
212 cpu = hard_smp_processor_id();
213 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
214 }
215
216 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
217 {
218 unsigned int cpu = 0;
219
220 if (mpic->flags & MPIC_PRIMARY)
221 cpu = hard_smp_processor_id();
222
223 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
224 }
225
226 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
227 {
228 unsigned int isu = src_no >> mpic->isu_shift;
229 unsigned int idx = src_no & mpic->isu_mask;
230
231 #ifdef CONFIG_MPIC_BROKEN_REGREAD
232 if (reg == 0)
233 return mpic->isu_reg0_shadow[idx];
234 else
235 #endif
236 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
237 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
238 }
239
240 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
241 unsigned int reg, u32 value)
242 {
243 unsigned int isu = src_no >> mpic->isu_shift;
244 unsigned int idx = src_no & mpic->isu_mask;
245
246 _mpic_write(mpic->reg_type, &mpic->isus[isu],
247 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
248
249 #ifdef CONFIG_MPIC_BROKEN_REGREAD
250 if (reg == 0)
251 mpic->isu_reg0_shadow[idx] = value;
252 #endif
253 }
254
255 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
256 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
257 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
258 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
259 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
260 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
261 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
262 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
263
264
265 /*
266 * Low level utility functions
267 */
268
269
270 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
271 struct mpic_reg_bank *rb, unsigned int offset,
272 unsigned int size)
273 {
274 rb->base = ioremap(phys_addr + offset, size);
275 BUG_ON(rb->base == NULL);
276 }
277
278 #ifdef CONFIG_PPC_DCR
279 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
280 unsigned int offset, unsigned int size)
281 {
282 const u32 *dbasep;
283
284 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
285
286 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
287 BUG_ON(!DCR_MAP_OK(rb->dhost));
288 }
289
290 static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
291 struct mpic_reg_bank *rb, unsigned int offset,
292 unsigned int size)
293 {
294 if (mpic->flags & MPIC_USES_DCR)
295 _mpic_map_dcr(mpic, rb, offset, size);
296 else
297 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
298 }
299 #else /* CONFIG_PPC_DCR */
300 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
301 #endif /* !CONFIG_PPC_DCR */
302
303
304
305 /* Check if we have one of those nice broken MPICs with a flipped endian on
306 * reads from IPI registers
307 */
308 static void __init mpic_test_broken_ipi(struct mpic *mpic)
309 {
310 u32 r;
311
312 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
313 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
314
315 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
316 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
317 mpic->flags |= MPIC_BROKEN_IPI;
318 }
319 }
320
321 #ifdef CONFIG_MPIC_U3_HT_IRQS
322
323 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
324 * to force the edge setting on the MPIC and do the ack workaround.
325 */
326 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
327 {
328 if (source >= 128 || !mpic->fixups)
329 return 0;
330 return mpic->fixups[source].base != NULL;
331 }
332
333
334 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
335 {
336 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
337
338 if (fixup->applebase) {
339 unsigned int soff = (fixup->index >> 3) & ~3;
340 unsigned int mask = 1U << (fixup->index & 0x1f);
341 writel(mask, fixup->applebase + soff);
342 } else {
343 spin_lock(&mpic->fixup_lock);
344 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
345 writel(fixup->data, fixup->base + 4);
346 spin_unlock(&mpic->fixup_lock);
347 }
348 }
349
350 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
351 unsigned int irqflags)
352 {
353 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
354 unsigned long flags;
355 u32 tmp;
356
357 if (fixup->base == NULL)
358 return;
359
360 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
361 source, irqflags, fixup->index);
362 spin_lock_irqsave(&mpic->fixup_lock, flags);
363 /* Enable and configure */
364 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
365 tmp = readl(fixup->base + 4);
366 tmp &= ~(0x23U);
367 if (irqflags & IRQ_LEVEL)
368 tmp |= 0x22;
369 writel(tmp, fixup->base + 4);
370 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
371
372 #ifdef CONFIG_PM
373 /* use the lowest bit inverted to the actual HW,
374 * set if this fixup was enabled, clear otherwise */
375 mpic->save_data[source].fixup_data = tmp | 1;
376 #endif
377 }
378
379 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
380 unsigned int irqflags)
381 {
382 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
383 unsigned long flags;
384 u32 tmp;
385
386 if (fixup->base == NULL)
387 return;
388
389 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
390
391 /* Disable */
392 spin_lock_irqsave(&mpic->fixup_lock, flags);
393 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
394 tmp = readl(fixup->base + 4);
395 tmp |= 1;
396 writel(tmp, fixup->base + 4);
397 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
398
399 #ifdef CONFIG_PM
400 /* use the lowest bit inverted to the actual HW,
401 * set if this fixup was enabled, clear otherwise */
402 mpic->save_data[source].fixup_data = tmp & ~1;
403 #endif
404 }
405
406 #ifdef CONFIG_PCI_MSI
407 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
408 unsigned int devfn)
409 {
410 u8 __iomem *base;
411 u8 pos, flags;
412 u64 addr = 0;
413
414 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
415 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
416 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
417 if (id == PCI_CAP_ID_HT) {
418 id = readb(devbase + pos + 3);
419 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
420 break;
421 }
422 }
423
424 if (pos == 0)
425 return;
426
427 base = devbase + pos;
428
429 flags = readb(base + HT_MSI_FLAGS);
430 if (!(flags & HT_MSI_FLAGS_FIXED)) {
431 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
432 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
433 }
434
435 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
436 PCI_SLOT(devfn), PCI_FUNC(devfn),
437 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
438
439 if (!(flags & HT_MSI_FLAGS_ENABLE))
440 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
441 }
442 #else
443 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
444 unsigned int devfn)
445 {
446 return;
447 }
448 #endif
449
450 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
451 unsigned int devfn, u32 vdid)
452 {
453 int i, irq, n;
454 u8 __iomem *base;
455 u32 tmp;
456 u8 pos;
457
458 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
459 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
460 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
461 if (id == PCI_CAP_ID_HT) {
462 id = readb(devbase + pos + 3);
463 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
464 break;
465 }
466 }
467 if (pos == 0)
468 return;
469
470 base = devbase + pos;
471 writeb(0x01, base + 2);
472 n = (readl(base + 4) >> 16) & 0xff;
473
474 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
475 " has %d irqs\n",
476 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
477
478 for (i = 0; i <= n; i++) {
479 writeb(0x10 + 2 * i, base + 2);
480 tmp = readl(base + 4);
481 irq = (tmp >> 16) & 0xff;
482 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
483 /* mask it , will be unmasked later */
484 tmp |= 0x1;
485 writel(tmp, base + 4);
486 mpic->fixups[irq].index = i;
487 mpic->fixups[irq].base = base;
488 /* Apple HT PIC has a non-standard way of doing EOIs */
489 if ((vdid & 0xffff) == 0x106b)
490 mpic->fixups[irq].applebase = devbase + 0x60;
491 else
492 mpic->fixups[irq].applebase = NULL;
493 writeb(0x11 + 2 * i, base + 2);
494 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
495 }
496 }
497
498
499 static void __init mpic_scan_ht_pics(struct mpic *mpic)
500 {
501 unsigned int devfn;
502 u8 __iomem *cfgspace;
503
504 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
505
506 /* Allocate fixups array */
507 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
508 BUG_ON(mpic->fixups == NULL);
509 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
510
511 /* Init spinlock */
512 spin_lock_init(&mpic->fixup_lock);
513
514 /* Map U3 config space. We assume all IO-APICs are on the primary bus
515 * so we only need to map 64kB.
516 */
517 cfgspace = ioremap(0xf2000000, 0x10000);
518 BUG_ON(cfgspace == NULL);
519
520 /* Now we scan all slots. We do a very quick scan, we read the header
521 * type, vendor ID and device ID only, that's plenty enough
522 */
523 for (devfn = 0; devfn < 0x100; devfn++) {
524 u8 __iomem *devbase = cfgspace + (devfn << 8);
525 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
526 u32 l = readl(devbase + PCI_VENDOR_ID);
527 u16 s;
528
529 DBG("devfn %x, l: %x\n", devfn, l);
530
531 /* If no device, skip */
532 if (l == 0xffffffff || l == 0x00000000 ||
533 l == 0x0000ffff || l == 0xffff0000)
534 goto next;
535 /* Check if is supports capability lists */
536 s = readw(devbase + PCI_STATUS);
537 if (!(s & PCI_STATUS_CAP_LIST))
538 goto next;
539
540 mpic_scan_ht_pic(mpic, devbase, devfn, l);
541 mpic_scan_ht_msi(mpic, devbase, devfn);
542
543 next:
544 /* next device, if function 0 */
545 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
546 devfn += 7;
547 }
548 }
549
550 #else /* CONFIG_MPIC_U3_HT_IRQS */
551
552 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
553 {
554 return 0;
555 }
556
557 static void __init mpic_scan_ht_pics(struct mpic *mpic)
558 {
559 }
560
561 #endif /* CONFIG_MPIC_U3_HT_IRQS */
562
563
564 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
565
566 /* Find an mpic associated with a given linux interrupt */
567 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
568 {
569 unsigned int src = mpic_irq_to_hw(irq);
570 struct mpic *mpic;
571
572 if (irq < NUM_ISA_INTERRUPTS)
573 return NULL;
574
575 mpic = irq_desc[irq].chip_data;
576
577 if (is_ipi)
578 *is_ipi = (src >= mpic->ipi_vecs[0] &&
579 src <= mpic->ipi_vecs[3]);
580
581 return mpic;
582 }
583
584 /* Convert a cpu mask from logical to physical cpu numbers. */
585 static inline u32 mpic_physmask(u32 cpumask)
586 {
587 int i;
588 u32 mask = 0;
589
590 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
591 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
592 return mask;
593 }
594
595 #ifdef CONFIG_SMP
596 /* Get the mpic structure from the IPI number */
597 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
598 {
599 return irq_desc[ipi].chip_data;
600 }
601 #endif
602
603 /* Get the mpic structure from the irq number */
604 static inline struct mpic * mpic_from_irq(unsigned int irq)
605 {
606 return irq_desc[irq].chip_data;
607 }
608
609 /* Send an EOI */
610 static inline void mpic_eoi(struct mpic *mpic)
611 {
612 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
613 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
614 }
615
616 #ifdef CONFIG_SMP
617 static irqreturn_t mpic_ipi_action(int irq, void *data)
618 {
619 long ipi = (long)data;
620
621 smp_message_recv(ipi);
622
623 return IRQ_HANDLED;
624 }
625 #endif /* CONFIG_SMP */
626
627 /*
628 * Linux descriptor level callbacks
629 */
630
631
632 void mpic_unmask_irq(unsigned int irq)
633 {
634 unsigned int loops = 100000;
635 struct mpic *mpic = mpic_from_irq(irq);
636 unsigned int src = mpic_irq_to_hw(irq);
637
638 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
639
640 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
641 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
642 ~MPIC_VECPRI_MASK);
643 /* make sure mask gets to controller before we return to user */
644 do {
645 if (!loops--) {
646 printk(KERN_ERR "mpic_enable_irq timeout\n");
647 break;
648 }
649 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
650 }
651
652 void mpic_mask_irq(unsigned int irq)
653 {
654 unsigned int loops = 100000;
655 struct mpic *mpic = mpic_from_irq(irq);
656 unsigned int src = mpic_irq_to_hw(irq);
657
658 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
659
660 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
661 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
662 MPIC_VECPRI_MASK);
663
664 /* make sure mask gets to controller before we return to user */
665 do {
666 if (!loops--) {
667 printk(KERN_ERR "mpic_enable_irq timeout\n");
668 break;
669 }
670 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
671 }
672
673 void mpic_end_irq(unsigned int irq)
674 {
675 struct mpic *mpic = mpic_from_irq(irq);
676
677 #ifdef DEBUG_IRQ
678 DBG("%s: end_irq: %d\n", mpic->name, irq);
679 #endif
680 /* We always EOI on end_irq() even for edge interrupts since that
681 * should only lower the priority, the MPIC should have properly
682 * latched another edge interrupt coming in anyway
683 */
684
685 mpic_eoi(mpic);
686 }
687
688 #ifdef CONFIG_MPIC_U3_HT_IRQS
689
690 static void mpic_unmask_ht_irq(unsigned int irq)
691 {
692 struct mpic *mpic = mpic_from_irq(irq);
693 unsigned int src = mpic_irq_to_hw(irq);
694
695 mpic_unmask_irq(irq);
696
697 if (irq_desc[irq].status & IRQ_LEVEL)
698 mpic_ht_end_irq(mpic, src);
699 }
700
701 static unsigned int mpic_startup_ht_irq(unsigned int irq)
702 {
703 struct mpic *mpic = mpic_from_irq(irq);
704 unsigned int src = mpic_irq_to_hw(irq);
705
706 mpic_unmask_irq(irq);
707 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
708
709 return 0;
710 }
711
712 static void mpic_shutdown_ht_irq(unsigned int irq)
713 {
714 struct mpic *mpic = mpic_from_irq(irq);
715 unsigned int src = mpic_irq_to_hw(irq);
716
717 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
718 mpic_mask_irq(irq);
719 }
720
721 static void mpic_end_ht_irq(unsigned int irq)
722 {
723 struct mpic *mpic = mpic_from_irq(irq);
724 unsigned int src = mpic_irq_to_hw(irq);
725
726 #ifdef DEBUG_IRQ
727 DBG("%s: end_irq: %d\n", mpic->name, irq);
728 #endif
729 /* We always EOI on end_irq() even for edge interrupts since that
730 * should only lower the priority, the MPIC should have properly
731 * latched another edge interrupt coming in anyway
732 */
733
734 if (irq_desc[irq].status & IRQ_LEVEL)
735 mpic_ht_end_irq(mpic, src);
736 mpic_eoi(mpic);
737 }
738 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
739
740 #ifdef CONFIG_SMP
741
742 static void mpic_unmask_ipi(unsigned int irq)
743 {
744 struct mpic *mpic = mpic_from_ipi(irq);
745 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
746
747 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
748 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
749 }
750
751 static void mpic_mask_ipi(unsigned int irq)
752 {
753 /* NEVER disable an IPI... that's just plain wrong! */
754 }
755
756 static void mpic_end_ipi(unsigned int irq)
757 {
758 struct mpic *mpic = mpic_from_ipi(irq);
759
760 /*
761 * IPIs are marked IRQ_PER_CPU. This has the side effect of
762 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
763 * applying to them. We EOI them late to avoid re-entering.
764 * We mark IPI's with IRQF_DISABLED as they must run with
765 * irqs disabled.
766 */
767 mpic_eoi(mpic);
768 }
769
770 #endif /* CONFIG_SMP */
771
772 void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
773 {
774 struct mpic *mpic = mpic_from_irq(irq);
775 unsigned int src = mpic_irq_to_hw(irq);
776
777 cpumask_t tmp;
778
779 cpus_and(tmp, cpumask, cpu_online_map);
780
781 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
782 mpic_physmask(cpus_addr(tmp)[0]));
783 }
784
785 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
786 {
787 /* Now convert sense value */
788 switch(type & IRQ_TYPE_SENSE_MASK) {
789 case IRQ_TYPE_EDGE_RISING:
790 return MPIC_INFO(VECPRI_SENSE_EDGE) |
791 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
792 case IRQ_TYPE_EDGE_FALLING:
793 case IRQ_TYPE_EDGE_BOTH:
794 return MPIC_INFO(VECPRI_SENSE_EDGE) |
795 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
796 case IRQ_TYPE_LEVEL_HIGH:
797 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
798 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
799 case IRQ_TYPE_LEVEL_LOW:
800 default:
801 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
802 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
803 }
804 }
805
806 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
807 {
808 struct mpic *mpic = mpic_from_irq(virq);
809 unsigned int src = mpic_irq_to_hw(virq);
810 struct irq_desc *desc = get_irq_desc(virq);
811 unsigned int vecpri, vold, vnew;
812
813 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
814 mpic, virq, src, flow_type);
815
816 if (src >= mpic->irq_count)
817 return -EINVAL;
818
819 if (flow_type == IRQ_TYPE_NONE)
820 if (mpic->senses && src < mpic->senses_count)
821 flow_type = mpic->senses[src];
822 if (flow_type == IRQ_TYPE_NONE)
823 flow_type = IRQ_TYPE_LEVEL_LOW;
824
825 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
826 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
827 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
828 desc->status |= IRQ_LEVEL;
829
830 if (mpic_is_ht_interrupt(mpic, src))
831 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
832 MPIC_VECPRI_SENSE_EDGE;
833 else
834 vecpri = mpic_type_to_vecpri(mpic, flow_type);
835
836 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
837 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
838 MPIC_INFO(VECPRI_SENSE_MASK));
839 vnew |= vecpri;
840 if (vold != vnew)
841 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
842
843 return 0;
844 }
845
846 void mpic_set_vector(unsigned int virq, unsigned int vector)
847 {
848 struct mpic *mpic = mpic_from_irq(virq);
849 unsigned int src = mpic_irq_to_hw(virq);
850 unsigned int vecpri;
851
852 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
853 mpic, virq, src, vector);
854
855 if (src >= mpic->irq_count)
856 return;
857
858 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
859 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
860 vecpri |= vector;
861 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
862 }
863
864 static struct irq_chip mpic_irq_chip = {
865 .mask = mpic_mask_irq,
866 .unmask = mpic_unmask_irq,
867 .eoi = mpic_end_irq,
868 .set_type = mpic_set_irq_type,
869 };
870
871 #ifdef CONFIG_SMP
872 static struct irq_chip mpic_ipi_chip = {
873 .mask = mpic_mask_ipi,
874 .unmask = mpic_unmask_ipi,
875 .eoi = mpic_end_ipi,
876 };
877 #endif /* CONFIG_SMP */
878
879 #ifdef CONFIG_MPIC_U3_HT_IRQS
880 static struct irq_chip mpic_irq_ht_chip = {
881 .startup = mpic_startup_ht_irq,
882 .shutdown = mpic_shutdown_ht_irq,
883 .mask = mpic_mask_irq,
884 .unmask = mpic_unmask_ht_irq,
885 .eoi = mpic_end_ht_irq,
886 .set_type = mpic_set_irq_type,
887 };
888 #endif /* CONFIG_MPIC_U3_HT_IRQS */
889
890
891 static int mpic_host_match(struct irq_host *h, struct device_node *node)
892 {
893 /* Exact match, unless mpic node is NULL */
894 return h->of_node == NULL || h->of_node == node;
895 }
896
897 static int mpic_host_map(struct irq_host *h, unsigned int virq,
898 irq_hw_number_t hw)
899 {
900 struct mpic *mpic = h->host_data;
901 struct irq_chip *chip;
902
903 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
904
905 if (hw == mpic->spurious_vec)
906 return -EINVAL;
907 if (mpic->protected && test_bit(hw, mpic->protected))
908 return -EINVAL;
909
910 #ifdef CONFIG_SMP
911 else if (hw >= mpic->ipi_vecs[0]) {
912 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
913
914 DBG("mpic: mapping as IPI\n");
915 set_irq_chip_data(virq, mpic);
916 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
917 handle_percpu_irq);
918 return 0;
919 }
920 #endif /* CONFIG_SMP */
921
922 if (hw >= mpic->irq_count)
923 return -EINVAL;
924
925 mpic_msi_reserve_hwirq(mpic, hw);
926
927 /* Default chip */
928 chip = &mpic->hc_irq;
929
930 #ifdef CONFIG_MPIC_U3_HT_IRQS
931 /* Check for HT interrupts, override vecpri */
932 if (mpic_is_ht_interrupt(mpic, hw))
933 chip = &mpic->hc_ht_irq;
934 #endif /* CONFIG_MPIC_U3_HT_IRQS */
935
936 DBG("mpic: mapping to irq chip @%p\n", chip);
937
938 set_irq_chip_data(virq, mpic);
939 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
940
941 /* Set default irq type */
942 set_irq_type(virq, IRQ_TYPE_NONE);
943
944 return 0;
945 }
946
947 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
948 u32 *intspec, unsigned int intsize,
949 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
950
951 {
952 static unsigned char map_mpic_senses[4] = {
953 IRQ_TYPE_EDGE_RISING,
954 IRQ_TYPE_LEVEL_LOW,
955 IRQ_TYPE_LEVEL_HIGH,
956 IRQ_TYPE_EDGE_FALLING,
957 };
958
959 *out_hwirq = intspec[0];
960 if (intsize > 1) {
961 u32 mask = 0x3;
962
963 /* Apple invented a new race of encoding on machines with
964 * an HT APIC. They encode, among others, the index within
965 * the HT APIC. We don't care about it here since thankfully,
966 * it appears that they have the APIC already properly
967 * configured, and thus our current fixup code that reads the
968 * APIC config works fine. However, we still need to mask out
969 * bits in the specifier to make sure we only get bit 0 which
970 * is the level/edge bit (the only sense bit exposed by Apple),
971 * as their bit 1 means something else.
972 */
973 if (machine_is(powermac))
974 mask = 0x1;
975 *out_flags = map_mpic_senses[intspec[1] & mask];
976 } else
977 *out_flags = IRQ_TYPE_NONE;
978
979 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
980 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
981
982 return 0;
983 }
984
985 static struct irq_host_ops mpic_host_ops = {
986 .match = mpic_host_match,
987 .map = mpic_host_map,
988 .xlate = mpic_host_xlate,
989 };
990
991 /*
992 * Exported functions
993 */
994
995 struct mpic * __init mpic_alloc(struct device_node *node,
996 phys_addr_t phys_addr,
997 unsigned int flags,
998 unsigned int isu_size,
999 unsigned int irq_count,
1000 const char *name)
1001 {
1002 struct mpic *mpic;
1003 u32 reg;
1004 const char *vers;
1005 int i;
1006 int intvec_top;
1007 u64 paddr = phys_addr;
1008
1009 mpic = alloc_bootmem(sizeof(struct mpic));
1010 if (mpic == NULL)
1011 return NULL;
1012
1013 memset(mpic, 0, sizeof(struct mpic));
1014 mpic->name = name;
1015
1016 mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
1017 isu_size, &mpic_host_ops,
1018 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1019 if (mpic->irqhost == NULL) {
1020 of_node_put(node);
1021 return NULL;
1022 }
1023
1024 mpic->irqhost->host_data = mpic;
1025 mpic->hc_irq = mpic_irq_chip;
1026 mpic->hc_irq.typename = name;
1027 if (flags & MPIC_PRIMARY)
1028 mpic->hc_irq.set_affinity = mpic_set_affinity;
1029 #ifdef CONFIG_MPIC_U3_HT_IRQS
1030 mpic->hc_ht_irq = mpic_irq_ht_chip;
1031 mpic->hc_ht_irq.typename = name;
1032 if (flags & MPIC_PRIMARY)
1033 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1034 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1035
1036 #ifdef CONFIG_SMP
1037 mpic->hc_ipi = mpic_ipi_chip;
1038 mpic->hc_ipi.typename = name;
1039 #endif /* CONFIG_SMP */
1040
1041 mpic->flags = flags;
1042 mpic->isu_size = isu_size;
1043 mpic->irq_count = irq_count;
1044 mpic->num_sources = 0; /* so far */
1045
1046 if (flags & MPIC_LARGE_VECTORS)
1047 intvec_top = 2047;
1048 else
1049 intvec_top = 255;
1050
1051 mpic->timer_vecs[0] = intvec_top - 8;
1052 mpic->timer_vecs[1] = intvec_top - 7;
1053 mpic->timer_vecs[2] = intvec_top - 6;
1054 mpic->timer_vecs[3] = intvec_top - 5;
1055 mpic->ipi_vecs[0] = intvec_top - 4;
1056 mpic->ipi_vecs[1] = intvec_top - 3;
1057 mpic->ipi_vecs[2] = intvec_top - 2;
1058 mpic->ipi_vecs[3] = intvec_top - 1;
1059 mpic->spurious_vec = intvec_top;
1060
1061 /* Check for "big-endian" in device-tree */
1062 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1063 mpic->flags |= MPIC_BIG_ENDIAN;
1064
1065 /* Look for protected sources */
1066 if (node) {
1067 unsigned int psize, bits, mapsize;
1068 const u32 *psrc =
1069 of_get_property(node, "protected-sources", &psize);
1070 if (psrc) {
1071 psize /= 4;
1072 bits = intvec_top + 1;
1073 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1074 mpic->protected = alloc_bootmem(mapsize);
1075 BUG_ON(mpic->protected == NULL);
1076 memset(mpic->protected, 0, mapsize);
1077 for (i = 0; i < psize; i++) {
1078 if (psrc[i] > intvec_top)
1079 continue;
1080 __set_bit(psrc[i], mpic->protected);
1081 }
1082 }
1083 }
1084
1085 #ifdef CONFIG_MPIC_WEIRD
1086 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1087 #endif
1088
1089 /* default register type */
1090 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1091 mpic_access_mmio_be : mpic_access_mmio_le;
1092
1093 /* If no physical address is passed in, a device-node is mandatory */
1094 BUG_ON(paddr == 0 && node == NULL);
1095
1096 /* If no physical address passed in, check if it's dcr based */
1097 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1098 #ifdef CONFIG_PPC_DCR
1099 mpic->flags |= MPIC_USES_DCR;
1100 mpic->reg_type = mpic_access_dcr;
1101 #else
1102 BUG();
1103 #endif /* CONFIG_PPC_DCR */
1104 }
1105
1106 /* If the MPIC is not DCR based, and no physical address was passed
1107 * in, try to obtain one
1108 */
1109 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1110 const u32 *reg;
1111 reg = of_get_property(node, "reg", NULL);
1112 BUG_ON(reg == NULL);
1113 paddr = of_translate_address(node, reg);
1114 BUG_ON(paddr == OF_BAD_ADDR);
1115 }
1116
1117 /* Map the global registers */
1118 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1119 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1120
1121 /* Reset */
1122 if (flags & MPIC_WANTS_RESET) {
1123 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1124 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1125 | MPIC_GREG_GCONF_RESET);
1126 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1127 & MPIC_GREG_GCONF_RESET)
1128 mb();
1129 }
1130
1131 if (flags & MPIC_ENABLE_MCK)
1132 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1133 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1134 | MPIC_GREG_GCONF_MCK);
1135
1136 /* Read feature register, calculate num CPUs and, for non-ISU
1137 * MPICs, num sources as well. On ISU MPICs, sources are counted
1138 * as ISUs are added
1139 */
1140 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1141 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1142 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1143 if (isu_size == 0)
1144 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1145 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1146
1147 /* Map the per-CPU registers */
1148 for (i = 0; i < mpic->num_cpus; i++) {
1149 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1150 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1151 0x1000);
1152 }
1153
1154 /* Initialize main ISU if none provided */
1155 if (mpic->isu_size == 0) {
1156 mpic->isu_size = mpic->num_sources;
1157 mpic_map(mpic, paddr, &mpic->isus[0],
1158 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1159 }
1160 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1161 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1162
1163 /* Display version */
1164 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1165 case 1:
1166 vers = "1.0";
1167 break;
1168 case 2:
1169 vers = "1.2";
1170 break;
1171 case 3:
1172 vers = "1.3";
1173 break;
1174 default:
1175 vers = "<unknown>";
1176 break;
1177 }
1178 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1179 " max %d CPUs\n",
1180 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1181 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1182 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1183
1184 mpic->next = mpics;
1185 mpics = mpic;
1186
1187 if (flags & MPIC_PRIMARY) {
1188 mpic_primary = mpic;
1189 irq_set_default_host(mpic->irqhost);
1190 }
1191
1192 return mpic;
1193 }
1194
1195 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1196 phys_addr_t paddr)
1197 {
1198 unsigned int isu_first = isu_num * mpic->isu_size;
1199
1200 BUG_ON(isu_num >= MPIC_MAX_ISU);
1201
1202 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1203 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1204 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1205 mpic->num_sources = isu_first + mpic->isu_size;
1206 }
1207
1208 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1209 {
1210 mpic->senses = senses;
1211 mpic->senses_count = count;
1212 }
1213
1214 void __init mpic_init(struct mpic *mpic)
1215 {
1216 int i;
1217
1218 BUG_ON(mpic->num_sources == 0);
1219
1220 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1221
1222 /* Set current processor priority to max */
1223 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1224
1225 /* Initialize timers: just disable them all */
1226 for (i = 0; i < 4; i++) {
1227 mpic_write(mpic->tmregs,
1228 i * MPIC_INFO(TIMER_STRIDE) +
1229 MPIC_INFO(TIMER_DESTINATION), 0);
1230 mpic_write(mpic->tmregs,
1231 i * MPIC_INFO(TIMER_STRIDE) +
1232 MPIC_INFO(TIMER_VECTOR_PRI),
1233 MPIC_VECPRI_MASK |
1234 (mpic->timer_vecs[0] + i));
1235 }
1236
1237 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1238 mpic_test_broken_ipi(mpic);
1239 for (i = 0; i < 4; i++) {
1240 mpic_ipi_write(i,
1241 MPIC_VECPRI_MASK |
1242 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1243 (mpic->ipi_vecs[0] + i));
1244 }
1245
1246 /* Initialize interrupt sources */
1247 if (mpic->irq_count == 0)
1248 mpic->irq_count = mpic->num_sources;
1249
1250 /* Do the HT PIC fixups on U3 broken mpic */
1251 DBG("MPIC flags: %x\n", mpic->flags);
1252 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1253 mpic_scan_ht_pics(mpic);
1254 mpic_u3msi_init(mpic);
1255 }
1256
1257 mpic_pasemi_msi_init(mpic);
1258
1259 for (i = 0; i < mpic->num_sources; i++) {
1260 /* start with vector = source number, and masked */
1261 u32 vecpri = MPIC_VECPRI_MASK | i |
1262 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1263
1264 /* check if protected */
1265 if (mpic->protected && test_bit(i, mpic->protected))
1266 continue;
1267 /* init hw */
1268 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1269 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1270 1 << hard_smp_processor_id());
1271 }
1272
1273 /* Init spurious vector */
1274 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1275
1276 /* Disable 8259 passthrough, if supported */
1277 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1278 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1279 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1280 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1281
1282 if (mpic->flags & MPIC_NO_BIAS)
1283 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1284 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1285 | MPIC_GREG_GCONF_NO_BIAS);
1286
1287 /* Set current processor priority to 0 */
1288 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1289
1290 #ifdef CONFIG_PM
1291 /* allocate memory to save mpic state */
1292 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1293 BUG_ON(mpic->save_data == NULL);
1294 #endif
1295 }
1296
1297 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1298 {
1299 u32 v;
1300
1301 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1302 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1303 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1304 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1305 }
1306
1307 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1308 {
1309 unsigned long flags;
1310 u32 v;
1311
1312 spin_lock_irqsave(&mpic_lock, flags);
1313 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1314 if (enable)
1315 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1316 else
1317 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1318 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1319 spin_unlock_irqrestore(&mpic_lock, flags);
1320 }
1321
1322 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1323 {
1324 int is_ipi;
1325 struct mpic *mpic = mpic_find(irq, &is_ipi);
1326 unsigned int src = mpic_irq_to_hw(irq);
1327 unsigned long flags;
1328 u32 reg;
1329
1330 spin_lock_irqsave(&mpic_lock, flags);
1331 if (is_ipi) {
1332 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1333 ~MPIC_VECPRI_PRIORITY_MASK;
1334 mpic_ipi_write(src - mpic->ipi_vecs[0],
1335 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1336 } else {
1337 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1338 & ~MPIC_VECPRI_PRIORITY_MASK;
1339 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1340 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1341 }
1342 spin_unlock_irqrestore(&mpic_lock, flags);
1343 }
1344
1345 unsigned int mpic_irq_get_priority(unsigned int irq)
1346 {
1347 int is_ipi;
1348 struct mpic *mpic = mpic_find(irq, &is_ipi);
1349 unsigned int src = mpic_irq_to_hw(irq);
1350 unsigned long flags;
1351 u32 reg;
1352
1353 spin_lock_irqsave(&mpic_lock, flags);
1354 if (is_ipi)
1355 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1356 else
1357 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1358 spin_unlock_irqrestore(&mpic_lock, flags);
1359 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1360 }
1361
1362 void mpic_setup_this_cpu(void)
1363 {
1364 #ifdef CONFIG_SMP
1365 struct mpic *mpic = mpic_primary;
1366 unsigned long flags;
1367 u32 msk = 1 << hard_smp_processor_id();
1368 unsigned int i;
1369
1370 BUG_ON(mpic == NULL);
1371
1372 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1373
1374 spin_lock_irqsave(&mpic_lock, flags);
1375
1376 /* let the mpic know we want intrs. default affinity is 0xffffffff
1377 * until changed via /proc. That's how it's done on x86. If we want
1378 * it differently, then we should make sure we also change the default
1379 * values of irq_desc[].affinity in irq.c.
1380 */
1381 if (distribute_irqs) {
1382 for (i = 0; i < mpic->num_sources ; i++)
1383 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1384 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1385 }
1386
1387 /* Set current processor priority to 0 */
1388 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1389
1390 spin_unlock_irqrestore(&mpic_lock, flags);
1391 #endif /* CONFIG_SMP */
1392 }
1393
1394 int mpic_cpu_get_priority(void)
1395 {
1396 struct mpic *mpic = mpic_primary;
1397
1398 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1399 }
1400
1401 void mpic_cpu_set_priority(int prio)
1402 {
1403 struct mpic *mpic = mpic_primary;
1404
1405 prio &= MPIC_CPU_TASKPRI_MASK;
1406 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1407 }
1408
1409 /*
1410 * XXX: someone who knows mpic should check this.
1411 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1412 * or can we reset the mpic in the new kernel?
1413 */
1414 void mpic_teardown_this_cpu(int secondary)
1415 {
1416 struct mpic *mpic = mpic_primary;
1417 unsigned long flags;
1418 u32 msk = 1 << hard_smp_processor_id();
1419 unsigned int i;
1420
1421 BUG_ON(mpic == NULL);
1422
1423 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1424 spin_lock_irqsave(&mpic_lock, flags);
1425
1426 /* let the mpic know we don't want intrs. */
1427 for (i = 0; i < mpic->num_sources ; i++)
1428 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1429 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1430
1431 /* Set current processor priority to max */
1432 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1433
1434 spin_unlock_irqrestore(&mpic_lock, flags);
1435 }
1436
1437
1438 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1439 {
1440 struct mpic *mpic = mpic_primary;
1441
1442 BUG_ON(mpic == NULL);
1443
1444 #ifdef DEBUG_IPI
1445 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1446 #endif
1447
1448 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1449 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1450 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1451 }
1452
1453 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1454 {
1455 u32 src;
1456
1457 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1458 #ifdef DEBUG_LOW
1459 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1460 #endif
1461 if (unlikely(src == mpic->spurious_vec)) {
1462 if (mpic->flags & MPIC_SPV_EOI)
1463 mpic_eoi(mpic);
1464 return NO_IRQ;
1465 }
1466 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1467 if (printk_ratelimit())
1468 printk(KERN_WARNING "%s: Got protected source %d !\n",
1469 mpic->name, (int)src);
1470 mpic_eoi(mpic);
1471 return NO_IRQ;
1472 }
1473
1474 return irq_linear_revmap(mpic->irqhost, src);
1475 }
1476
1477 unsigned int mpic_get_one_irq(struct mpic *mpic)
1478 {
1479 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1480 }
1481
1482 unsigned int mpic_get_irq(void)
1483 {
1484 struct mpic *mpic = mpic_primary;
1485
1486 BUG_ON(mpic == NULL);
1487
1488 return mpic_get_one_irq(mpic);
1489 }
1490
1491 unsigned int mpic_get_mcirq(void)
1492 {
1493 struct mpic *mpic = mpic_primary;
1494
1495 BUG_ON(mpic == NULL);
1496
1497 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1498 }
1499
1500 #ifdef CONFIG_SMP
1501 void mpic_request_ipis(void)
1502 {
1503 struct mpic *mpic = mpic_primary;
1504 long i, err;
1505 static char *ipi_names[] = {
1506 "IPI0 (call function)",
1507 "IPI1 (reschedule)",
1508 "IPI2 (unused)",
1509 "IPI3 (debugger break)",
1510 };
1511 BUG_ON(mpic == NULL);
1512
1513 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1514
1515 for (i = 0; i < 4; i++) {
1516 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1517 mpic->ipi_vecs[0] + i);
1518 if (vipi == NO_IRQ) {
1519 printk(KERN_ERR "Failed to map IPI %ld\n", i);
1520 break;
1521 }
1522 err = request_irq(vipi, mpic_ipi_action,
1523 IRQF_DISABLED|IRQF_PERCPU,
1524 ipi_names[i], (void *)i);
1525 if (err) {
1526 printk(KERN_ERR "Request of irq %d for IPI %ld failed\n",
1527 vipi, i);
1528 break;
1529 }
1530 }
1531 }
1532
1533 void smp_mpic_message_pass(int target, int msg)
1534 {
1535 /* make sure we're sending something that translates to an IPI */
1536 if ((unsigned int)msg > 3) {
1537 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1538 smp_processor_id(), msg);
1539 return;
1540 }
1541 switch (target) {
1542 case MSG_ALL:
1543 mpic_send_ipi(msg, 0xffffffff);
1544 break;
1545 case MSG_ALL_BUT_SELF:
1546 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1547 break;
1548 default:
1549 mpic_send_ipi(msg, 1 << target);
1550 break;
1551 }
1552 }
1553
1554 int __init smp_mpic_probe(void)
1555 {
1556 int nr_cpus;
1557
1558 DBG("smp_mpic_probe()...\n");
1559
1560 nr_cpus = cpus_weight(cpu_possible_map);
1561
1562 DBG("nr_cpus: %d\n", nr_cpus);
1563
1564 if (nr_cpus > 1)
1565 mpic_request_ipis();
1566
1567 return nr_cpus;
1568 }
1569
1570 void __devinit smp_mpic_setup_cpu(int cpu)
1571 {
1572 mpic_setup_this_cpu();
1573 }
1574 #endif /* CONFIG_SMP */
1575
1576 #ifdef CONFIG_PM
1577 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1578 {
1579 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1580 int i;
1581
1582 for (i = 0; i < mpic->num_sources; i++) {
1583 mpic->save_data[i].vecprio =
1584 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1585 mpic->save_data[i].dest =
1586 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1587 }
1588
1589 return 0;
1590 }
1591
1592 static int mpic_resume(struct sys_device *dev)
1593 {
1594 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1595 int i;
1596
1597 for (i = 0; i < mpic->num_sources; i++) {
1598 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1599 mpic->save_data[i].vecprio);
1600 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1601 mpic->save_data[i].dest);
1602
1603 #ifdef CONFIG_MPIC_U3_HT_IRQS
1604 {
1605 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1606
1607 if (fixup->base) {
1608 /* we use the lowest bit in an inverted meaning */
1609 if ((mpic->save_data[i].fixup_data & 1) == 0)
1610 continue;
1611
1612 /* Enable and configure */
1613 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1614
1615 writel(mpic->save_data[i].fixup_data & ~1,
1616 fixup->base + 4);
1617 }
1618 }
1619 #endif
1620 } /* end for loop */
1621
1622 return 0;
1623 }
1624 #endif
1625
1626 static struct sysdev_class mpic_sysclass = {
1627 #ifdef CONFIG_PM
1628 .resume = mpic_resume,
1629 .suspend = mpic_suspend,
1630 #endif
1631 .name = "mpic",
1632 };
1633
1634 static int mpic_init_sys(void)
1635 {
1636 struct mpic *mpic = mpics;
1637 int error, id = 0;
1638
1639 error = sysdev_class_register(&mpic_sysclass);
1640
1641 while (mpic && !error) {
1642 mpic->sysdev.cls = &mpic_sysclass;
1643 mpic->sysdev.id = id++;
1644 error = sysdev_register(&mpic->sysdev);
1645 mpic = mpic->next;
1646 }
1647 return error;
1648 }
1649
1650 device_initcall(mpic_init_sys);
WRT350N Kernel Patches