arch/sh/kernel/cpu/sh3/setup-sh770x.c

   1 /*
   2  * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
   3  *
   4  *  Copyright (C) 2007  Magnus Damm
   5  *
   6  * Based on setup-sh7709.c
   7  *
   8  *  Copyright (C) 2006  Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/serial.h>
  19 #include <asm/sci.h>
  20
  21 enum {
  22         UNUSED = 0,
  23
  24         /* interrupt sources */
  25         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  26         PINT07, PINT815,
  27         DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
  28         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  29         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  30         SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
  31         ADC_ADI,
  32         LCDC, PCC0, PCC1,
  33         TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
  34         RTC_ATI, RTC_PRI, RTC_CUI,
  35         WDT,
  36         REF_RCMI, REF_ROVI,
  37
  38         /* interrupt groups */
  39         RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
  40 };
  41
  42 static struct intc_vect vectors[] __initdata = {
  43         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  44         INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
  45         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
  46         INTC_VECT(RTC_CUI, 0x4c0),
  47         INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
  48         INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
  49         INTC_VECT(WDT, 0x560),
  50         INTC_VECT(REF_RCMI, 0x580),
  51         INTC_VECT(REF_ROVI, 0x5a0),
  52 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  53     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  54     defined(CONFIG_CPU_SUBTYPE_SH7709)
  55         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  56         INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
  57         INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
  58         INTC_VECT(ADC_ADI, 0x980),
  59         INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
  60         INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
  61 #endif
  62 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  63     defined(CONFIG_CPU_SUBTYPE_SH7709)
  64         INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  65         INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  66         INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  67 #endif
  68 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  69         INTC_VECT(LCDC, 0x9a0),
  70         INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  71 #endif
  72 };
  73
  74 static struct intc_group groups[] __initdata = {
  75         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
  76         INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
  77         INTC_GROUP(REF, REF_RCMI, REF_ROVI),
  78         INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
  79         INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
  80         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  81         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  82 };
  83
  84 static struct intc_prio_reg prio_registers[] __initdata = {
  85         { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  86         { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  87 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  88     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  89     defined(CONFIG_CPU_SUBTYPE_SH7709)
  90         { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  91         { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  92         { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  93 #endif
  94 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  95     defined(CONFIG_CPU_SUBTYPE_SH7709)
  96         { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  97         { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  98 #endif
  99 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 100         { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
 101 #endif
 102 };
 103
 104 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
 105                          NULL, prio_registers, NULL);
 106
 107 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 108     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 109     defined(CONFIG_CPU_SUBTYPE_SH7709)
 110 static struct intc_vect vectors_irq[] __initdata = {
 111         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 112         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 113 };
 114
 115 static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
 116                          NULL, prio_registers, NULL);
 117 #endif
 118
 119 static struct resource rtc_resources[] = {
 120         [0] =   {
 121                 .start  = 0xfffffec0,
 122                 .end    = 0xfffffec0 + 0x1e,
 123                 .flags  = IORESOURCE_IO,
 124         },
 125         [1] =   {
 126                 .start  = 20,
 127                 .flags  = IORESOURCE_IRQ,
 128         },
 129         [2] =   {
 130                 .start  = 21,
 131                 .flags  = IORESOURCE_IRQ,
 132         },
 133         [3] =   {
 134                 .start  = 22,
 135                 .flags  = IORESOURCE_IRQ,
 136         },
 137 };
 138
 139 static struct platform_device rtc_device = {
 140         .name           = "sh-rtc",
 141         .id             = -1,
 142         .num_resources  = ARRAY_SIZE(rtc_resources),
 143         .resource       = rtc_resources,
 144 };
 145
 146 static struct plat_sci_port sci_platform_data[] = {
 147         {
 148                 .mapbase        = 0xfffffe80,
 149                 .flags          = UPF_BOOT_AUTOCONF,
 150                 .type           = PORT_SCI,
 151                 .irqs           = { 23, 24, 25, 0 },
 152         },
 153 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 154     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 155     defined(CONFIG_CPU_SUBTYPE_SH7709)
 156         {
 157                 .mapbase        = 0xa4000150,
 158                 .flags          = UPF_BOOT_AUTOCONF,
 159                 .type           = PORT_SCIF,
 160                 .irqs           = { 56, 57, 59, 58 },
 161         },
 162 #endif
 163 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 164     defined(CONFIG_CPU_SUBTYPE_SH7709)
 165         {
 166                 .mapbase        = 0xa4000140,
 167                 .flags          = UPF_BOOT_AUTOCONF,
 168                 .type           = PORT_IRDA,
 169                 .irqs           = { 52, 53, 55, 54 },
 170         },
 171 #endif
 172         {
 173                 .flags = 0,
 174         }
 175 };
 176
 177 static struct platform_device sci_device = {
 178         .name           = "sh-sci",
 179         .id             = -1,
 180         .dev            = {
 181                 .platform_data  = sci_platform_data,
 182         },
 183 };
 184
 185 static struct platform_device *sh770x_devices[] __initdata = {
 186         &sci_device,
 187         &rtc_device,
 188 };
 189
 190 static int __init sh770x_devices_setup(void)
 191 {
 192         return platform_add_devices(sh770x_devices,
 193                 ARRAY_SIZE(sh770x_devices));
 194 }
 195 __initcall(sh770x_devices_setup);
 196
 197 #define INTC_ICR1               0xa4000010UL
 198 #define INTC_ICR1_IRQLVL        (1<<14)
 199
 200 void __init plat_irq_setup_pins(int mode)
 201 {
 202         if (mode == IRQ_MODE_IRQ) {
 203 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 204     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 205     defined(CONFIG_CPU_SUBTYPE_SH7709)
 206                 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
 207                 register_intc_controller(&intc_desc_irq);
 208                 return;
 209 #endif
 210         }
 211         BUG();
 212 }
 213
 214 void __init plat_irq_setup(void)
 215 {
 216         register_intc_controller(&intc_desc);
 217 }