?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Initial commit
[wrt350n-kernel.git] / drivers / media / dvb / frontends / cx24123.c
blobd74fdbd63361f77e621d1cf1e6d7f4c1b8d5f322
1 /*
2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
3
4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
5
6 Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/slab.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/init.h>
27
28 #include "dvb_frontend.h"
29 #include "cx24123.h"
30
31 #define XTAL 10111000
32
33 static int force_band;
34 static int debug;
35 #define dprintk(args...) \
36 do { \
37 if (debug) printk (KERN_DEBUG "cx24123: " args); \
38 } while (0)
39
40 struct cx24123_state
41 {
42 struct i2c_adapter* i2c;
43 const struct cx24123_config* config;
44
45 struct dvb_frontend frontend;
46
47 /* Some PLL specifics for tuning */
48 u32 VCAarg;
49 u32 VGAarg;
50 u32 bandselectarg;
51 u32 pllarg;
52 u32 FILTune;
53
54 /* The Demod/Tuner can't easily provide these, we cache them */
55 u32 currentfreq;
56 u32 currentsymbolrate;
57 };
58
59 /* Various tuner defaults need to be established for a given symbol rate Sps */
60 static struct
61 {
62 u32 symbolrate_low;
63 u32 symbolrate_high;
64 u32 VCAprogdata;
65 u32 VGAprogdata;
66 u32 FILTune;
67 } cx24123_AGC_vals[] =
68 {
69 {
70 .symbolrate_low = 1000000,
71 .symbolrate_high = 4999999,
72 /* the specs recommend other values for VGA offsets,
73 but tests show they are wrong */
74 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
75 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
76 .FILTune = 0x27f /* 0.41 V */
77 },
78 {
79 .symbolrate_low = 5000000,
80 .symbolrate_high = 14999999,
81 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
82 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
83 .FILTune = 0x317 /* 0.90 V */
84 },
85 {
86 .symbolrate_low = 15000000,
87 .symbolrate_high = 45000000,
88 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
89 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
90 .FILTune = 0x145 /* 2.70 V */
91 },
92 };
93
94 /*
95 * Various tuner defaults need to be established for a given frequency kHz.
96 * fixme: The bounds on the bands do not match the doc in real life.
97 * fixme: Some of them have been moved, other might need adjustment.
98 */
99 static struct
100 {
101 u32 freq_low;
102 u32 freq_high;
103 u32 VCOdivider;
104 u32 progdata;
105 } cx24123_bandselect_vals[] =
106 {
107 /* band 1 */
108 {
109 .freq_low = 950000,
110 .freq_high = 1074999,
111 .VCOdivider = 4,
112 .progdata = (0 << 19) | (0 << 9) | 0x40,
113 },
114
115 /* band 2 */
116 {
117 .freq_low = 1075000,
118 .freq_high = 1177999,
119 .VCOdivider = 4,
120 .progdata = (0 << 19) | (0 << 9) | 0x80,
121 },
122
123 /* band 3 */
124 {
125 .freq_low = 1178000,
126 .freq_high = 1295999,
127 .VCOdivider = 2,
128 .progdata = (0 << 19) | (1 << 9) | 0x01,
129 },
130
131 /* band 4 */
132 {
133 .freq_low = 1296000,
134 .freq_high = 1431999,
135 .VCOdivider = 2,
136 .progdata = (0 << 19) | (1 << 9) | 0x02,
137 },
138
139 /* band 5 */
140 {
141 .freq_low = 1432000,
142 .freq_high = 1575999,
143 .VCOdivider = 2,
144 .progdata = (0 << 19) | (1 << 9) | 0x04,
145 },
146
147 /* band 6 */
148 {
149 .freq_low = 1576000,
150 .freq_high = 1717999,
151 .VCOdivider = 2,
152 .progdata = (0 << 19) | (1 << 9) | 0x08,
153 },
154
155 /* band 7 */
156 {
157 .freq_low = 1718000,
158 .freq_high = 1855999,
159 .VCOdivider = 2,
160 .progdata = (0 << 19) | (1 << 9) | 0x10,
161 },
162
163 /* band 8 */
164 {
165 .freq_low = 1856000,
166 .freq_high = 2035999,
167 .VCOdivider = 2,
168 .progdata = (0 << 19) | (1 << 9) | 0x20,
169 },
170
171 /* band 9 */
172 {
173 .freq_low = 2036000,
174 .freq_high = 2150000,
175 .VCOdivider = 2,
176 .progdata = (0 << 19) | (1 << 9) | 0x40,
177 },
178 };
179
180 static struct {
181 u8 reg;
182 u8 data;
183 } cx24123_regdata[] =
184 {
185 {0x00, 0x03}, /* Reset system */
186 {0x00, 0x00}, /* Clear reset */
187 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
188 {0x04, 0x10}, /* MPEG */
189 {0x05, 0x04}, /* MPEG */
190 {0x06, 0x31}, /* MPEG (default) */
191 {0x0b, 0x00}, /* Freq search start point (default) */
192 {0x0c, 0x00}, /* Demodulator sample gain (default) */
193 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
194 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
195 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
196 {0x10, 0x01}, /* Default search inversion, no repeat (default) */
197 {0x16, 0x00}, /* Enable reading of frequency */
198 {0x17, 0x01}, /* Enable EsNO Ready Counter */
199 {0x1c, 0x80}, /* Enable error counter */
200 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
201 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
202 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
203 {0x29, 0x00}, /* DiSEqC LNB_DC off */
204 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
205 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
206 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
207 {0x2d, 0x00},
208 {0x2e, 0x00},
209 {0x2f, 0x00},
210 {0x30, 0x00},
211 {0x31, 0x00},
212 {0x32, 0x8c}, /* DiSEqC Parameters (default) */
213 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
214 {0x34, 0x00},
215 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
216 {0x36, 0x02}, /* DiSEqC Parameters (default) */
217 {0x37, 0x3a}, /* DiSEqC Parameters (default) */
218 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
219 {0x44, 0x00}, /* Constellation (default) */
220 {0x45, 0x00}, /* Symbol count (default) */
221 {0x46, 0x0d}, /* Symbol rate estimator on (default) */
222 {0x56, 0xc1}, /* Error Counter = Viterbi BER */
223 {0x57, 0xff}, /* Error Counter Window (default) */
224 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
225 {0x67, 0x83}, /* Non-DCII symbol clock */
226 };
227
228 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
229 {
230 u8 buf[] = { reg, data };
231 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
232 int err;
233
234 if (debug>1)
235 printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n",
236 __FUNCTION__,reg, data);
237
238 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
239 printk("%s: writereg error(err == %i, reg == 0x%02x,"
240 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
241 return -EREMOTEIO;
242 }
243
244 return 0;
245 }
246
247 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
248 {
249 int ret;
250 u8 b0[] = { reg };
251 u8 b1[] = { 0 };
252 struct i2c_msg msg[] = {
253 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
254 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
255 };
256
257 ret = i2c_transfer(state->i2c, msg, 2);
258
259 if (ret != 2) {
260 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
261 return ret;
262 }
263
264 if (debug>1)
265 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);
266
267 return b1[0];
268 }
269
270 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
271 {
272 u8 nom_reg = cx24123_readreg(state, 0x0e);
273 u8 auto_reg = cx24123_readreg(state, 0x10);
274
275 switch (inversion) {
276 case INVERSION_OFF:
277 dprintk("%s: inversion off\n",__FUNCTION__);
278 cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
279 cx24123_writereg(state, 0x10, auto_reg | 0x80);
280 break;
281 case INVERSION_ON:
282 dprintk("%s: inversion on\n",__FUNCTION__);
283 cx24123_writereg(state, 0x0e, nom_reg | 0x80);
284 cx24123_writereg(state, 0x10, auto_reg | 0x80);
285 break;
286 case INVERSION_AUTO:
287 dprintk("%s: inversion auto\n",__FUNCTION__);
288 cx24123_writereg(state, 0x10, auto_reg & ~0x80);
289 break;
290 default:
291 return -EINVAL;
292 }
293
294 return 0;
295 }
296
297 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
298 {
299 u8 val;
300
301 val = cx24123_readreg(state, 0x1b) >> 7;
302
303 if (val == 0) {
304 dprintk("%s: read inversion off\n",__FUNCTION__);
305 *inversion = INVERSION_OFF;
306 } else {
307 dprintk("%s: read inversion on\n",__FUNCTION__);
308 *inversion = INVERSION_ON;
309 }
310
311 return 0;
312 }
313
314 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
315 {
316 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
317
318 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
319 fec = FEC_AUTO;
320
321 /* Set the soft decision threshold */
322 if(fec == FEC_1_2)
323 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) | 0x01);
324 else
325 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) & ~0x01);
326
327 switch (fec) {
328 case FEC_1_2:
329 dprintk("%s: set FEC to 1/2\n",__FUNCTION__);
330 cx24123_writereg(state, 0x0e, nom_reg | 0x01);
331 cx24123_writereg(state, 0x0f, 0x02);
332 break;
333 case FEC_2_3:
334 dprintk("%s: set FEC to 2/3\n",__FUNCTION__);
335 cx24123_writereg(state, 0x0e, nom_reg | 0x02);
336 cx24123_writereg(state, 0x0f, 0x04);
337 break;
338 case FEC_3_4:
339 dprintk("%s: set FEC to 3/4\n",__FUNCTION__);
340 cx24123_writereg(state, 0x0e, nom_reg | 0x03);
341 cx24123_writereg(state, 0x0f, 0x08);
342 break;
343 case FEC_4_5:
344 dprintk("%s: set FEC to 4/5\n",__FUNCTION__);
345 cx24123_writereg(state, 0x0e, nom_reg | 0x04);
346 cx24123_writereg(state, 0x0f, 0x10);
347 break;
348 case FEC_5_6:
349 dprintk("%s: set FEC to 5/6\n",__FUNCTION__);
350 cx24123_writereg(state, 0x0e, nom_reg | 0x05);
351 cx24123_writereg(state, 0x0f, 0x20);
352 break;
353 case FEC_6_7:
354 dprintk("%s: set FEC to 6/7\n",__FUNCTION__);
355 cx24123_writereg(state, 0x0e, nom_reg | 0x06);
356 cx24123_writereg(state, 0x0f, 0x40);
357 break;
358 case FEC_7_8:
359 dprintk("%s: set FEC to 7/8\n",__FUNCTION__);
360 cx24123_writereg(state, 0x0e, nom_reg | 0x07);
361 cx24123_writereg(state, 0x0f, 0x80);
362 break;
363 case FEC_AUTO:
364 dprintk("%s: set FEC to auto\n",__FUNCTION__);
365 cx24123_writereg(state, 0x0f, 0xfe);
366 break;
367 default:
368 return -EOPNOTSUPP;
369 }
370
371 return 0;
372 }
373
374 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
375 {
376 int ret;
377
378 ret = cx24123_readreg (state, 0x1b);
379 if (ret < 0)
380 return ret;
381 ret = ret & 0x07;
382
383 switch (ret) {
384 case 1:
385 *fec = FEC_1_2;
386 break;
387 case 2:
388 *fec = FEC_2_3;
389 break;
390 case 3:
391 *fec = FEC_3_4;
392 break;
393 case 4:
394 *fec = FEC_4_5;
395 break;
396 case 5:
397 *fec = FEC_5_6;
398 break;
399 case 6:
400 *fec = FEC_6_7;
401 break;
402 case 7:
403 *fec = FEC_7_8;
404 break;
405 default:
406 /* this can happen when there's no lock */
407 *fec = FEC_NONE;
408 }
409
410 return 0;
411 }
412
413 /* Approximation of closest integer of log2(a/b). It actually gives the
414 lowest integer i such that 2^i >= round(a/b) */
415 static u32 cx24123_int_log2(u32 a, u32 b)
416 {
417 u32 exp, nearest = 0;
418 u32 div = a / b;
419 if(a % b >= b / 2) ++div;
420 if(div < (1 << 31))
421 {
422 for(exp = 1; div > exp; nearest++)
423 exp += exp;
424 }
425 return nearest;
426 }
427
428 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
429 {
430 u32 tmp, sample_rate, ratio, sample_gain;
431 u8 pll_mult;
432
433 /* check if symbol rate is within limits */
434 if ((srate > state->frontend.ops.info.symbol_rate_max) ||
435 (srate < state->frontend.ops.info.symbol_rate_min))
436 return -EOPNOTSUPP;;
437
438 /* choose the sampling rate high enough for the required operation,
439 while optimizing the power consumed by the demodulator */
440 if (srate < (XTAL*2)/2)
441 pll_mult = 2;
442 else if (srate < (XTAL*3)/2)
443 pll_mult = 3;
444 else if (srate < (XTAL*4)/2)
445 pll_mult = 4;
446 else if (srate < (XTAL*5)/2)
447 pll_mult = 5;
448 else if (srate < (XTAL*6)/2)
449 pll_mult = 6;
450 else if (srate < (XTAL*7)/2)
451 pll_mult = 7;
452 else if (srate < (XTAL*8)/2)
453 pll_mult = 8;
454 else
455 pll_mult = 9;
456
457
458 sample_rate = pll_mult * XTAL;
459
460 /*
461 SYSSymbolRate[21:0] = (srate << 23) / sample_rate
462
463 We have to use 32 bit unsigned arithmetic without precision loss.
464 The maximum srate is 45000000 or 0x02AEA540. This number has
465 only 6 clear bits on top, hence we can shift it left only 6 bits
466 at a time. Borrowed from cx24110.c
467 */
468
469 tmp = srate << 6;
470 ratio = tmp / sample_rate;
471
472 tmp = (tmp % sample_rate) << 6;
473 ratio = (ratio << 6) + (tmp / sample_rate);
474
475 tmp = (tmp % sample_rate) << 6;
476 ratio = (ratio << 6) + (tmp / sample_rate);
477
478 tmp = (tmp % sample_rate) << 5;
479 ratio = (ratio << 5) + (tmp / sample_rate);
480
481
482 cx24123_writereg(state, 0x01, pll_mult * 6);
483
484 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
485 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff );
486 cx24123_writereg(state, 0x0a, (ratio ) & 0xff );
487
488 /* also set the demodulator sample gain */
489 sample_gain = cx24123_int_log2(sample_rate, srate);
490 tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
491 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
492
493 dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);
494
495 return 0;
496 }
497
498 /*
499 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
500 * and the correct band selected. Calculate those values
501 */
502 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
503 {
504 struct cx24123_state *state = fe->demodulator_priv;
505 u32 ndiv = 0, adiv = 0, vco_div = 0;
506 int i = 0;
507 int pump = 2;
508 int band = 0;
509 int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
510
511 /* Defaults for low freq, low rate */
512 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
513 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
514 state->bandselectarg = cx24123_bandselect_vals[0].progdata;
515 vco_div = cx24123_bandselect_vals[0].VCOdivider;
516
517 /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
518 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++)
519 {
520 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
521 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
522 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
523 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
524 state->FILTune = cx24123_AGC_vals[i].FILTune;
525 }
526 }
527
528 /* determine the band to use */
529 if(force_band < 1 || force_band > num_bands)
530 {
531 for (i = 0; i < num_bands; i++)
532 {
533 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
534 (cx24123_bandselect_vals[i].freq_high >= p->frequency) )
535 band = i;
536 }
537 }
538 else
539 band = force_band - 1;
540
541 state->bandselectarg = cx24123_bandselect_vals[band].progdata;
542 vco_div = cx24123_bandselect_vals[band].VCOdivider;
543
544 /* determine the charge pump current */
545 if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 )
546 pump = 0x01;
547 else
548 pump = 0x02;
549
550 /* Determine the N/A dividers for the requested lband freq (in kHz). */
551 /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
552 ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
553 adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
554
555 if (adiv == 0 && ndiv > 0)
556 ndiv--;
557
558 /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
559 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
560
561 return 0;
562 }
563
564 /*
565 * Tuner data is 21 bits long, must be left-aligned in data.
566 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
567 */
568 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
569 {
570 struct cx24123_state *state = fe->demodulator_priv;
571 unsigned long timeout;
572
573 dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data);
574
575 /* align the 21 bytes into to bit23 boundary */
576 data = data << 3;
577
578 /* Reset the demod pll word length to 0x15 bits */
579 cx24123_writereg(state, 0x21, 0x15);
580
581 /* write the msb 8 bits, wait for the send to be completed */
582 timeout = jiffies + msecs_to_jiffies(40);
583 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
584 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
585 if (time_after(jiffies, timeout)) {
586 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
587 return -EREMOTEIO;
588 }
589 msleep(10);
590 }
591
592 /* send another 8 bytes, wait for the send to be completed */
593 timeout = jiffies + msecs_to_jiffies(40);
594 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
595 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
596 if (time_after(jiffies, timeout)) {
597 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
598 return -EREMOTEIO;
599 }
600 msleep(10);
601 }
602
603 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
604 timeout = jiffies + msecs_to_jiffies(40);
605 cx24123_writereg(state, 0x22, (data) & 0xff );
606 while ((cx24123_readreg(state, 0x20) & 0x80)) {
607 if (time_after(jiffies, timeout)) {
608 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
609 return -EREMOTEIO;
610 }
611 msleep(10);
612 }
613
614 /* Trigger the demod to configure the tuner */
615 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
616 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
617
618 return 0;
619 }
620
621 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
622 {
623 struct cx24123_state *state = fe->demodulator_priv;
624 u8 val;
625
626 dprintk("frequency=%i\n", p->frequency);
627
628 if (cx24123_pll_calculate(fe, p) != 0) {
629 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
630 return -EINVAL;
631 }
632
633 /* Write the new VCO/VGA */
634 cx24123_pll_writereg(fe, p, state->VCAarg);
635 cx24123_pll_writereg(fe, p, state->VGAarg);
636
637 /* Write the new bandselect and pll args */
638 cx24123_pll_writereg(fe, p, state->bandselectarg);
639 cx24123_pll_writereg(fe, p, state->pllarg);
640
641 /* set the FILTUNE voltage */
642 val = cx24123_readreg(state, 0x28) & ~0x3;
643 cx24123_writereg(state, 0x27, state->FILTune >> 2);
644 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
645
646 dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
647 state->bandselectarg,state->pllarg);
648
649 return 0;
650 }
651
652 static int cx24123_initfe(struct dvb_frontend* fe)
653 {
654 struct cx24123_state *state = fe->demodulator_priv;
655 int i;
656
657 dprintk("%s: init frontend\n",__FUNCTION__);
658
659 /* Configure the demod to a good set of defaults */
660 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
661 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
662
663 /* Set the LNB polarity */
664 if(state->config->lnb_polarity)
665 cx24123_writereg(state, 0x32, cx24123_readreg(state, 0x32) | 0x02);
666
667 return 0;
668 }
669
670 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
671 {
672 struct cx24123_state *state = fe->demodulator_priv;
673 u8 val;
674
675 val = cx24123_readreg(state, 0x29) & ~0x40;
676
677 switch (voltage) {
678 case SEC_VOLTAGE_13:
679 dprintk("%s: setting voltage 13V\n", __FUNCTION__);
680 return cx24123_writereg(state, 0x29, val & 0x7f);
681 case SEC_VOLTAGE_18:
682 dprintk("%s: setting voltage 18V\n", __FUNCTION__);
683 return cx24123_writereg(state, 0x29, val | 0x80);
684 case SEC_VOLTAGE_OFF:
685 /* already handled in cx88-dvb */
686 return 0;
687 default:
688 return -EINVAL;
689 };
690
691 return 0;
692 }
693
694 /* wait for diseqc queue to become ready (or timeout) */
695 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
696 {
697 unsigned long timeout = jiffies + msecs_to_jiffies(200);
698 while (!(cx24123_readreg(state, 0x29) & 0x40)) {
699 if(time_after(jiffies, timeout)) {
700 printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
701 break;
702 }
703 msleep(10);
704 }
705 }
706
707 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
708 {
709 struct cx24123_state *state = fe->demodulator_priv;
710 int i, val, tone;
711
712 dprintk("%s:\n",__FUNCTION__);
713
714 /* stop continuous tone if enabled */
715 tone = cx24123_readreg(state, 0x29);
716 if (tone & 0x10)
717 cx24123_writereg(state, 0x29, tone & ~0x50);
718
719 /* wait for diseqc queue ready */
720 cx24123_wait_for_diseqc(state);
721
722 /* select tone mode */
723 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
724
725 for (i = 0; i < cmd->msg_len; i++)
726 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
727
728 val = cx24123_readreg(state, 0x29);
729 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
730
731 /* wait for diseqc message to finish sending */
732 cx24123_wait_for_diseqc(state);
733
734 /* restart continuous tone if enabled */
735 if (tone & 0x10) {
736 cx24123_writereg(state, 0x29, tone & ~0x40);
737 }
738
739 return 0;
740 }
741
742 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
743 {
744 struct cx24123_state *state = fe->demodulator_priv;
745 int val, tone;
746
747 dprintk("%s:\n", __FUNCTION__);
748
749 /* stop continuous tone if enabled */
750 tone = cx24123_readreg(state, 0x29);
751 if (tone & 0x10)
752 cx24123_writereg(state, 0x29, tone & ~0x50);
753
754 /* wait for diseqc queue ready */
755 cx24123_wait_for_diseqc(state);
756
757 /* select tone mode */
758 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
759 msleep(30);
760 val = cx24123_readreg(state, 0x29);
761 if (burst == SEC_MINI_A)
762 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
763 else if (burst == SEC_MINI_B)
764 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
765 else
766 return -EINVAL;
767
768 cx24123_wait_for_diseqc(state);
769 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
770
771 /* restart continuous tone if enabled */
772 if (tone & 0x10) {
773 cx24123_writereg(state, 0x29, tone & ~0x40);
774 }
775 return 0;
776 }
777
778 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
779 {
780 struct cx24123_state *state = fe->demodulator_priv;
781
782 int sync = cx24123_readreg(state, 0x14);
783 int lock = cx24123_readreg(state, 0x20);
784
785 *status = 0;
786 if (lock & 0x01)
787 *status |= FE_HAS_SIGNAL;
788 if (sync & 0x02)
789 *status |= FE_HAS_CARRIER; /* Phase locked */
790 if (sync & 0x04)
791 *status |= FE_HAS_VITERBI;
792
793 /* Reed-Solomon Status */
794 if (sync & 0x08)
795 *status |= FE_HAS_SYNC;
796 if (sync & 0x80)
797 *status |= FE_HAS_LOCK; /*Full Sync */
798
799 return 0;
800 }
801
802 /*
803 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
804 * is available, so this value doubles up to satisfy both measurements
805 */
806 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
807 {
808 struct cx24123_state *state = fe->demodulator_priv;
809
810 /* The true bit error rate is this value divided by
811 the window size (set as 256 * 255) */
812 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
813 (cx24123_readreg(state, 0x1d) << 8 |
814 cx24123_readreg(state, 0x1e));
815
816 dprintk("%s: BER = %d\n",__FUNCTION__,*ber);
817
818 return 0;
819 }
820
821 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
822 {
823 struct cx24123_state *state = fe->demodulator_priv;
824
825 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
826
827 dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength);
828
829 return 0;
830 }
831
832 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
833 {
834 struct cx24123_state *state = fe->demodulator_priv;
835
836 /* Inverted raw Es/N0 count, totally bogus but better than the
837 BER threshold. */
838 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
839 (u16)cx24123_readreg(state, 0x19));
840
841 dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr);
842
843 return 0;
844 }
845
846 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
847 {
848 struct cx24123_state *state = fe->demodulator_priv;
849
850 dprintk("%s: set_frontend\n",__FUNCTION__);
851
852 if (state->config->set_ts_params)
853 state->config->set_ts_params(fe, 0);
854
855 state->currentfreq=p->frequency;
856 state->currentsymbolrate = p->u.qpsk.symbol_rate;
857
858 cx24123_set_inversion(state, p->inversion);
859 cx24123_set_fec(state, p->u.qpsk.fec_inner);
860 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
861 cx24123_pll_tune(fe, p);
862
863 /* Enable automatic aquisition and reset cycle */
864 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
865 cx24123_writereg(state, 0x00, 0x10);
866 cx24123_writereg(state, 0x00, 0);
867
868 return 0;
869 }
870
871 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
872 {
873 struct cx24123_state *state = fe->demodulator_priv;
874
875 dprintk("%s: get_frontend\n",__FUNCTION__);
876
877 if (cx24123_get_inversion(state, &p->inversion) != 0) {
878 printk("%s: Failed to get inversion status\n",__FUNCTION__);
879 return -EREMOTEIO;
880 }
881 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
882 printk("%s: Failed to get fec status\n",__FUNCTION__);
883 return -EREMOTEIO;
884 }
885 p->frequency = state->currentfreq;
886 p->u.qpsk.symbol_rate = state->currentsymbolrate;
887
888 return 0;
889 }
890
891 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
892 {
893 struct cx24123_state *state = fe->demodulator_priv;
894 u8 val;
895
896 /* wait for diseqc queue ready */
897 cx24123_wait_for_diseqc(state);
898
899 val = cx24123_readreg(state, 0x29) & ~0x40;
900
901 switch (tone) {
902 case SEC_TONE_ON:
903 dprintk("%s: setting tone on\n", __FUNCTION__);
904 return cx24123_writereg(state, 0x29, val | 0x10);
905 case SEC_TONE_OFF:
906 dprintk("%s: setting tone off\n",__FUNCTION__);
907 return cx24123_writereg(state, 0x29, val & 0xef);
908 default:
909 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
910 return -EINVAL;
911 }
912
913 return 0;
914 }
915
916 static int cx24123_tune(struct dvb_frontend* fe,
917 struct dvb_frontend_parameters* params,
918 unsigned int mode_flags,
919 unsigned int *delay,
920 fe_status_t *status)
921 {
922 int retval = 0;
923
924 if (params != NULL)
925 retval = cx24123_set_frontend(fe, params);
926
927 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
928 cx24123_read_status(fe, status);
929 *delay = HZ/10;
930
931 return retval;
932 }
933
934 static int cx24123_get_algo(struct dvb_frontend *fe)
935 {
936 return 1; //FE_ALGO_HW
937 }
938
939 static void cx24123_release(struct dvb_frontend* fe)
940 {
941 struct cx24123_state* state = fe->demodulator_priv;
942 dprintk("%s\n",__FUNCTION__);
943 kfree(state);
944 }
945
946 static struct dvb_frontend_ops cx24123_ops;
947
948 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
949 struct i2c_adapter* i2c)
950 {
951 struct cx24123_state* state = NULL;
952 int ret;
953
954 dprintk("%s\n",__FUNCTION__);
955
956 /* allocate memory for the internal state */
957 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
958 if (state == NULL) {
959 printk("Unable to kmalloc\n");
960 goto error;
961 }
962
963 /* setup the state */
964 state->config = config;
965 state->i2c = i2c;
966 state->VCAarg = 0;
967 state->VGAarg = 0;
968 state->bandselectarg = 0;
969 state->pllarg = 0;
970 state->currentfreq = 0;
971 state->currentsymbolrate = 0;
972
973 /* check if the demod is there */
974 ret = cx24123_readreg(state, 0x00);
975 if ((ret != 0xd1) && (ret != 0xe1)) {
976 printk("Version != d1 or e1\n");
977 goto error;
978 }
979
980 /* create dvb_frontend */
981 memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
982 state->frontend.demodulator_priv = state;
983 return &state->frontend;
984
985 error:
986 kfree(state);
987
988 return NULL;
989 }
990
991 static struct dvb_frontend_ops cx24123_ops = {
992
993 .info = {
994 .name = "Conexant CX24123/CX24109",
995 .type = FE_QPSK,
996 .frequency_min = 950000,
997 .frequency_max = 2150000,
998 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
999 .frequency_tolerance = 5000,
1000 .symbol_rate_min = 1000000,
1001 .symbol_rate_max = 45000000,
1002 .caps = FE_CAN_INVERSION_AUTO |
1003 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1004 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1005 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1006 FE_CAN_QPSK | FE_CAN_RECOVER
1007 },
1008
1009 .release = cx24123_release,
1010
1011 .init = cx24123_initfe,
1012 .set_frontend = cx24123_set_frontend,
1013 .get_frontend = cx24123_get_frontend,
1014 .read_status = cx24123_read_status,
1015 .read_ber = cx24123_read_ber,
1016 .read_signal_strength = cx24123_read_signal_strength,
1017 .read_snr = cx24123_read_snr,
1018 .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1019 .diseqc_send_burst = cx24123_diseqc_send_burst,
1020 .set_tone = cx24123_set_tone,
1021 .set_voltage = cx24123_set_voltage,
1022 .tune = cx24123_tune,
1023 .get_frontend_algo = cx24123_get_algo,
1024 };
1025
1026 module_param(debug, int, 0644);
1027 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1028
1029 module_param(force_band, int, 0644);
1030 MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off).");
1031
1032 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
1033 MODULE_AUTHOR("Steven Toth");
1034 MODULE_LICENSE("GPL");
1035
1036 EXPORT_SYMBOL(cx24123_attach);
WRT350N Kernel Patches