Initial commit
[wrt350n-kernel.git] / drivers / media / video / planb.h
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1 /*
2 planb - PlanB frame grabber driver
4 PlanB is used in the 7x00/8x00 series of PowerMacintosh
5 Computers as video input DMA controller.
7 Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
9 Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)
11 Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; if not, write to the Free Software
26 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 /* $Id: planb.h,v 1.13 1999/05/03 19:28:56 mlan Exp $ */
31 #ifndef _PLANB_H_
32 #define _PLANB_H_
34 #ifdef __KERNEL__
35 #include <asm/dbdma.h>
36 #include "saa7196.h"
37 #endif /* __KERNEL__ */
39 #define PLANB_DEVICE_NAME "Apple PlanB Video-In"
40 #define PLANB_REV "1.0"
42 #ifdef __KERNEL__
43 //#define PLANB_GSCANLINE /* use this if apps have the notion of */
44 /* grab buffer scanline */
45 /* This should be safe for both PAL and NTSC */
46 #define PLANB_MAXPIXELS 768
47 #define PLANB_MAXLINES 576
48 #define PLANB_NTSC_MAXLINES 480
50 /* Uncomment your preferred norm ;-) */
51 #define PLANB_DEF_NORM VIDEO_MODE_PAL
52 //#define PLANB_DEF_NORM VIDEO_MODE_NTSC
53 //#define PLANB_DEF_NORM VIDEO_MODE_SECAM
55 /* fields settings */
56 #define PLANB_GRAY 0x1 /* 8-bit mono? */
57 #define PLANB_COLOUR15 0x2 /* 16-bit mode */
58 #define PLANB_COLOUR32 0x4 /* 32-bit mode */
59 #define PLANB_CLIPMASK 0x8 /* hardware clipmasking */
61 /* misc. flags for PlanB DMA operation */
62 #define CH_SYNC 0x1 /* synchronize channels (set by ch1;
63 cleared by ch2) */
64 #define FIELD_SYNC 0x2 /* used for the start of each field
65 (0 -> 1 -> 0 for ch1; 0 -> 1 for ch2) */
66 #define EVEN_FIELD 0x0 /* even field is detected if unset */
67 #define DMA_ABORT 0x2 /* error or just out of sync if set */
68 #define ODD_FIELD 0x4 /* odd field is detected if set */
70 /* for capture operations */
71 #define MAX_GBUFFERS 2
72 /* note PLANB_MAX_FBUF must be divisible by PAGE_SIZE */
73 #ifdef PLANB_GSCANLINE
74 #define PLANB_MAX_FBUF 0x240000 /* 576 * 1024 * 4 */
75 #define TAB_FACTOR (1)
76 #else
77 #define PLANB_MAX_FBUF 0x1b0000 /* 576 * 768 * 4 */
78 #define TAB_FACTOR (2)
79 #endif
80 #endif /* __KERNEL__ */
82 struct planb_saa_regs {
83 unsigned char addr;
84 unsigned char val;
87 struct planb_stat_regs {
88 unsigned int ch1_stat;
89 unsigned int ch2_stat;
90 unsigned char saa_stat0;
91 unsigned char saa_stat1;
94 struct planb_any_regs {
95 unsigned int offset;
96 unsigned int bytes;
97 unsigned char data[128];
100 /* planb private ioctls */
101 #define PLANBIOCGSAAREGS _IOWR('v', BASE_VIDIOCPRIVATE, struct planb_saa_regs) /* Read a saa7196 reg value */
102 #define PLANBIOCSSAAREGS _IOW('v', BASE_VIDIOCPRIVATE + 1, struct planb_saa_regs) /* Set a saa7196 reg value */
103 #define PLANBIOCGSTAT _IOR('v', BASE_VIDIOCPRIVATE + 2, struct planb_stat_regs) /* Read planb status */
104 #define PLANB_TV_MODE 1
105 #define PLANB_VTR_MODE 2
106 #define PLANBIOCGMODE _IOR('v', BASE_VIDIOCPRIVATE + 3, int) /* Get TV/VTR mode */
107 #define PLANBIOCSMODE _IOW('v', BASE_VIDIOCPRIVATE + 4, int) /* Set TV/VTR mode */
109 #ifdef PLANB_GSCANLINE
110 #define PLANBG_GRAB_BPL _IOR('v', BASE_VIDIOCPRIVATE + 5, int) /* # of bytes per scanline in grab buffer */
111 #endif
113 /* call wake_up_interruptible() with appropriate actions */
114 #define PLANB_INTR_DEBUG _IOW('v', BASE_VIDIOCPRIVATE + 20, int)
115 /* investigate which reg does what */
116 #define PLANB_INV_REGS _IOWR('v', BASE_VIDIOCPRIVATE + 21, struct planb_any_regs)
118 #ifdef __KERNEL__
120 /* Potentially useful macros */
121 #define PLANB_SET(x) ((x) << 16 | (x))
122 #define PLANB_CLR(x) ((x) << 16)
124 /* This represents the physical register layout */
125 struct planb_registers {
126 volatile struct dbdma_regs ch1; /* 0x00: video in */
127 volatile unsigned int even; /* 0x40: even field setting */
128 volatile unsigned int odd; /* 0x44; odd field setting */
129 unsigned int pad1[14]; /* empty? */
130 volatile struct dbdma_regs ch2; /* 0x80: clipmask out */
131 unsigned int pad2[16]; /* 0xc0: empty? */
132 volatile unsigned int reg3; /* 0x100: ???? */
133 volatile unsigned int intr_stat; /* 0x104: irq status */
134 #define PLANB_CLR_IRQ 0x00 /* clear Plan B interrupt */
135 #define PLANB_GEN_IRQ 0x01 /* assert Plan B interrupt */
136 #define PLANB_FRM_IRQ 0x0100 /* end of frame */
137 unsigned int pad3[1]; /* empty? */
138 volatile unsigned int reg5; /* 0x10c: ??? */
139 unsigned int pad4[60]; /* empty? */
140 volatile unsigned char saa_addr; /* 0x200: SAA subadr */
141 char pad5[3];
142 volatile unsigned char saa_regval; /* SAA7196 write reg. val */
143 char pad6[3];
144 volatile unsigned char saa_status; /* SAA7196 status byte */
145 /* There is more unused stuff here */
148 struct planb_window {
149 int x, y;
150 ushort width, height;
151 ushort bpp, bpl, depth, pad;
152 ushort swidth, sheight;
153 int norm;
154 int interlace;
155 u32 color_fmt;
156 int chromakey;
157 int mode; /* used to switch between TV/VTR modes */
160 struct planb_suspend {
161 int overlay;
162 int frame;
163 struct dbdma_cmd cmd;
166 struct planb {
167 struct video_device video_dev;
168 struct video_picture picture; /* Current picture params */
169 struct video_audio audio_dev; /* Current audio params */
171 volatile struct planb_registers *planb_base; /* virt base of planb */
172 struct planb_registers *planb_base_phys; /* phys base of planb */
173 void *priv_space; /* Org. alloc. mem for kfree */
174 int user;
175 unsigned int tab_size;
176 int maxlines;
177 struct mutex lock;
178 unsigned int irq; /* interrupt number */
179 volatile unsigned int intr_mask;
180 struct pci_dev *dev; /* Our PCI device */
182 int overlay; /* overlay running? */
183 struct planb_window win;
184 unsigned long frame_buffer_phys; /* We need phys for DMA */
185 int offset; /* offset of pixel 1 */
186 volatile struct dbdma_cmd *ch1_cmd; /* Video In DMA cmd buffer */
187 volatile struct dbdma_cmd *ch2_cmd; /* Clip Out DMA cmd buffer */
188 volatile struct dbdma_cmd *overlay_last1;
189 volatile struct dbdma_cmd *overlay_last2;
190 unsigned long ch1_cmd_phys;
191 volatile unsigned char *mask; /* Clipmask buffer */
192 int suspend;
193 wait_queue_head_t suspendq;
194 struct planb_suspend suspended;
195 int cmd_buff_inited; /* cmd buffer inited? */
197 int grabbing;
198 unsigned int gcount;
199 wait_queue_head_t capq;
200 int last_fr;
201 int prev_last_fr;
202 unsigned char **rawbuf;
203 int rawbuf_size;
204 int gbuf_idx[MAX_GBUFFERS];
205 volatile struct dbdma_cmd *cap_cmd[MAX_GBUFFERS];
206 volatile struct dbdma_cmd *last_cmd[MAX_GBUFFERS];
207 volatile struct dbdma_cmd *pre_cmd[MAX_GBUFFERS];
208 int need_pre_capture[MAX_GBUFFERS];
209 #define PLANB_DUMMY 40 /* # of command buf's allocated for pre-capture seq. */
210 int gwidth[MAX_GBUFFERS], gheight[MAX_GBUFFERS];
211 unsigned int gfmt[MAX_GBUFFERS];
212 int gnorm_switch[MAX_GBUFFERS];
213 volatile unsigned int *frame_stat;
214 #define GBUFFER_UNUSED 0x00U
215 #define GBUFFER_GRABBING 0x01U
216 #define GBUFFER_DONE 0x02U
217 #ifdef PLANB_GSCANLINE
218 int gbytes_per_line;
219 #else
220 #define MAX_LNUM 431 /* change this if PLANB_MAXLINES or */
221 /* PLANB_MAXPIXELS changes */
222 int l_fr_addr_idx[MAX_GBUFFERS];
223 unsigned char *l_to_addr[MAX_GBUFFERS][MAX_LNUM];
224 int l_to_next_idx[MAX_GBUFFERS][MAX_LNUM];
225 int l_to_next_size[MAX_GBUFFERS][MAX_LNUM];
226 int lsize[MAX_GBUFFERS], lnum[MAX_GBUFFERS];
227 #endif
230 #endif /* __KERNEL__ */
232 #endif /* _PLANB_H_ */