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Initial commit
[wrt350n-kernel.git] / drivers / media / video / sn9c102 / sn9c102_hv7131r.c
blob0fc401223cfc9c08741fa3595b93cadf7811f5b3
1 /***************************************************************************
2 * Plug-in for HV7131R image sensor connected to the SN9C1xx PC Camera *
3 * Controllers *
4 * *
5 * Copyright (C) 2007 by Luca Risolia <luca.risolia@studio.unibo.it> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the Free Software *
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
20 ***************************************************************************/
21
22 #include "sn9c102_sensor.h"
23
24
25 static int hv7131r_init(struct sn9c102_device* cam)
26 {
27 int err = 0;
28
29 switch (sn9c102_get_bridge(cam)) {
30 case BRIDGE_SN9C103:
31 err = sn9c102_write_const_regs(cam, {0x00, 0x03}, {0x1a, 0x04},
32 {0x20, 0x05}, {0x20, 0x06},
33 {0x03, 0x10}, {0x00, 0x14},
34 {0x60, 0x17}, {0x0a, 0x18},
35 {0xf0, 0x19}, {0x1d, 0x1a},
36 {0x10, 0x1b}, {0x02, 0x1c},
37 {0x03, 0x1d}, {0x0f, 0x1e},
38 {0x0c, 0x1f}, {0x00, 0x20},
39 {0x10, 0x21}, {0x20, 0x22},
40 {0x30, 0x23}, {0x40, 0x24},
41 {0x50, 0x25}, {0x60, 0x26},
42 {0x70, 0x27}, {0x80, 0x28},
43 {0x90, 0x29}, {0xa0, 0x2a},
44 {0xb0, 0x2b}, {0xc0, 0x2c},
45 {0xd0, 0x2d}, {0xe0, 0x2e},
46 {0xf0, 0x2f}, {0xff, 0x30});
47 break;
48 case BRIDGE_SN9C105:
49 case BRIDGE_SN9C120:
50 err = sn9c102_write_const_regs(cam, {0x44, 0x01}, {0x40, 0x02},
51 {0x00, 0x03}, {0x1a, 0x04},
52 {0x44, 0x05}, {0x3e, 0x06},
53 {0x1a, 0x07}, {0x03, 0x10},
54 {0x08, 0x14}, {0xa3, 0x17},
55 {0x4b, 0x18}, {0x00, 0x19},
56 {0x1d, 0x1a}, {0x10, 0x1b},
57 {0x02, 0x1c}, {0x03, 0x1d},
58 {0x0f, 0x1e}, {0x0c, 0x1f},
59 {0x00, 0x20}, {0x29, 0x21},
60 {0x40, 0x22}, {0x54, 0x23},
61 {0x66, 0x24}, {0x76, 0x25},
62 {0x85, 0x26}, {0x94, 0x27},
63 {0xa1, 0x28}, {0xae, 0x29},
64 {0xbb, 0x2a}, {0xc7, 0x2b},
65 {0xd3, 0x2c}, {0xde, 0x2d},
66 {0xea, 0x2e}, {0xf4, 0x2f},
67 {0xff, 0x30}, {0x00, 0x3F},
68 {0xC7, 0x40}, {0x01, 0x41},
69 {0x44, 0x42}, {0x00, 0x43},
70 {0x44, 0x44}, {0x00, 0x45},
71 {0x44, 0x46}, {0x00, 0x47},
72 {0xC7, 0x48}, {0x01, 0x49},
73 {0xC7, 0x4A}, {0x01, 0x4B},
74 {0xC7, 0x4C}, {0x01, 0x4D},
75 {0x44, 0x4E}, {0x00, 0x4F},
76 {0x44, 0x50}, {0x00, 0x51},
77 {0x44, 0x52}, {0x00, 0x53},
78 {0xC7, 0x54}, {0x01, 0x55},
79 {0xC7, 0x56}, {0x01, 0x57},
80 {0xC7, 0x58}, {0x01, 0x59},
81 {0x44, 0x5A}, {0x00, 0x5B},
82 {0x44, 0x5C}, {0x00, 0x5D},
83 {0x44, 0x5E}, {0x00, 0x5F},
84 {0xC7, 0x60}, {0x01, 0x61},
85 {0xC7, 0x62}, {0x01, 0x63},
86 {0xC7, 0x64}, {0x01, 0x65},
87 {0x44, 0x66}, {0x00, 0x67},
88 {0x44, 0x68}, {0x00, 0x69},
89 {0x44, 0x6A}, {0x00, 0x6B},
90 {0xC7, 0x6C}, {0x01, 0x6D},
91 {0xC7, 0x6E}, {0x01, 0x6F},
92 {0xC7, 0x70}, {0x01, 0x71},
93 {0x44, 0x72}, {0x00, 0x73},
94 {0x44, 0x74}, {0x00, 0x75},
95 {0x44, 0x76}, {0x00, 0x77},
96 {0xC7, 0x78}, {0x01, 0x79},
97 {0xC7, 0x7A}, {0x01, 0x7B},
98 {0xC7, 0x7C}, {0x01, 0x7D},
99 {0x44, 0x7E}, {0x00, 0x7F},
100 {0x14, 0x84}, {0x00, 0x85},
101 {0x27, 0x86}, {0x00, 0x87},
102 {0x07, 0x88}, {0x00, 0x89},
103 {0xEC, 0x8A}, {0x0f, 0x8B},
104 {0xD8, 0x8C}, {0x0f, 0x8D},
105 {0x3D, 0x8E}, {0x00, 0x8F},
106 {0x3D, 0x90}, {0x00, 0x91},
107 {0xCD, 0x92}, {0x0f, 0x93},
108 {0xf7, 0x94}, {0x0f, 0x95},
109 {0x0C, 0x96}, {0x00, 0x97},
110 {0x00, 0x98}, {0x66, 0x99},
111 {0x05, 0x9A}, {0x00, 0x9B},
112 {0x04, 0x9C}, {0x00, 0x9D},
113 {0x08, 0x9E}, {0x00, 0x9F},
114 {0x2D, 0xC0}, {0x2D, 0xC1},
115 {0x3A, 0xC2}, {0x05, 0xC3},
116 {0x04, 0xC4}, {0x3F, 0xC5},
117 {0x00, 0xC6}, {0x00, 0xC7},
118 {0x50, 0xC8}, {0x3C, 0xC9},
119 {0x28, 0xCA}, {0xD8, 0xCB},
120 {0x14, 0xCC}, {0xEC, 0xCD},
121 {0x32, 0xCE}, {0xDD, 0xCF},
122 {0x32, 0xD0}, {0xDD, 0xD1},
123 {0x6A, 0xD2}, {0x50, 0xD3},
124 {0x00, 0xD4}, {0x00, 0xD5},
125 {0x00, 0xD6});
126 break;
127 default:
128 break;
129 }
130
131 err += sn9c102_i2c_write(cam, 0x20, 0x00);
132 err += sn9c102_i2c_write(cam, 0x21, 0xd6);
133 err += sn9c102_i2c_write(cam, 0x25, 0x06);
134
135 return err;
136 }
137
138
139 static int hv7131r_get_ctrl(struct sn9c102_device* cam,
140 struct v4l2_control* ctrl)
141 {
142 switch (ctrl->id) {
143 case V4L2_CID_GAIN:
144 if ((ctrl->value = sn9c102_i2c_read(cam, 0x30)) < 0)
145 return -EIO;
146 return 0;
147 case V4L2_CID_RED_BALANCE:
148 if ((ctrl->value = sn9c102_i2c_read(cam, 0x31)) < 0)
149 return -EIO;
150 ctrl->value = ctrl->value & 0x3f;
151 return 0;
152 case V4L2_CID_BLUE_BALANCE:
153 if ((ctrl->value = sn9c102_i2c_read(cam, 0x33)) < 0)
154 return -EIO;
155 ctrl->value = ctrl->value & 0x3f;
156 return 0;
157 case SN9C102_V4L2_CID_GREEN_BALANCE:
158 if ((ctrl->value = sn9c102_i2c_read(cam, 0x32)) < 0)
159 return -EIO;
160 ctrl->value = ctrl->value & 0x3f;
161 return 0;
162 case V4L2_CID_BLACK_LEVEL:
163 if ((ctrl->value = sn9c102_i2c_read(cam, 0x01)) < 0)
164 return -EIO;
165 ctrl->value = (ctrl->value & 0x08) ? 1 : 0;
166 return 0;
167 default:
168 return -EINVAL;
169 }
170 }
171
172
173 static int hv7131r_set_ctrl(struct sn9c102_device* cam,
174 const struct v4l2_control* ctrl)
175 {
176 int err = 0;
177
178 switch (ctrl->id) {
179 case V4L2_CID_GAIN:
180 err += sn9c102_i2c_write(cam, 0x30, ctrl->value);
181 break;
182 case V4L2_CID_RED_BALANCE:
183 err += sn9c102_i2c_write(cam, 0x31, ctrl->value);
184 break;
185 case V4L2_CID_BLUE_BALANCE:
186 err += sn9c102_i2c_write(cam, 0x33, ctrl->value);
187 break;
188 case SN9C102_V4L2_CID_GREEN_BALANCE:
189 err += sn9c102_i2c_write(cam, 0x32, ctrl->value);
190 break;
191 case V4L2_CID_BLACK_LEVEL:
192 {
193 int r = sn9c102_i2c_read(cam, 0x01);
194 if (r < 0)
195 return -EIO;
196 err += sn9c102_i2c_write(cam, 0x01,
197 (ctrl->value<<3) | (r&0xf7));
198 }
199 break;
200 default:
201 return -EINVAL;
202 }
203
204 return err ? -EIO : 0;
205 }
206
207
208 static int hv7131r_set_crop(struct sn9c102_device* cam,
209 const struct v4l2_rect* rect)
210 {
211 struct sn9c102_sensor* s = sn9c102_get_sensor(cam);
212 int err = 0;
213 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1,
214 v_start = (u8)(rect->top - s->cropcap.bounds.top) + 1;
215
216 err += sn9c102_write_reg(cam, h_start, 0x12);
217 err += sn9c102_write_reg(cam, v_start, 0x13);
218
219 return err;
220 }
221
222
223 static int hv7131r_set_pix_format(struct sn9c102_device* cam,
224 const struct v4l2_pix_format* pix)
225 {
226 int err = 0;
227
228 switch (sn9c102_get_bridge(cam)) {
229 case BRIDGE_SN9C103:
230 if (pix->pixelformat == V4L2_PIX_FMT_SBGGR8) {
231 err += sn9c102_write_reg(cam, 0xa0, 0x19);
232 err += sn9c102_i2c_write(cam, 0x01, 0x04);
233 } else {
234 err += sn9c102_write_reg(cam, 0x30, 0x19);
235 err += sn9c102_i2c_write(cam, 0x01, 0x04);
236 }
237 break;
238 case BRIDGE_SN9C105:
239 case BRIDGE_SN9C120:
240 if (pix->pixelformat == V4L2_PIX_FMT_SBGGR8) {
241 err += sn9c102_write_reg(cam, 0xa5, 0x17);
242 err += sn9c102_i2c_write(cam, 0x01, 0x24);
243 } else {
244 err += sn9c102_write_reg(cam, 0xa3, 0x17);
245 err += sn9c102_i2c_write(cam, 0x01, 0x04);
246 }
247 break;
248 default:
249 break;
250 }
251
252 return err;
253 }
254
255
256 static const struct sn9c102_sensor hv7131r = {
257 .name = "HV7131R",
258 .maintainer = "Luca Risolia <luca.risolia@studio.unibo.it>",
259 .supported_bridge = BRIDGE_SN9C103 | BRIDGE_SN9C105 | BRIDGE_SN9C120,
260 .sysfs_ops = SN9C102_I2C_READ | SN9C102_I2C_WRITE,
261 .frequency = SN9C102_I2C_100KHZ,
262 .interface = SN9C102_I2C_2WIRES,
263 .i2c_slave_id = 0x11,
264 .init = &hv7131r_init,
265 .qctrl = {
266 {
267 .id = V4L2_CID_GAIN,
268 .type = V4L2_CTRL_TYPE_INTEGER,
269 .name = "global gain",
270 .minimum = 0x00,
271 .maximum = 0xff,
272 .step = 0x01,
273 .default_value = 0x40,
274 .flags = 0,
275 },
276 {
277 .id = V4L2_CID_RED_BALANCE,
278 .type = V4L2_CTRL_TYPE_INTEGER,
279 .name = "red balance",
280 .minimum = 0x00,
281 .maximum = 0x3f,
282 .step = 0x01,
283 .default_value = 0x08,
284 .flags = 0,
285 },
286 {
287 .id = V4L2_CID_BLUE_BALANCE,
288 .type = V4L2_CTRL_TYPE_INTEGER,
289 .name = "blue balance",
290 .minimum = 0x00,
291 .maximum = 0x3f,
292 .step = 0x01,
293 .default_value = 0x1a,
294 .flags = 0,
295 },
296 {
297 .id = SN9C102_V4L2_CID_GREEN_BALANCE,
298 .type = V4L2_CTRL_TYPE_INTEGER,
299 .name = "green balance",
300 .minimum = 0x00,
301 .maximum = 0x3f,
302 .step = 0x01,
303 .default_value = 0x2f,
304 .flags = 0,
305 },
306 {
307 .id = V4L2_CID_BLACK_LEVEL,
308 .type = V4L2_CTRL_TYPE_BOOLEAN,
309 .name = "auto black level compensation",
310 .minimum = 0x00,
311 .maximum = 0x01,
312 .step = 0x01,
313 .default_value = 0x00,
314 .flags = 0,
315 },
316 },
317 .get_ctrl = &hv7131r_get_ctrl,
318 .set_ctrl = &hv7131r_set_ctrl,
319 .cropcap = {
320 .bounds = {
321 .left = 0,
322 .top = 0,
323 .width = 640,
324 .height = 480,
325 },
326 .defrect = {
327 .left = 0,
328 .top = 0,
329 .width = 640,
330 .height = 480,
331 },
332 },
333 .set_crop = &hv7131r_set_crop,
334 .pix_format = {
335 .width = 640,
336 .height = 480,
337 .pixelformat = V4L2_PIX_FMT_SBGGR8,
338 .priv = 8,
339 },
340 .set_pix_format = &hv7131r_set_pix_format
341 };
342
343
344 int sn9c102_probe_hv7131r(struct sn9c102_device* cam)
345 {
346 int devid, err;
347
348 err = sn9c102_write_const_regs(cam, {0x09, 0x01}, {0x44, 0x02},
349 {0x34, 0x01}, {0x20, 0x17},
350 {0x34, 0x01}, {0x46, 0x01});
351
352 devid = sn9c102_i2c_try_read(cam, &hv7131r, 0x00);
353 if (err || devid < 0)
354 return -EIO;
355
356 if (devid != 0x02)
357 return -ENODEV;
358
359 sn9c102_attach_sensor(cam, &hv7131r);
360
361 return 0;
362 }
WRT350N Kernel Patches