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Initial commit
[wrt350n-kernel.git] / drivers / net / ibm_newemac / mal.c
blob6869f08c9dcba0188b920524e68c747d1445fb9f
1 /*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
16 * David Gibson <hermes@gibson.dropbear.id.au>,
17 *
18 * Armin Kuster <akuster@mvista.com>
19 * Copyright 2002 MontaVista Softare Inc.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 */
27
28 #include <linux/delay.h>
29
30 #include "core.h"
31
32 static int mal_count;
33
34 int __devinit mal_register_commac(struct mal_instance *mal,
35 struct mal_commac *commac)
36 {
37 unsigned long flags;
38
39 spin_lock_irqsave(&mal->lock, flags);
40
41 MAL_DBG(mal, "reg(%08x, %08x)" NL,
42 commac->tx_chan_mask, commac->rx_chan_mask);
43
44 /* Don't let multiple commacs claim the same channel(s) */
45 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
46 (mal->rx_chan_mask & commac->rx_chan_mask)) {
47 spin_unlock_irqrestore(&mal->lock, flags);
48 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
49 mal->index);
50 return -EBUSY;
51 }
52
53 if (list_empty(&mal->list))
54 napi_enable(&mal->napi);
55 mal->tx_chan_mask |= commac->tx_chan_mask;
56 mal->rx_chan_mask |= commac->rx_chan_mask;
57 list_add(&commac->list, &mal->list);
58
59 spin_unlock_irqrestore(&mal->lock, flags);
60
61 return 0;
62 }
63
64 void __devexit mal_unregister_commac(struct mal_instance *mal,
65 struct mal_commac *commac)
66 {
67 unsigned long flags;
68
69 spin_lock_irqsave(&mal->lock, flags);
70
71 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
72 commac->tx_chan_mask, commac->rx_chan_mask);
73
74 mal->tx_chan_mask &= ~commac->tx_chan_mask;
75 mal->rx_chan_mask &= ~commac->rx_chan_mask;
76 list_del_init(&commac->list);
77 if (list_empty(&mal->list))
78 napi_disable(&mal->napi);
79
80 spin_unlock_irqrestore(&mal->lock, flags);
81 }
82
83 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
84 {
85 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
86 size > MAL_MAX_RX_SIZE);
87
88 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
89
90 if (size & 0xf) {
91 printk(KERN_WARNING
92 "mal%d: incorrect RX size %lu for the channel %d\n",
93 mal->index, size, channel);
94 return -EINVAL;
95 }
96
97 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
98 return 0;
99 }
100
101 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
102 {
103 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
104
105 return channel * NUM_TX_BUFF;
106 }
107
108 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
109 {
110 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
111 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
112 }
113
114 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
115 {
116 unsigned long flags;
117
118 spin_lock_irqsave(&mal->lock, flags);
119
120 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
121
122 set_mal_dcrn(mal, MAL_TXCASR,
123 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
124
125 spin_unlock_irqrestore(&mal->lock, flags);
126 }
127
128 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
129 {
130 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
131
132 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
133 }
134
135 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
136 {
137 unsigned long flags;
138
139 spin_lock_irqsave(&mal->lock, flags);
140
141 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
142
143 set_mal_dcrn(mal, MAL_RXCASR,
144 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
145
146 spin_unlock_irqrestore(&mal->lock, flags);
147 }
148
149 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
150 {
151 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
152
153 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
154 }
155
156 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
157 {
158 unsigned long flags;
159
160 spin_lock_irqsave(&mal->lock, flags);
161
162 MAL_DBG(mal, "poll_add(%p)" NL, commac);
163
164 /* starts disabled */
165 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
166
167 list_add_tail(&commac->poll_list, &mal->poll_list);
168
169 spin_unlock_irqrestore(&mal->lock, flags);
170 }
171
172 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
173 {
174 unsigned long flags;
175
176 spin_lock_irqsave(&mal->lock, flags);
177
178 MAL_DBG(mal, "poll_del(%p)" NL, commac);
179
180 list_del(&commac->poll_list);
181
182 spin_unlock_irqrestore(&mal->lock, flags);
183 }
184
185 /* synchronized by mal_poll() */
186 static inline void mal_enable_eob_irq(struct mal_instance *mal)
187 {
188 MAL_DBG2(mal, "enable_irq" NL);
189
190 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
191 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
192 }
193
194 /* synchronized by NAPI state */
195 static inline void mal_disable_eob_irq(struct mal_instance *mal)
196 {
197 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
198 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
199
200 MAL_DBG2(mal, "disable_irq" NL);
201 }
202
203 static irqreturn_t mal_serr(int irq, void *dev_instance)
204 {
205 struct mal_instance *mal = dev_instance;
206
207 u32 esr = get_mal_dcrn(mal, MAL_ESR);
208
209 /* Clear the error status register */
210 set_mal_dcrn(mal, MAL_ESR, esr);
211
212 MAL_DBG(mal, "SERR %08x" NL, esr);
213
214 if (esr & MAL_ESR_EVB) {
215 if (esr & MAL_ESR_DE) {
216 /* We ignore Descriptor error,
217 * TXDE or RXDE interrupt will be generated anyway.
218 */
219 return IRQ_HANDLED;
220 }
221
222 if (esr & MAL_ESR_PEIN) {
223 /* PLB error, it's probably buggy hardware or
224 * incorrect physical address in BD (i.e. bug)
225 */
226 if (net_ratelimit())
227 printk(KERN_ERR
228 "mal%d: system error, "
229 "PLB (ESR = 0x%08x)\n",
230 mal->index, esr);
231 return IRQ_HANDLED;
232 }
233
234 /* OPB error, it's probably buggy hardware or incorrect
235 * EBC setup
236 */
237 if (net_ratelimit())
238 printk(KERN_ERR
239 "mal%d: system error, OPB (ESR = 0x%08x)\n",
240 mal->index, esr);
241 }
242 return IRQ_HANDLED;
243 }
244
245 static inline void mal_schedule_poll(struct mal_instance *mal)
246 {
247 if (likely(napi_schedule_prep(&mal->napi))) {
248 MAL_DBG2(mal, "schedule_poll" NL);
249 mal_disable_eob_irq(mal);
250 __napi_schedule(&mal->napi);
251 } else
252 MAL_DBG2(mal, "already in poll" NL);
253 }
254
255 static irqreturn_t mal_txeob(int irq, void *dev_instance)
256 {
257 struct mal_instance *mal = dev_instance;
258
259 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
260
261 MAL_DBG2(mal, "txeob %08x" NL, r);
262
263 mal_schedule_poll(mal);
264 set_mal_dcrn(mal, MAL_TXEOBISR, r);
265
266 return IRQ_HANDLED;
267 }
268
269 static irqreturn_t mal_rxeob(int irq, void *dev_instance)
270 {
271 struct mal_instance *mal = dev_instance;
272
273 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
274
275 MAL_DBG2(mal, "rxeob %08x" NL, r);
276
277 mal_schedule_poll(mal);
278 set_mal_dcrn(mal, MAL_RXEOBISR, r);
279
280 return IRQ_HANDLED;
281 }
282
283 static irqreturn_t mal_txde(int irq, void *dev_instance)
284 {
285 struct mal_instance *mal = dev_instance;
286
287 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
288 set_mal_dcrn(mal, MAL_TXDEIR, deir);
289
290 MAL_DBG(mal, "txde %08x" NL, deir);
291
292 if (net_ratelimit())
293 printk(KERN_ERR
294 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
295 mal->index, deir);
296
297 return IRQ_HANDLED;
298 }
299
300 static irqreturn_t mal_rxde(int irq, void *dev_instance)
301 {
302 struct mal_instance *mal = dev_instance;
303 struct list_head *l;
304
305 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
306
307 MAL_DBG(mal, "rxde %08x" NL, deir);
308
309 list_for_each(l, &mal->list) {
310 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
311 if (deir & mc->rx_chan_mask) {
312 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
313 mc->ops->rxde(mc->dev);
314 }
315 }
316
317 mal_schedule_poll(mal);
318 set_mal_dcrn(mal, MAL_RXDEIR, deir);
319
320 return IRQ_HANDLED;
321 }
322
323 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
324 {
325 /* Spinlock-type semantics: only one caller disable poll at a time */
326 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
327 msleep(1);
328
329 /* Synchronize with the MAL NAPI poller */
330 napi_synchronize(&mal->napi);
331 }
332
333 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
334 {
335 smp_wmb();
336 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
337
338 /* Feels better to trigger a poll here to catch up with events that
339 * may have happened on this channel while disabled. It will most
340 * probably be delayed until the next interrupt but that's mostly a
341 * non-issue in the context where this is called.
342 */
343 napi_schedule(&mal->napi);
344 }
345
346 static int mal_poll(struct napi_struct *napi, int budget)
347 {
348 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
349 struct list_head *l;
350 int received = 0;
351 unsigned long flags;
352
353 MAL_DBG2(mal, "poll(%d)" NL, budget);
354 again:
355 /* Process TX skbs */
356 list_for_each(l, &mal->poll_list) {
357 struct mal_commac *mc =
358 list_entry(l, struct mal_commac, poll_list);
359 mc->ops->poll_tx(mc->dev);
360 }
361
362 /* Process RX skbs.
363 *
364 * We _might_ need something more smart here to enforce polling
365 * fairness.
366 */
367 list_for_each(l, &mal->poll_list) {
368 struct mal_commac *mc =
369 list_entry(l, struct mal_commac, poll_list);
370 int n;
371 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
372 continue;
373 n = mc->ops->poll_rx(mc->dev, budget);
374 if (n) {
375 received += n;
376 budget -= n;
377 if (budget <= 0)
378 goto more_work; // XXX What if this is the last one ?
379 }
380 }
381
382 /* We need to disable IRQs to protect from RXDE IRQ here */
383 spin_lock_irqsave(&mal->lock, flags);
384 __napi_complete(napi);
385 mal_enable_eob_irq(mal);
386 spin_unlock_irqrestore(&mal->lock, flags);
387
388 /* Check for "rotting" packet(s) */
389 list_for_each(l, &mal->poll_list) {
390 struct mal_commac *mc =
391 list_entry(l, struct mal_commac, poll_list);
392 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
393 continue;
394 if (unlikely(mc->ops->peek_rx(mc->dev) ||
395 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
396 MAL_DBG2(mal, "rotting packet" NL);
397 if (napi_reschedule(napi))
398 mal_disable_eob_irq(mal);
399 else
400 MAL_DBG2(mal, "already in poll list" NL);
401
402 if (budget > 0)
403 goto again;
404 else
405 goto more_work;
406 }
407 mc->ops->poll_tx(mc->dev);
408 }
409
410 more_work:
411 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
412 return received;
413 }
414
415 static void mal_reset(struct mal_instance *mal)
416 {
417 int n = 10;
418
419 MAL_DBG(mal, "reset" NL);
420
421 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
422
423 /* Wait for reset to complete (1 system clock) */
424 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
425 --n;
426
427 if (unlikely(!n))
428 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
429 }
430
431 int mal_get_regs_len(struct mal_instance *mal)
432 {
433 return sizeof(struct emac_ethtool_regs_subhdr) +
434 sizeof(struct mal_regs);
435 }
436
437 void *mal_dump_regs(struct mal_instance *mal, void *buf)
438 {
439 struct emac_ethtool_regs_subhdr *hdr = buf;
440 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
441 int i;
442
443 hdr->version = mal->version;
444 hdr->index = mal->index;
445
446 regs->tx_count = mal->num_tx_chans;
447 regs->rx_count = mal->num_rx_chans;
448
449 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
450 regs->esr = get_mal_dcrn(mal, MAL_ESR);
451 regs->ier = get_mal_dcrn(mal, MAL_IER);
452 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
453 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
454 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
455 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
456 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
457 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
458 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
459 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
460
461 for (i = 0; i < regs->tx_count; ++i)
462 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
463
464 for (i = 0; i < regs->rx_count; ++i) {
465 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
466 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
467 }
468 return regs + 1;
469 }
470
471 static int __devinit mal_probe(struct of_device *ofdev,
472 const struct of_device_id *match)
473 {
474 struct mal_instance *mal;
475 int err = 0, i, bd_size;
476 int index = mal_count++;
477 unsigned int dcr_base;
478 const u32 *prop;
479 u32 cfg;
480
481 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
482 if (!mal) {
483 printk(KERN_ERR
484 "mal%d: out of memory allocating MAL structure!\n",
485 index);
486 return -ENOMEM;
487 }
488 mal->index = index;
489 mal->ofdev = ofdev;
490 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
491
492 MAL_DBG(mal, "probe" NL);
493
494 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
495 if (prop == NULL) {
496 printk(KERN_ERR
497 "mal%d: can't find MAL num-tx-chans property!\n",
498 index);
499 err = -ENODEV;
500 goto fail;
501 }
502 mal->num_tx_chans = prop[0];
503
504 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
505 if (prop == NULL) {
506 printk(KERN_ERR
507 "mal%d: can't find MAL num-rx-chans property!\n",
508 index);
509 err = -ENODEV;
510 goto fail;
511 }
512 mal->num_rx_chans = prop[0];
513
514 dcr_base = dcr_resource_start(ofdev->node, 0);
515 if (dcr_base == 0) {
516 printk(KERN_ERR
517 "mal%d: can't find DCR resource!\n", index);
518 err = -ENODEV;
519 goto fail;
520 }
521 mal->dcr_host = dcr_map(ofdev->node, dcr_base, 0x100);
522 if (!DCR_MAP_OK(mal->dcr_host)) {
523 printk(KERN_ERR
524 "mal%d: failed to map DCRs !\n", index);
525 err = -ENODEV;
526 goto fail;
527 }
528
529 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
530 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
531 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
532 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
533 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
534 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
535 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
536 mal->rxde_irq == NO_IRQ) {
537 printk(KERN_ERR
538 "mal%d: failed to map interrupts !\n", index);
539 err = -ENODEV;
540 goto fail_unmap;
541 }
542
543 INIT_LIST_HEAD(&mal->poll_list);
544 INIT_LIST_HEAD(&mal->list);
545 spin_lock_init(&mal->lock);
546
547 netif_napi_add(NULL, &mal->napi, mal_poll,
548 CONFIG_IBM_NEW_EMAC_POLL_WEIGHT);
549
550 /* Load power-on reset defaults */
551 mal_reset(mal);
552
553 /* Set the MAL configuration register */
554 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
555 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
556
557 /* Current Axon is not happy with priority being non-0, it can
558 * deadlock, fix it up here
559 */
560 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
561 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
562
563 /* Apply configuration */
564 set_mal_dcrn(mal, MAL_CFG, cfg);
565
566 /* Allocate space for BD rings */
567 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
568 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
569
570 bd_size = sizeof(struct mal_descriptor) *
571 (NUM_TX_BUFF * mal->num_tx_chans +
572 NUM_RX_BUFF * mal->num_rx_chans);
573 mal->bd_virt =
574 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
575 GFP_KERNEL);
576 if (mal->bd_virt == NULL) {
577 printk(KERN_ERR
578 "mal%d: out of memory allocating RX/TX descriptors!\n",
579 index);
580 err = -ENOMEM;
581 goto fail_unmap;
582 }
583 memset(mal->bd_virt, 0, bd_size);
584
585 for (i = 0; i < mal->num_tx_chans; ++i)
586 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
587 sizeof(struct mal_descriptor) *
588 mal_tx_bd_offset(mal, i));
589
590 for (i = 0; i < mal->num_rx_chans; ++i)
591 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
592 sizeof(struct mal_descriptor) *
593 mal_rx_bd_offset(mal, i));
594
595 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
596 if (err)
597 goto fail2;
598 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
599 if (err)
600 goto fail3;
601 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
602 if (err)
603 goto fail4;
604 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
605 if (err)
606 goto fail5;
607 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
608 if (err)
609 goto fail6;
610
611 /* Enable all MAL SERR interrupt sources */
612 if (mal->version == 2)
613 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
614 else
615 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
616
617 /* Enable EOB interrupt */
618 mal_enable_eob_irq(mal);
619
620 printk(KERN_INFO
621 "MAL v%d %s, %d TX channels, %d RX channels\n",
622 mal->version, ofdev->node->full_name,
623 mal->num_tx_chans, mal->num_rx_chans);
624
625 /* Advertise this instance to the rest of the world */
626 wmb();
627 dev_set_drvdata(&ofdev->dev, mal);
628
629 mal_dbg_register(mal);
630
631 return 0;
632
633 fail6:
634 free_irq(mal->rxde_irq, mal);
635 fail5:
636 free_irq(mal->txeob_irq, mal);
637 fail4:
638 free_irq(mal->txde_irq, mal);
639 fail3:
640 free_irq(mal->serr_irq, mal);
641 fail2:
642 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
643 fail_unmap:
644 dcr_unmap(mal->dcr_host, 0x100);
645 fail:
646 kfree(mal);
647
648 return err;
649 }
650
651 static int __devexit mal_remove(struct of_device *ofdev)
652 {
653 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
654
655 MAL_DBG(mal, "remove" NL);
656
657 /* Synchronize with scheduled polling */
658 napi_disable(&mal->napi);
659
660 if (!list_empty(&mal->list)) {
661 /* This is *very* bad */
662 printk(KERN_EMERG
663 "mal%d: commac list is not empty on remove!\n",
664 mal->index);
665 WARN_ON(1);
666 }
667
668 dev_set_drvdata(&ofdev->dev, NULL);
669
670 free_irq(mal->serr_irq, mal);
671 free_irq(mal->txde_irq, mal);
672 free_irq(mal->txeob_irq, mal);
673 free_irq(mal->rxde_irq, mal);
674 free_irq(mal->rxeob_irq, mal);
675
676 mal_reset(mal);
677
678 mal_dbg_unregister(mal);
679
680 dma_free_coherent(&ofdev->dev,
681 sizeof(struct mal_descriptor) *
682 (NUM_TX_BUFF * mal->num_tx_chans +
683 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
684 mal->bd_dma);
685 kfree(mal);
686
687 return 0;
688 }
689
690 static struct of_device_id mal_platform_match[] =
691 {
692 {
693 .compatible = "ibm,mcmal",
694 },
695 {
696 .compatible = "ibm,mcmal2",
697 },
698 /* Backward compat */
699 {
700 .type = "mcmal-dma",
701 .compatible = "ibm,mcmal",
702 },
703 {
704 .type = "mcmal-dma",
705 .compatible = "ibm,mcmal2",
706 },
707 {},
708 };
709
710 static struct of_platform_driver mal_of_driver = {
711 .name = "mcmal",
712 .match_table = mal_platform_match,
713
714 .probe = mal_probe,
715 .remove = mal_remove,
716 };
717
718 int __init mal_init(void)
719 {
720 return of_register_platform_driver(&mal_of_driver);
721 }
722
723 void mal_exit(void)
724 {
725 of_unregister_platform_driver(&mal_of_driver);
726 }
WRT350N Kernel Patches