?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Initial commit
[wrt350n-kernel.git] / drivers / serial / imx.c
blob56af1f566a4cd1b0ebfc7d78f71646ca267face9
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
28
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #define SUPPORT_SYSRQ
31 #endif
32
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/hardware.h>
47 #include <asm/arch/imx-uart.h>
48
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
65 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
66 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
67 #define BIPR4 0xbc /* Incremental Preset Register 4 */
68 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
69 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
70 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
71 #define BMPR4 0xcc /* BRM Modulator Register 4 */
72 #define UTS 0xd0 /* UART Test Register */
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
164
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 204
167 #define MINOR_START 41
168
169 #define NR_PORTS 2
170
171 #define IMX_ISR_PASS_LIMIT 256
172
173 /*
174 * This is the size of our serial port register set.
175 */
176 #define UART_PORT_SIZE 0x100
177
178 /*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184 #define MCTRL_TIMEOUT (250*HZ/1000)
185
186 #define DRIVER_NAME "IMX-uart"
187
188 struct imx_port {
189 struct uart_port port;
190 struct timer_list timer;
191 unsigned int old_status;
192 int txirq,rxirq,rtsirq;
193 int have_rtscts:1;
194 };
195
196 /*
197 * Handle any change of modem status signal since we were last called.
198 */
199 static void imx_mctrl_check(struct imx_port *sport)
200 {
201 unsigned int status, changed;
202
203 status = sport->port.ops->get_mctrl(&sport->port);
204 changed = status ^ sport->old_status;
205
206 if (changed == 0)
207 return;
208
209 sport->old_status = status;
210
211 if (changed & TIOCM_RI)
212 sport->port.icount.rng++;
213 if (changed & TIOCM_DSR)
214 sport->port.icount.dsr++;
215 if (changed & TIOCM_CAR)
216 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
217 if (changed & TIOCM_CTS)
218 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
219
220 wake_up_interruptible(&sport->port.info->delta_msr_wait);
221 }
222
223 /*
224 * This is our per-port timeout handler, for checking the
225 * modem status signals.
226 */
227 static void imx_timeout(unsigned long data)
228 {
229 struct imx_port *sport = (struct imx_port *)data;
230 unsigned long flags;
231
232 if (sport->port.info) {
233 spin_lock_irqsave(&sport->port.lock, flags);
234 imx_mctrl_check(sport);
235 spin_unlock_irqrestore(&sport->port.lock, flags);
236
237 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
238 }
239 }
240
241 /*
242 * interrupts disabled on entry
243 */
244 static void imx_stop_tx(struct uart_port *port)
245 {
246 struct imx_port *sport = (struct imx_port *)port;
247 unsigned long temp;
248
249 temp = readl(sport->port.membase + UCR1);
250 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
251 }
252
253 /*
254 * interrupts disabled on entry
255 */
256 static void imx_stop_rx(struct uart_port *port)
257 {
258 struct imx_port *sport = (struct imx_port *)port;
259 unsigned long temp;
260
261 temp = readl(sport->port.membase + UCR2);
262 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
263 }
264
265 /*
266 * Set the modem control timer to fire immediately.
267 */
268 static void imx_enable_ms(struct uart_port *port)
269 {
270 struct imx_port *sport = (struct imx_port *)port;
271
272 mod_timer(&sport->timer, jiffies);
273 }
274
275 static inline void imx_transmit_buffer(struct imx_port *sport)
276 {
277 struct circ_buf *xmit = &sport->port.info->xmit;
278
279 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
280 /* send xmit->buf[xmit->tail]
281 * out the port here */
282 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
283 xmit->tail = (xmit->tail + 1) &
284 (UART_XMIT_SIZE - 1);
285 sport->port.icount.tx++;
286 if (uart_circ_empty(xmit))
287 break;
288 }
289
290 if (uart_circ_empty(xmit))
291 imx_stop_tx(&sport->port);
292 }
293
294 /*
295 * interrupts disabled on entry
296 */
297 static void imx_start_tx(struct uart_port *port)
298 {
299 struct imx_port *sport = (struct imx_port *)port;
300 unsigned long temp;
301
302 temp = readl(sport->port.membase + UCR1);
303 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
304
305 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
306 imx_transmit_buffer(sport);
307 }
308
309 static irqreturn_t imx_rtsint(int irq, void *dev_id)
310 {
311 struct imx_port *sport = dev_id;
312 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
313 unsigned long flags;
314
315 spin_lock_irqsave(&sport->port.lock, flags);
316
317 writel(USR1_RTSD, sport->port.membase + USR1);
318 uart_handle_cts_change(&sport->port, !!val);
319 wake_up_interruptible(&sport->port.info->delta_msr_wait);
320
321 spin_unlock_irqrestore(&sport->port.lock, flags);
322 return IRQ_HANDLED;
323 }
324
325 static irqreturn_t imx_txint(int irq, void *dev_id)
326 {
327 struct imx_port *sport = dev_id;
328 struct circ_buf *xmit = &sport->port.info->xmit;
329 unsigned long flags;
330
331 spin_lock_irqsave(&sport->port.lock,flags);
332 if (sport->port.x_char)
333 {
334 /* Send next char */
335 writel(sport->port.x_char, sport->port.membase + URTX0);
336 goto out;
337 }
338
339 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
340 imx_stop_tx(&sport->port);
341 goto out;
342 }
343
344 imx_transmit_buffer(sport);
345
346 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
347 uart_write_wakeup(&sport->port);
348
349 out:
350 spin_unlock_irqrestore(&sport->port.lock,flags);
351 return IRQ_HANDLED;
352 }
353
354 static irqreturn_t imx_rxint(int irq, void *dev_id)
355 {
356 struct imx_port *sport = dev_id;
357 unsigned int rx,flg,ignored = 0;
358 struct tty_struct *tty = sport->port.info->tty;
359 unsigned long flags, temp;
360
361 rx = readl(sport->port.membase + URXD0);
362 spin_lock_irqsave(&sport->port.lock,flags);
363
364 do {
365 flg = TTY_NORMAL;
366 sport->port.icount.rx++;
367
368 temp = readl(sport->port.membase + USR2);
369 if( temp & USR2_BRCD ) {
370 writel(temp | USR2_BRCD, sport->port.membase + USR2);
371 if(uart_handle_break(&sport->port))
372 goto ignore_char;
373 }
374
375 if (uart_handle_sysrq_char
376 (&sport->port, (unsigned char)rx))
377 goto ignore_char;
378
379 if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) )
380 goto handle_error;
381
382 error_return:
383 tty_insert_flip_char(tty, rx, flg);
384
385 ignore_char:
386 rx = readl(sport->port.membase + URXD0);
387 } while(rx & URXD_CHARRDY);
388
389 out:
390 spin_unlock_irqrestore(&sport->port.lock,flags);
391 tty_flip_buffer_push(tty);
392 return IRQ_HANDLED;
393
394 handle_error:
395 if (rx & URXD_PRERR)
396 sport->port.icount.parity++;
397 else if (rx & URXD_FRMERR)
398 sport->port.icount.frame++;
399 if (rx & URXD_OVRRUN)
400 sport->port.icount.overrun++;
401
402 if (rx & sport->port.ignore_status_mask) {
403 if (++ignored > 100)
404 goto out;
405 goto ignore_char;
406 }
407
408 rx &= sport->port.read_status_mask;
409
410 if (rx & URXD_PRERR)
411 flg = TTY_PARITY;
412 else if (rx & URXD_FRMERR)
413 flg = TTY_FRAME;
414 if (rx & URXD_OVRRUN)
415 flg = TTY_OVERRUN;
416
417 #ifdef SUPPORT_SYSRQ
418 sport->port.sysrq = 0;
419 #endif
420 goto error_return;
421 }
422
423 /*
424 * Return TIOCSER_TEMT when transmitter is not busy.
425 */
426 static unsigned int imx_tx_empty(struct uart_port *port)
427 {
428 struct imx_port *sport = (struct imx_port *)port;
429
430 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
431 }
432
433 /*
434 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
435 */
436 static unsigned int imx_get_mctrl(struct uart_port *port)
437 {
438 struct imx_port *sport = (struct imx_port *)port;
439 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
440
441 if (readl(sport->port.membase + USR1) & USR1_RTSS)
442 tmp |= TIOCM_CTS;
443
444 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
445 tmp |= TIOCM_RTS;
446
447 return tmp;
448 }
449
450 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
451 {
452 struct imx_port *sport = (struct imx_port *)port;
453 unsigned long temp;
454
455 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
456
457 if (mctrl & TIOCM_RTS)
458 temp |= UCR2_CTS;
459
460 writel(temp, sport->port.membase + UCR2);
461 }
462
463 /*
464 * Interrupts always disabled.
465 */
466 static void imx_break_ctl(struct uart_port *port, int break_state)
467 {
468 struct imx_port *sport = (struct imx_port *)port;
469 unsigned long flags, temp;
470
471 spin_lock_irqsave(&sport->port.lock, flags);
472
473 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
474
475 if ( break_state != 0 )
476 temp |= UCR1_SNDBRK;
477
478 writel(temp, sport->port.membase + UCR1);
479
480 spin_unlock_irqrestore(&sport->port.lock, flags);
481 }
482
483 #define TXTL 2 /* reset default */
484 #define RXTL 1 /* reset default */
485
486 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
487 {
488 unsigned int val;
489 unsigned int ufcr_rfdiv;
490
491 /* set receiver / transmitter trigger level.
492 * RFDIV is set such way to satisfy requested uartclk value
493 */
494 val = TXTL << 10 | RXTL;
495 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
496
497 if(!ufcr_rfdiv)
498 ufcr_rfdiv = 1;
499
500 if(ufcr_rfdiv >= 7)
501 ufcr_rfdiv = 6;
502 else
503 ufcr_rfdiv = 6 - ufcr_rfdiv;
504
505 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
506
507 writel(val, sport->port.membase + UFCR);
508
509 return 0;
510 }
511
512 static int imx_startup(struct uart_port *port)
513 {
514 struct imx_port *sport = (struct imx_port *)port;
515 int retval;
516 unsigned long flags, temp;
517
518 imx_setup_ufcr(sport, 0);
519
520 /* disable the DREN bit (Data Ready interrupt enable) before
521 * requesting IRQs
522 */
523 temp = readl(sport->port.membase + UCR4);
524 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
525
526 /*
527 * Allocate the IRQ
528 */
529 retval = request_irq(sport->rxirq, imx_rxint, 0,
530 DRIVER_NAME, sport);
531 if (retval) goto error_out1;
532
533 retval = request_irq(sport->txirq, imx_txint, 0,
534 DRIVER_NAME, sport);
535 if (retval) goto error_out2;
536
537 retval = request_irq(sport->rtsirq, imx_rtsint,
538 (sport->rtsirq < IMX_IRQS) ? 0 :
539 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
540 DRIVER_NAME, sport);
541 if (retval) goto error_out3;
542
543 /*
544 * Finally, clear and enable interrupts
545 */
546 writel(USR1_RTSD, sport->port.membase + USR1);
547
548 temp = readl(sport->port.membase + UCR1);
549 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
550 writel(temp, sport->port.membase + UCR1);
551
552 temp = readl(sport->port.membase + UCR2);
553 temp |= (UCR2_RXEN | UCR2_TXEN);
554 writel(temp, sport->port.membase + UCR2);
555
556 /*
557 * Enable modem status interrupts
558 */
559 spin_lock_irqsave(&sport->port.lock,flags);
560 imx_enable_ms(&sport->port);
561 spin_unlock_irqrestore(&sport->port.lock,flags);
562
563 return 0;
564
565 error_out3:
566 free_irq(sport->txirq, sport);
567 error_out2:
568 free_irq(sport->rxirq, sport);
569 error_out1:
570 return retval;
571 }
572
573 static void imx_shutdown(struct uart_port *port)
574 {
575 struct imx_port *sport = (struct imx_port *)port;
576 unsigned long temp;
577
578 /*
579 * Stop our timer.
580 */
581 del_timer_sync(&sport->timer);
582
583 /*
584 * Free the interrupts
585 */
586 free_irq(sport->rtsirq, sport);
587 free_irq(sport->txirq, sport);
588 free_irq(sport->rxirq, sport);
589
590 /*
591 * Disable all interrupts, port and break condition.
592 */
593
594 temp = readl(sport->port.membase + UCR1);
595 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
596 writel(temp, sport->port.membase + UCR1);
597 }
598
599 static void
600 imx_set_termios(struct uart_port *port, struct ktermios *termios,
601 struct ktermios *old)
602 {
603 struct imx_port *sport = (struct imx_port *)port;
604 unsigned long flags;
605 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
606 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
607
608 /*
609 * If we don't support modem control lines, don't allow
610 * these to be set.
611 */
612 if (0) {
613 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
614 termios->c_cflag |= CLOCAL;
615 }
616
617 /*
618 * We only support CS7 and CS8.
619 */
620 while ((termios->c_cflag & CSIZE) != CS7 &&
621 (termios->c_cflag & CSIZE) != CS8) {
622 termios->c_cflag &= ~CSIZE;
623 termios->c_cflag |= old_csize;
624 old_csize = CS8;
625 }
626
627 if ((termios->c_cflag & CSIZE) == CS8)
628 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
629 else
630 ucr2 = UCR2_SRST | UCR2_IRTS;
631
632 if (termios->c_cflag & CRTSCTS) {
633 if( sport->have_rtscts ) {
634 ucr2 &= ~UCR2_IRTS;
635 ucr2 |= UCR2_CTSC;
636 } else {
637 termios->c_cflag &= ~CRTSCTS;
638 }
639 }
640
641 if (termios->c_cflag & CSTOPB)
642 ucr2 |= UCR2_STPB;
643 if (termios->c_cflag & PARENB) {
644 ucr2 |= UCR2_PREN;
645 if (termios->c_cflag & PARODD)
646 ucr2 |= UCR2_PROE;
647 }
648
649 /*
650 * Ask the core to calculate the divisor for us.
651 */
652 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
653 quot = uart_get_divisor(port, baud);
654
655 spin_lock_irqsave(&sport->port.lock, flags);
656
657 sport->port.read_status_mask = 0;
658 if (termios->c_iflag & INPCK)
659 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
660 if (termios->c_iflag & (BRKINT | PARMRK))
661 sport->port.read_status_mask |= URXD_BRK;
662
663 /*
664 * Characters to ignore
665 */
666 sport->port.ignore_status_mask = 0;
667 if (termios->c_iflag & IGNPAR)
668 sport->port.ignore_status_mask |= URXD_PRERR;
669 if (termios->c_iflag & IGNBRK) {
670 sport->port.ignore_status_mask |= URXD_BRK;
671 /*
672 * If we're ignoring parity and break indicators,
673 * ignore overruns too (for real raw support).
674 */
675 if (termios->c_iflag & IGNPAR)
676 sport->port.ignore_status_mask |= URXD_OVRRUN;
677 }
678
679 del_timer_sync(&sport->timer);
680
681 /*
682 * Update the per-port timeout.
683 */
684 uart_update_timeout(port, termios->c_cflag, baud);
685
686 /*
687 * disable interrupts and drain transmitter
688 */
689 old_ucr1 = readl(sport->port.membase + UCR1);
690 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
691 sport->port.membase + UCR1);
692
693 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
694 barrier();
695
696 /* then, disable everything */
697 old_txrxen = readl(sport->port.membase + UCR2);
698 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
699 sport->port.membase + UCR2);
700 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
701
702 /* set the baud rate. We assume uartclk = 16 MHz
703 *
704 * baud * 16 UBIR - 1
705 * --------- = --------
706 * uartclk UBMR - 1
707 */
708 writel((baud / 100) - 1, sport->port.membase + UBIR);
709 writel(10000 - 1, sport->port.membase + UBMR);
710
711 writel(old_ucr1, sport->port.membase + UCR1);
712
713 /* set the parity, stop bits and data size */
714 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
715
716 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
717 imx_enable_ms(&sport->port);
718
719 spin_unlock_irqrestore(&sport->port.lock, flags);
720 }
721
722 static const char *imx_type(struct uart_port *port)
723 {
724 struct imx_port *sport = (struct imx_port *)port;
725
726 return sport->port.type == PORT_IMX ? "IMX" : NULL;
727 }
728
729 /*
730 * Release the memory region(s) being used by 'port'.
731 */
732 static void imx_release_port(struct uart_port *port)
733 {
734 struct imx_port *sport = (struct imx_port *)port;
735
736 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
737 }
738
739 /*
740 * Request the memory region(s) being used by 'port'.
741 */
742 static int imx_request_port(struct uart_port *port)
743 {
744 struct imx_port *sport = (struct imx_port *)port;
745
746 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
747 "imx-uart") != NULL ? 0 : -EBUSY;
748 }
749
750 /*
751 * Configure/autoconfigure the port.
752 */
753 static void imx_config_port(struct uart_port *port, int flags)
754 {
755 struct imx_port *sport = (struct imx_port *)port;
756
757 if (flags & UART_CONFIG_TYPE &&
758 imx_request_port(&sport->port) == 0)
759 sport->port.type = PORT_IMX;
760 }
761
762 /*
763 * Verify the new serial_struct (for TIOCSSERIAL).
764 * The only change we allow are to the flags and type, and
765 * even then only between PORT_IMX and PORT_UNKNOWN
766 */
767 static int
768 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
769 {
770 struct imx_port *sport = (struct imx_port *)port;
771 int ret = 0;
772
773 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
774 ret = -EINVAL;
775 if (sport->port.irq != ser->irq)
776 ret = -EINVAL;
777 if (ser->io_type != UPIO_MEM)
778 ret = -EINVAL;
779 if (sport->port.uartclk / 16 != ser->baud_base)
780 ret = -EINVAL;
781 if ((void *)sport->port.mapbase != ser->iomem_base)
782 ret = -EINVAL;
783 if (sport->port.iobase != ser->port)
784 ret = -EINVAL;
785 if (ser->hub6 != 0)
786 ret = -EINVAL;
787 return ret;
788 }
789
790 static struct uart_ops imx_pops = {
791 .tx_empty = imx_tx_empty,
792 .set_mctrl = imx_set_mctrl,
793 .get_mctrl = imx_get_mctrl,
794 .stop_tx = imx_stop_tx,
795 .start_tx = imx_start_tx,
796 .stop_rx = imx_stop_rx,
797 .enable_ms = imx_enable_ms,
798 .break_ctl = imx_break_ctl,
799 .startup = imx_startup,
800 .shutdown = imx_shutdown,
801 .set_termios = imx_set_termios,
802 .type = imx_type,
803 .release_port = imx_release_port,
804 .request_port = imx_request_port,
805 .config_port = imx_config_port,
806 .verify_port = imx_verify_port,
807 };
808
809 static struct imx_port imx_ports[] = {
810 {
811 .txirq = UART1_MINT_TX,
812 .rxirq = UART1_MINT_RX,
813 .rtsirq = UART1_MINT_RTS,
814 .port = {
815 .type = PORT_IMX,
816 .iotype = UPIO_MEM,
817 .membase = (void *)IMX_UART1_BASE,
818 .mapbase = IMX_UART1_BASE, /* FIXME */
819 .irq = UART1_MINT_RX,
820 .uartclk = 16000000,
821 .fifosize = 32,
822 .flags = UPF_BOOT_AUTOCONF,
823 .ops = &imx_pops,
824 .line = 0,
825 },
826 }, {
827 .txirq = UART2_MINT_TX,
828 .rxirq = UART2_MINT_RX,
829 .rtsirq = UART2_MINT_RTS,
830 .port = {
831 .type = PORT_IMX,
832 .iotype = UPIO_MEM,
833 .membase = (void *)IMX_UART2_BASE,
834 .mapbase = IMX_UART2_BASE, /* FIXME */
835 .irq = UART2_MINT_RX,
836 .uartclk = 16000000,
837 .fifosize = 32,
838 .flags = UPF_BOOT_AUTOCONF,
839 .ops = &imx_pops,
840 .line = 1,
841 },
842 }
843 };
844
845 /*
846 * Setup the IMX serial ports.
847 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
848 * Which serial port this ends up being depends on the machine you're
849 * running this kernel on. I'm not convinced that this is a good idea,
850 * but that's the way it traditionally works.
851 *
852 */
853 static void __init imx_init_ports(void)
854 {
855 static int first = 1;
856 int i;
857
858 if (!first)
859 return;
860 first = 0;
861
862 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
863 init_timer(&imx_ports[i].timer);
864 imx_ports[i].timer.function = imx_timeout;
865 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
866 }
867 }
868
869 #ifdef CONFIG_SERIAL_IMX_CONSOLE
870 static void imx_console_putchar(struct uart_port *port, int ch)
871 {
872 struct imx_port *sport = (struct imx_port *)port;
873
874 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
875 barrier();
876
877 writel(ch, sport->port.membase + URTX0);
878 }
879
880 /*
881 * Interrupts are disabled on entering
882 */
883 static void
884 imx_console_write(struct console *co, const char *s, unsigned int count)
885 {
886 struct imx_port *sport = &imx_ports[co->index];
887 unsigned int old_ucr1, old_ucr2;
888
889 /*
890 * First, save UCR1/2 and then disable interrupts
891 */
892 old_ucr1 = readl(sport->port.membase + UCR1);
893 old_ucr2 = readl(sport->port.membase + UCR2);
894
895 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
896 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
897 sport->port.membase + UCR1);
898
899 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
900
901 uart_console_write(&sport->port, s, count, imx_console_putchar);
902
903 /*
904 * Finally, wait for transmitter to become empty
905 * and restore UCR1/2
906 */
907 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
908
909 writel(old_ucr1, sport->port.membase + UCR1);
910 writel(old_ucr2, sport->port.membase + UCR2);
911 }
912
913 /*
914 * If the port was already initialised (eg, by a boot loader),
915 * try to determine the current setup.
916 */
917 static void __init
918 imx_console_get_options(struct imx_port *sport, int *baud,
919 int *parity, int *bits)
920 {
921
922 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
923 /* ok, the port was enabled */
924 unsigned int ucr2, ubir,ubmr, uartclk;
925 unsigned int baud_raw;
926 unsigned int ucfr_rfdiv;
927
928 ucr2 = readl(sport->port.membase + UCR2);
929
930 *parity = 'n';
931 if (ucr2 & UCR2_PREN) {
932 if (ucr2 & UCR2_PROE)
933 *parity = 'o';
934 else
935 *parity = 'e';
936 }
937
938 if (ucr2 & UCR2_WS)
939 *bits = 8;
940 else
941 *bits = 7;
942
943 ubir = readl(sport->port.membase + UBIR) & 0xffff;
944 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
945
946 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
947 if (ucfr_rfdiv == 6)
948 ucfr_rfdiv = 7;
949 else
950 ucfr_rfdiv = 6 - ucfr_rfdiv;
951
952 uartclk = imx_get_perclk1();
953 uartclk /= ucfr_rfdiv;
954
955 { /*
956 * The next code provides exact computation of
957 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
958 * without need of float support or long long division,
959 * which would be required to prevent 32bit arithmetic overflow
960 */
961 unsigned int mul = ubir + 1;
962 unsigned int div = 16 * (ubmr + 1);
963 unsigned int rem = uartclk % div;
964
965 baud_raw = (uartclk / div) * mul;
966 baud_raw += (rem * mul + div / 2) / div;
967 *baud = (baud_raw + 50) / 100 * 100;
968 }
969
970 if(*baud != baud_raw)
971 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
972 baud_raw, *baud);
973 }
974 }
975
976 static int __init
977 imx_console_setup(struct console *co, char *options)
978 {
979 struct imx_port *sport;
980 int baud = 9600;
981 int bits = 8;
982 int parity = 'n';
983 int flow = 'n';
984
985 /*
986 * Check whether an invalid uart number has been specified, and
987 * if so, search for the first available port that does have
988 * console support.
989 */
990 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
991 co->index = 0;
992 sport = &imx_ports[co->index];
993
994 if (options)
995 uart_parse_options(options, &baud, &parity, &bits, &flow);
996 else
997 imx_console_get_options(sport, &baud, &parity, &bits);
998
999 imx_setup_ufcr(sport, 0);
1000
1001 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1002 }
1003
1004 static struct uart_driver imx_reg;
1005 static struct console imx_console = {
1006 .name = "ttySMX",
1007 .write = imx_console_write,
1008 .device = uart_console_device,
1009 .setup = imx_console_setup,
1010 .flags = CON_PRINTBUFFER,
1011 .index = -1,
1012 .data = &imx_reg,
1013 };
1014
1015 static int __init imx_rs_console_init(void)
1016 {
1017 imx_init_ports();
1018 register_console(&imx_console);
1019 return 0;
1020 }
1021 console_initcall(imx_rs_console_init);
1022
1023 #define IMX_CONSOLE &imx_console
1024 #else
1025 #define IMX_CONSOLE NULL
1026 #endif
1027
1028 static struct uart_driver imx_reg = {
1029 .owner = THIS_MODULE,
1030 .driver_name = DRIVER_NAME,
1031 .dev_name = "ttySMX",
1032 .major = SERIAL_IMX_MAJOR,
1033 .minor = MINOR_START,
1034 .nr = ARRAY_SIZE(imx_ports),
1035 .cons = IMX_CONSOLE,
1036 };
1037
1038 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1039 {
1040 struct imx_port *sport = platform_get_drvdata(dev);
1041
1042 if (sport)
1043 uart_suspend_port(&imx_reg, &sport->port);
1044
1045 return 0;
1046 }
1047
1048 static int serial_imx_resume(struct platform_device *dev)
1049 {
1050 struct imx_port *sport = platform_get_drvdata(dev);
1051
1052 if (sport)
1053 uart_resume_port(&imx_reg, &sport->port);
1054
1055 return 0;
1056 }
1057
1058 static int serial_imx_probe(struct platform_device *dev)
1059 {
1060 struct imxuart_platform_data *pdata;
1061
1062 imx_ports[dev->id].port.dev = &dev->dev;
1063
1064 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1065 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1066 imx_ports[dev->id].have_rtscts = 1;
1067
1068 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
1069 platform_set_drvdata(dev, &imx_ports[dev->id]);
1070 return 0;
1071 }
1072
1073 static int serial_imx_remove(struct platform_device *dev)
1074 {
1075 struct imx_port *sport = platform_get_drvdata(dev);
1076
1077 platform_set_drvdata(dev, NULL);
1078
1079 if (sport)
1080 uart_remove_one_port(&imx_reg, &sport->port);
1081
1082 return 0;
1083 }
1084
1085 static struct platform_driver serial_imx_driver = {
1086 .probe = serial_imx_probe,
1087 .remove = serial_imx_remove,
1088
1089 .suspend = serial_imx_suspend,
1090 .resume = serial_imx_resume,
1091 .driver = {
1092 .name = "imx-uart",
1093 },
1094 };
1095
1096 static int __init imx_serial_init(void)
1097 {
1098 int ret;
1099
1100 printk(KERN_INFO "Serial: IMX driver\n");
1101
1102 imx_init_ports();
1103
1104 ret = uart_register_driver(&imx_reg);
1105 if (ret)
1106 return ret;
1107
1108 ret = platform_driver_register(&serial_imx_driver);
1109 if (ret != 0)
1110 uart_unregister_driver(&imx_reg);
1111
1112 return 0;
1113 }
1114
1115 static void __exit imx_serial_exit(void)
1116 {
1117 platform_driver_unregister(&serial_imx_driver);
1118 uart_unregister_driver(&imx_reg);
1119 }
1120
1121 module_init(imx_serial_init);
1122 module_exit(imx_serial_exit);
1123
1124 MODULE_AUTHOR("Sascha Hauer");
1125 MODULE_DESCRIPTION("IMX generic serial port driver");
1126 MODULE_LICENSE("GPL");
WRT350N Kernel Patches