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Initial commit
[wrt350n-kernel.git] / drivers / spi / spi_s3c24xx.c
blob6e834b8b9d2785f51427cd11d3a051e9e9471b03
1 /* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
22
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_bitbang.h>
25
26 #include <asm/io.h>
27 #include <asm/dma.h>
28 #include <asm/hardware.h>
29
30 #include <asm/arch/regs-gpio.h>
31 #include <asm/plat-s3c24xx/regs-spi.h>
32 #include <asm/arch/spi.h>
33
34 struct s3c24xx_spi {
35 /* bitbang has to be first */
36 struct spi_bitbang bitbang;
37 struct completion done;
38
39 void __iomem *regs;
40 int irq;
41 int len;
42 int count;
43
44 void (*set_cs)(struct s3c2410_spi_info *spi,
45 int cs, int pol);
46
47 /* data buffers */
48 const unsigned char *tx;
49 unsigned char *rx;
50
51 struct clk *clk;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
55 struct device *dev;
56 struct s3c2410_spi_info *pdata;
57 };
58
59 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
61
62 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
63 {
64 return spi_master_get_devdata(sdev->master);
65 }
66
67 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
68 {
69 s3c2410_gpio_setpin(spi->pin_cs, pol);
70 }
71
72 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
73 {
74 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int spcon;
77
78 switch (value) {
79 case BITBANG_CS_INACTIVE:
80 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
81 break;
82
83 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON);
85
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
88 else
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
90
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
93 else
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
95
96 spcon |= S3C2410_SPCON_ENSCK;
97
98 /* write new configration */
99
100 writeb(spcon, hw->regs + S3C2410_SPCON);
101 hw->set_cs(hw->pdata, spi->chip_select, cspol);
102
103 break;
104 }
105 }
106
107 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
108 struct spi_transfer *t)
109 {
110 struct s3c24xx_spi *hw = to_hw(spi);
111 unsigned int bpw;
112 unsigned int hz;
113 unsigned int div;
114
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
117
118 if (bpw != 8) {
119 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
120 return -EINVAL;
121 }
122
123 div = clk_get_rate(hw->clk) / hz;
124
125 /* is clk = pclk / (2 * (pre+1)), or is it
126 * clk = (pclk * 2) / ( pre + 1) */
127
128 div = (div / 2) - 1;
129
130 if (div < 0)
131 div = 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
137 writeb(div, hw->regs + S3C2410_SPPRE);
138
139 spin_lock(&hw->bitbang.lock);
140 if (!hw->bitbang.busy) {
141 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
142 /* need to ndelay for 0.5 clocktick ? */
143 }
144 spin_unlock(&hw->bitbang.lock);
145
146 return 0;
147 }
148
149 /* the spi->mode bits understood by this driver: */
150 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
151
152 static int s3c24xx_spi_setup(struct spi_device *spi)
153 {
154 int ret;
155
156 if (!spi->bits_per_word)
157 spi->bits_per_word = 8;
158
159 if (spi->mode & ~MODEBITS) {
160 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
161 spi->mode & ~MODEBITS);
162 return -EINVAL;
163 }
164
165 ret = s3c24xx_spi_setupxfer(spi, NULL);
166 if (ret < 0) {
167 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
168 return ret;
169 }
170
171 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
172 __FUNCTION__, spi->mode, spi->bits_per_word,
173 spi->max_speed_hz);
174
175 return 0;
176 }
177
178 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
179 {
180 return hw->tx ? hw->tx[count] : 0;
181 }
182
183 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
184 {
185 struct s3c24xx_spi *hw = to_hw(spi);
186
187 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
188 t->tx_buf, t->rx_buf, t->len);
189
190 hw->tx = t->tx_buf;
191 hw->rx = t->rx_buf;
192 hw->len = t->len;
193 hw->count = 0;
194
195 /* send the first byte */
196 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
197 wait_for_completion(&hw->done);
198
199 return hw->count;
200 }
201
202 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
203 {
204 struct s3c24xx_spi *hw = dev;
205 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
206 unsigned int count = hw->count;
207
208 if (spsta & S3C2410_SPSTA_DCOL) {
209 dev_dbg(hw->dev, "data-collision\n");
210 complete(&hw->done);
211 goto irq_done;
212 }
213
214 if (!(spsta & S3C2410_SPSTA_READY)) {
215 dev_dbg(hw->dev, "spi not ready for tx?\n");
216 complete(&hw->done);
217 goto irq_done;
218 }
219
220 hw->count++;
221
222 if (hw->rx)
223 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
224
225 count++;
226
227 if (count < hw->len)
228 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
229 else
230 complete(&hw->done);
231
232 irq_done:
233 return IRQ_HANDLED;
234 }
235
236 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
237 {
238 struct s3c24xx_spi *hw;
239 struct spi_master *master;
240 struct resource *res;
241 int err = 0;
242
243 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
244 if (master == NULL) {
245 dev_err(&pdev->dev, "No memory for spi_master\n");
246 err = -ENOMEM;
247 goto err_nomem;
248 }
249
250 hw = spi_master_get_devdata(master);
251 memset(hw, 0, sizeof(struct s3c24xx_spi));
252
253 hw->master = spi_master_get(master);
254 hw->pdata = pdev->dev.platform_data;
255 hw->dev = &pdev->dev;
256
257 if (hw->pdata == NULL) {
258 dev_err(&pdev->dev, "No platform data supplied\n");
259 err = -ENOENT;
260 goto err_no_pdata;
261 }
262
263 platform_set_drvdata(pdev, hw);
264 init_completion(&hw->done);
265
266 /* setup the state for the bitbang driver */
267
268 hw->bitbang.master = hw->master;
269 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
270 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
271 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
272 hw->bitbang.master->setup = s3c24xx_spi_setup;
273
274 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
275
276 /* find and map our resources */
277
278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 if (res == NULL) {
280 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
281 err = -ENOENT;
282 goto err_no_iores;
283 }
284
285 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
286 pdev->name);
287
288 if (hw->ioarea == NULL) {
289 dev_err(&pdev->dev, "Cannot reserve region\n");
290 err = -ENXIO;
291 goto err_no_iores;
292 }
293
294 hw->regs = ioremap(res->start, (res->end - res->start)+1);
295 if (hw->regs == NULL) {
296 dev_err(&pdev->dev, "Cannot map IO\n");
297 err = -ENXIO;
298 goto err_no_iomap;
299 }
300
301 hw->irq = platform_get_irq(pdev, 0);
302 if (hw->irq < 0) {
303 dev_err(&pdev->dev, "No IRQ specified\n");
304 err = -ENOENT;
305 goto err_no_irq;
306 }
307
308 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
309 if (err) {
310 dev_err(&pdev->dev, "Cannot claim IRQ\n");
311 goto err_no_irq;
312 }
313
314 hw->clk = clk_get(&pdev->dev, "spi");
315 if (IS_ERR(hw->clk)) {
316 dev_err(&pdev->dev, "No clock for device\n");
317 err = PTR_ERR(hw->clk);
318 goto err_no_clk;
319 }
320
321 /* for the moment, permanently enable the clock */
322
323 clk_enable(hw->clk);
324
325 /* program defaults into the registers */
326
327 writeb(0xff, hw->regs + S3C2410_SPPRE);
328 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
329 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
330
331 /* setup any gpio we can */
332
333 if (!hw->pdata->set_cs) {
334 hw->set_cs = s3c24xx_spi_gpiocs;
335
336 s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
337 s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
338 } else
339 hw->set_cs = hw->pdata->set_cs;
340
341 /* register our spi controller */
342
343 err = spi_bitbang_start(&hw->bitbang);
344 if (err) {
345 dev_err(&pdev->dev, "Failed to register SPI master\n");
346 goto err_register;
347 }
348
349 return 0;
350
351 err_register:
352 clk_disable(hw->clk);
353 clk_put(hw->clk);
354
355 err_no_clk:
356 free_irq(hw->irq, hw);
357
358 err_no_irq:
359 iounmap(hw->regs);
360
361 err_no_iomap:
362 release_resource(hw->ioarea);
363 kfree(hw->ioarea);
364
365 err_no_iores:
366 err_no_pdata:
367 spi_master_put(hw->master);;
368
369 err_nomem:
370 return err;
371 }
372
373 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
374 {
375 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
376
377 platform_set_drvdata(dev, NULL);
378
379 spi_unregister_master(hw->master);
380
381 clk_disable(hw->clk);
382 clk_put(hw->clk);
383
384 free_irq(hw->irq, hw);
385 iounmap(hw->regs);
386
387 release_resource(hw->ioarea);
388 kfree(hw->ioarea);
389
390 spi_master_put(hw->master);
391 return 0;
392 }
393
394
395 #ifdef CONFIG_PM
396
397 static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
398 {
399 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
400
401 clk_disable(hw->clk);
402 return 0;
403 }
404
405 static int s3c24xx_spi_resume(struct platform_device *pdev)
406 {
407 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
408
409 clk_enable(hw->clk);
410 return 0;
411 }
412
413 #else
414 #define s3c24xx_spi_suspend NULL
415 #define s3c24xx_spi_resume NULL
416 #endif
417
418 MODULE_ALIAS("s3c2410_spi"); /* for platform bus hotplug */
419 static struct platform_driver s3c24xx_spidrv = {
420 .remove = __exit_p(s3c24xx_spi_remove),
421 .suspend = s3c24xx_spi_suspend,
422 .resume = s3c24xx_spi_resume,
423 .driver = {
424 .name = "s3c2410-spi",
425 .owner = THIS_MODULE,
426 },
427 };
428
429 static int __init s3c24xx_spi_init(void)
430 {
431 return platform_driver_probe(&s3c24xx_spidrv, s3c24xx_spi_probe);
432 }
433
434 static void __exit s3c24xx_spi_exit(void)
435 {
436 platform_driver_unregister(&s3c24xx_spidrv);
437 }
438
439 module_init(s3c24xx_spi_init);
440 module_exit(s3c24xx_spi_exit);
441
442 MODULE_DESCRIPTION("S3C24XX SPI Driver");
443 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
444 MODULE_LICENSE("GPL");
WRT350N Kernel Patches