Initial commit
[wrt350n-kernel.git] / include / asm-mips / mach-pnx8550 / cm.h
blobbb0a56c7d0118fc408f337a7baa59588d79b26c7
1 /*
3 * BRIEF MODULE DESCRIPTION
4 * Clock module specific definitions
6 * Author: source@mvista.com
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 #ifndef __PNX8550_CM_H
23 #define __PNX8550_CM_H
25 #define PNX8550_CM_BASE 0xBBE47000
27 #define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
28 #define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
29 #define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
30 #define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
32 // Table not complete.....
34 #define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
35 #define PNX8550_CM_PLL_LOCK_MASK 0x40000000
36 #define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
37 #define PNX8550_CM_PLL_N_MASK 0x01ff0000
38 #define PNX8550_CM_PLL_M_MASK 0x00003f00
39 #define PNX8550_CM_PLL_P_MASK 0x0000000c
40 #define PNX8550_CM_PLL_PD_MASK 0x00000002
43 #endif