include/asm-powerpc/ptrace.h

   1 #ifndef _ASM_POWERPC_PTRACE_H
   2 #define _ASM_POWERPC_PTRACE_H
   3
   4 /*
   5  * Copyright (C) 2001 PPC64 Team, IBM Corp
   6  *
   7  * This struct defines the way the registers are stored on the
   8  * kernel stack during a system call or other kernel entry.
   9  *
  10  * this should only contain volatile regs
  11  * since we can keep non-volatile in the thread_struct
  12  * should set this up when only volatiles are saved
  13  * by intr code.
  14  *
  15  * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
  16  * that the overall structure is a multiple of 16 bytes in length.
  17  *
  18  * Note that the offsets of the fields in this struct correspond with
  19  * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License
  23  * as published by the Free Software Foundation; either version
  24  * 2 of the License, or (at your option) any later version.
  25  */
  26
  27 #ifndef __ASSEMBLY__
  28
  29 struct pt_regs {
  30         unsigned long gpr[32];
  31         unsigned long nip;
  32         unsigned long msr;
  33         unsigned long orig_gpr3;        /* Used for restarting system calls */
  34         unsigned long ctr;
  35         unsigned long link;
  36         unsigned long xer;
  37         unsigned long ccr;
  38 #ifdef __powerpc64__
  39         unsigned long softe;            /* Soft enabled/disabled */
  40 #else
  41         unsigned long mq;               /* 601 only (not used at present) */
  42                                         /* Used on APUS to hold IPL value. */
  43 #endif
  44         unsigned long trap;             /* Reason for being here */
  45         /* N.B. for critical exceptions on 4xx, the dar and dsisr
  46            fields are overloaded to hold srr0 and srr1. */
  47         unsigned long dar;              /* Fault registers */
  48         unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
  49         unsigned long result;           /* Result of a system call */
  50 };
  51
  52 #endif /* __ASSEMBLY__ */
  53
  54 #ifdef __KERNEL__
  55
  56 #ifdef __powerpc64__
  57
  58 #define __ARCH_WANT_COMPAT_SYS_PTRACE
  59
  60 #define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
  61
  62 /* Size of dummy stack frame allocated when calling signal handler. */
  63 #define __SIGNAL_FRAMESIZE      128
  64 #define __SIGNAL_FRAMESIZE32    64
  65
  66 #else /* __powerpc64__ */
  67
  68 #define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
  69
  70 /* Size of stack frame allocated when calling signal handler. */
  71 #define __SIGNAL_FRAMESIZE      64
  72
  73 #endif /* __powerpc64__ */
  74
  75 #ifndef __ASSEMBLY__
  76
  77 #define instruction_pointer(regs) ((regs)->nip)
  78 #define regs_return_value(regs) ((regs)->gpr[3])
  79
  80 #ifdef CONFIG_SMP
  81 extern unsigned long profile_pc(struct pt_regs *regs);
  82 #else
  83 #define profile_pc(regs) instruction_pointer(regs)
  84 #endif
  85
  86 #ifdef __powerpc64__
  87 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
  88 #else
  89 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
  90 #endif
  91
  92 #define force_successful_syscall_return()   \
  93         do { \
  94                 set_thread_flag(TIF_NOERROR); \
  95         } while(0)
  96
  97 struct task_struct;
  98 extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
  99 extern int ptrace_put_reg(struct task_struct *task, int regno,
 100                           unsigned long data);
 101
 102 /*
 103  * We use the least-significant bit of the trap field to indicate
 104  * whether we have saved the full set of registers, or only a
 105  * partial set.  A 1 there means the partial set.
 106  * On 4xx we use the next bit to indicate whether the exception
 107  * is a critical exception (1 means it is).
 108  */
 109 #define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
 110 #ifndef __powerpc64__
 111 #define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) != 0)
 112 #define IS_MCHECK_EXC(regs)     (((regs)->trap & 4) != 0)
 113 #endif /* ! __powerpc64__ */
 114 #define TRAP(regs)              ((regs)->trap & ~0xF)
 115 #ifdef __powerpc64__
 116 #define CHECK_FULL_REGS(regs)   BUG_ON(regs->trap & 1)
 117 #else
 118 #define CHECK_FULL_REGS(regs)                                                 \
 119 do {                                                                          \
 120         if ((regs)->trap & 1)                                                 \
 121                 printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
 122 } while (0)
 123 #endif /* __powerpc64__ */
 124
 125 /*
 126  * These are defined as per linux/ptrace.h, which see.
 127  */
 128 #define arch_has_single_step()  (1)
 129 extern void user_enable_single_step(struct task_struct *);
 130 extern void user_disable_single_step(struct task_struct *);
 131
 132 #endif /* __ASSEMBLY__ */
 133
 134 #endif /* __KERNEL__ */
 135
 136 /*
 137  * Offsets used by 'ptrace' system call interface.
 138  * These can't be changed without breaking binary compatibility
 139  * with MkLinux, etc.
 140  */
 141 #define PT_R0   0
 142 #define PT_R1   1
 143 #define PT_R2   2
 144 #define PT_R3   3
 145 #define PT_R4   4
 146 #define PT_R5   5
 147 #define PT_R6   6
 148 #define PT_R7   7
 149 #define PT_R8   8
 150 #define PT_R9   9
 151 #define PT_R10  10
 152 #define PT_R11  11
 153 #define PT_R12  12
 154 #define PT_R13  13
 155 #define PT_R14  14
 156 #define PT_R15  15
 157 #define PT_R16  16
 158 #define PT_R17  17
 159 #define PT_R18  18
 160 #define PT_R19  19
 161 #define PT_R20  20
 162 #define PT_R21  21
 163 #define PT_R22  22
 164 #define PT_R23  23
 165 #define PT_R24  24
 166 #define PT_R25  25
 167 #define PT_R26  26
 168 #define PT_R27  27
 169 #define PT_R28  28
 170 #define PT_R29  29
 171 #define PT_R30  30
 172 #define PT_R31  31
 173
 174 #define PT_NIP  32
 175 #define PT_MSR  33
 176 #define PT_ORIG_R3 34
 177 #define PT_CTR  35
 178 #define PT_LNK  36
 179 #define PT_XER  37
 180 #define PT_CCR  38
 181 #ifndef __powerpc64__
 182 #define PT_MQ   39
 183 #else
 184 #define PT_SOFTE 39
 185 #endif
 186 #define PT_TRAP 40
 187 #define PT_DAR  41
 188 #define PT_DSISR 42
 189 #define PT_RESULT 43
 190 #define PT_REGS_COUNT 44
 191
 192 #define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
 193
 194 #ifndef __powerpc64__
 195
 196 #define PT_FPR31 (PT_FPR0 + 2*31)
 197 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 198
 199 #else /* __powerpc64__ */
 200
 201 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
 202
 203 #ifdef __KERNEL__
 204 #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
 205 #endif
 206
 207 #define PT_VR0 82       /* each Vector reg occupies 2 slots in 64-bit */
 208 #define PT_VSCR (PT_VR0 + 32*2 + 1)
 209 #define PT_VRSAVE (PT_VR0 + 33*2)
 210
 211 #ifdef __KERNEL__
 212 #define PT_VR0_32 164   /* each Vector reg occupies 4 slots in 32-bit */
 213 #define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
 214 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
 215 #endif
 216
 217 #endif /* __powerpc64__ */
 218
 219 /*
 220  * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
 221  * The transfer totals 34 quadword.  Quadwords 0-31 contain the
 222  * corresponding vector registers.  Quadword 32 contains the vscr as the
 223  * last word (offset 12) within that quadword.  Quadword 33 contains the
 224  * vrsave as the first word (offset 0) within the quadword.
 225  *
 226  * This definition of the VMX state is compatible with the current PPC32
 227  * ptrace interface.  This allows signal handling and ptrace to use the same
 228  * structures.  This also simplifies the implementation of a bi-arch
 229  * (combined (32- and 64-bit) gdb.
 230  */
 231 #define PTRACE_GETVRREGS        18
 232 #define PTRACE_SETVRREGS        19
 233
 234 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
 235  * spefscr, in one go */
 236 #define PTRACE_GETEVRREGS       20
 237 #define PTRACE_SETEVRREGS       21
 238
 239 /*
 240  * Get or set a debug register. The first 16 are DABR registers and the
 241  * second 16 are IABR registers.
 242  */
 243 #define PTRACE_GET_DEBUGREG     25
 244 #define PTRACE_SET_DEBUGREG     26
 245
 246 /* (new) PTRACE requests using the same numbers as x86 and the same
 247  * argument ordering. Additionally, they support more registers too
 248  */
 249 #define PTRACE_GETREGS            12
 250 #define PTRACE_SETREGS            13
 251 #define PTRACE_GETFPREGS          14
 252 #define PTRACE_SETFPREGS          15
 253 #define PTRACE_GETREGS64          22
 254 #define PTRACE_SETREGS64          23
 255
 256 /* (old) PTRACE requests with inverted arguments */
 257 #define PPC_PTRACE_GETREGS      0x99    /* Get GPRs 0 - 31 */
 258 #define PPC_PTRACE_SETREGS      0x98    /* Set GPRs 0 - 31 */
 259 #define PPC_PTRACE_GETFPREGS    0x97    /* Get FPRs 0 - 31 */
 260 #define PPC_PTRACE_SETFPREGS    0x96    /* Set FPRs 0 - 31 */
 261
 262 /* Calls to trace a 64bit program from a 32bit program */
 263 #define PPC_PTRACE_PEEKTEXT_3264 0x95
 264 #define PPC_PTRACE_PEEKDATA_3264 0x94
 265 #define PPC_PTRACE_POKETEXT_3264 0x93
 266 #define PPC_PTRACE_POKEDATA_3264 0x92
 267 #define PPC_PTRACE_PEEKUSR_3264  0x91
 268 #define PPC_PTRACE_POKEUSR_3264  0x90
 269
 270 #endif /* _ASM_POWERPC_PTRACE_H */