?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Initial commit
[wrt350n-kernel.git] / include / asm-x86 / paravirt.h
blobd6236eb46466c19ed4ebab33e64b3290ca127f53
1 #ifndef __ASM_PARAVIRT_H
2 #define __ASM_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/page.h>
8 #include <asm/asm.h>
9
10 /* Bitmask of what can be clobbered: usually at least eax. */
11 #define CLBR_NONE 0
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
15
16 #ifdef CONFIG_X86_64
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
25 #else
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
28 #endif /* X86_64 */
29
30 #ifndef __ASSEMBLY__
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
35
36 struct page;
37 struct thread_struct;
38 struct desc_ptr;
39 struct tss_struct;
40 struct mm_struct;
41 struct desc_struct;
42
43 /* general info */
44 struct pv_info {
45 unsigned int kernel_rpl;
46 int shared_kernel_pmd;
47 int paravirt_enabled;
48 const char *name;
49 };
50
51 struct pv_init_ops {
52 /*
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
59 */
60 unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
61 unsigned long addr, unsigned len);
62
63 /* Basic arch-specific setup */
64 void (*arch_setup)(void);
65 char *(*memory_setup)(void);
66 void (*post_allocator_init)(void);
67
68 /* Print a banner to identify the environment */
69 void (*banner)(void);
70 };
71
72
73 struct pv_lazy_ops {
74 /* Set deferred update mode, used for batching operations. */
75 void (*enter)(void);
76 void (*leave)(void);
77 };
78
79 struct pv_time_ops {
80 void (*time_init)(void);
81
82 /* Set and set time of day */
83 unsigned long (*get_wallclock)(void);
84 int (*set_wallclock)(unsigned long);
85
86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_cpu_khz)(void);
88 };
89
90 struct pv_cpu_ops {
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg)(int regno);
93 void (*set_debugreg)(int regno, unsigned long value);
94
95 void (*clts)(void);
96
97 unsigned long (*read_cr0)(void);
98 void (*write_cr0)(unsigned long);
99
100 unsigned long (*read_cr4_safe)(void);
101 unsigned long (*read_cr4)(void);
102 void (*write_cr4)(unsigned long);
103
104 #ifdef CONFIG_X86_64
105 unsigned long (*read_cr8)(void);
106 void (*write_cr8)(unsigned long);
107 #endif
108
109 /* Segment descriptor handling */
110 void (*load_tr_desc)(void);
111 void (*load_gdt)(const struct desc_ptr *);
112 void (*load_idt)(const struct desc_ptr *);
113 void (*store_gdt)(struct desc_ptr *);
114 void (*store_idt)(struct desc_ptr *);
115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
119 const void *desc);
120 void (*write_gdt_entry)(struct desc_struct *,
121 int entrynum, const void *desc, int size);
122 void (*write_idt_entry)(gate_desc *,
123 int entrynum, const gate_desc *gate);
124 void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
125
126 void (*set_iopl_mask)(unsigned mask);
127
128 void (*wbinvd)(void);
129 void (*io_delay)(void);
130
131 /* cpuid emulation, mostly so that caps bits can be disabled */
132 void (*cpuid)(unsigned int *eax, unsigned int *ebx,
133 unsigned int *ecx, unsigned int *edx);
134
135 /* MSR, PMC and TSR operations.
136 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
137 u64 (*read_msr)(unsigned int msr, int *err);
138 int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
139
140 u64 (*read_tsc)(void);
141 u64 (*read_pmc)(int counter);
142 unsigned long long (*read_tscp)(unsigned int *aux);
143
144 /* These two are jmp to, not actually called. */
145 void (*irq_enable_syscall_ret)(void);
146 void (*iret)(void);
147
148 void (*swapgs)(void);
149
150 struct pv_lazy_ops lazy_mode;
151 };
152
153 struct pv_irq_ops {
154 void (*init_IRQ)(void);
155
156 /*
157 * Get/set interrupt state. save_fl and restore_fl are only
158 * expected to use X86_EFLAGS_IF; all other bits
159 * returned from save_fl are undefined, and may be ignored by
160 * restore_fl.
161 */
162 unsigned long (*save_fl)(void);
163 void (*restore_fl)(unsigned long);
164 void (*irq_disable)(void);
165 void (*irq_enable)(void);
166 void (*safe_halt)(void);
167 void (*halt)(void);
168 };
169
170 struct pv_apic_ops {
171 #ifdef CONFIG_X86_LOCAL_APIC
172 /*
173 * Direct APIC operations, principally for VMI. Ideally
174 * these shouldn't be in this interface.
175 */
176 void (*apic_write)(unsigned long reg, u32 v);
177 void (*apic_write_atomic)(unsigned long reg, u32 v);
178 u32 (*apic_read)(unsigned long reg);
179 void (*setup_boot_clock)(void);
180 void (*setup_secondary_clock)(void);
181
182 void (*startup_ipi_hook)(int phys_apicid,
183 unsigned long start_eip,
184 unsigned long start_esp);
185 #endif
186 };
187
188 struct pv_mmu_ops {
189 /*
190 * Called before/after init_mm pagetable setup. setup_start
191 * may reset %cr3, and may pre-install parts of the pagetable;
192 * pagetable setup is expected to preserve any existing
193 * mapping.
194 */
195 void (*pagetable_setup_start)(pgd_t *pgd_base);
196 void (*pagetable_setup_done)(pgd_t *pgd_base);
197
198 unsigned long (*read_cr2)(void);
199 void (*write_cr2)(unsigned long);
200
201 unsigned long (*read_cr3)(void);
202 void (*write_cr3)(unsigned long);
203
204 /*
205 * Hooks for intercepting the creation/use/destruction of an
206 * mm_struct.
207 */
208 void (*activate_mm)(struct mm_struct *prev,
209 struct mm_struct *next);
210 void (*dup_mmap)(struct mm_struct *oldmm,
211 struct mm_struct *mm);
212 void (*exit_mmap)(struct mm_struct *mm);
213
214
215 /* TLB operations */
216 void (*flush_tlb_user)(void);
217 void (*flush_tlb_kernel)(void);
218 void (*flush_tlb_single)(unsigned long addr);
219 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
220 unsigned long va);
221
222 /* Hooks for allocating/releasing pagetable pages */
223 void (*alloc_pt)(struct mm_struct *mm, u32 pfn);
224 void (*alloc_pd)(struct mm_struct *mm, u32 pfn);
225 void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
226 void (*release_pt)(u32 pfn);
227 void (*release_pd)(u32 pfn);
228
229 /* Pagetable manipulation functions */
230 void (*set_pte)(pte_t *ptep, pte_t pteval);
231 void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
232 pte_t *ptep, pte_t pteval);
233 void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
234 void (*pte_update)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
235 void (*pte_update_defer)(struct mm_struct *mm,
236 unsigned long addr, pte_t *ptep);
237
238 pteval_t (*pte_val)(pte_t);
239 pte_t (*make_pte)(pteval_t pte);
240
241 pgdval_t (*pgd_val)(pgd_t);
242 pgd_t (*make_pgd)(pgdval_t pgd);
243
244 #if PAGETABLE_LEVELS >= 3
245 #ifdef CONFIG_X86_PAE
246 void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
247 void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
248 pte_t *ptep, pte_t pte);
249 void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
250 void (*pmd_clear)(pmd_t *pmdp);
251
252 #endif /* CONFIG_X86_PAE */
253
254 void (*set_pud)(pud_t *pudp, pud_t pudval);
255
256 pmdval_t (*pmd_val)(pmd_t);
257 pmd_t (*make_pmd)(pmdval_t pmd);
258
259 #if PAGETABLE_LEVELS == 4
260 pudval_t (*pud_val)(pud_t);
261 pud_t (*make_pud)(pudval_t pud);
262
263 void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
264 #endif /* PAGETABLE_LEVELS == 4 */
265 #endif /* PAGETABLE_LEVELS >= 3 */
266
267 #ifdef CONFIG_HIGHPTE
268 void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
269 #endif
270
271 struct pv_lazy_ops lazy_mode;
272 };
273
274 /* This contains all the paravirt structures: we get a convenient
275 * number for each function using the offset which we use to indicate
276 * what to patch. */
277 struct paravirt_patch_template
278 {
279 struct pv_init_ops pv_init_ops;
280 struct pv_time_ops pv_time_ops;
281 struct pv_cpu_ops pv_cpu_ops;
282 struct pv_irq_ops pv_irq_ops;
283 struct pv_apic_ops pv_apic_ops;
284 struct pv_mmu_ops pv_mmu_ops;
285 };
286
287 extern struct pv_info pv_info;
288 extern struct pv_init_ops pv_init_ops;
289 extern struct pv_time_ops pv_time_ops;
290 extern struct pv_cpu_ops pv_cpu_ops;
291 extern struct pv_irq_ops pv_irq_ops;
292 extern struct pv_apic_ops pv_apic_ops;
293 extern struct pv_mmu_ops pv_mmu_ops;
294
295 #define PARAVIRT_PATCH(x) \
296 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
297
298 #define paravirt_type(op) \
299 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
300 [paravirt_opptr] "m" (op)
301 #define paravirt_clobber(clobber) \
302 [paravirt_clobber] "i" (clobber)
303
304 /*
305 * Generate some code, and mark it as patchable by the
306 * apply_paravirt() alternate instruction patcher.
307 */
308 #define _paravirt_alt(insn_string, type, clobber) \
309 "771:\n\t" insn_string "\n" "772:\n" \
310 ".pushsection .parainstructions,\"a\"\n" \
311 _ASM_ALIGN "\n" \
312 _ASM_PTR " 771b\n" \
313 " .byte " type "\n" \
314 " .byte 772b-771b\n" \
315 " .short " clobber "\n" \
316 ".popsection\n"
317
318 /* Generate patchable code, with the default asm parameters. */
319 #define paravirt_alt(insn_string) \
320 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
321
322 /* Simple instruction patching code. */
323 #define DEF_NATIVE(ops, name, code) \
324 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
325 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
326
327 unsigned paravirt_patch_nop(void);
328 unsigned paravirt_patch_ignore(unsigned len);
329 unsigned paravirt_patch_call(void *insnbuf,
330 const void *target, u16 tgt_clobbers,
331 unsigned long addr, u16 site_clobbers,
332 unsigned len);
333 unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
334 unsigned long addr, unsigned len);
335 unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
336 unsigned long addr, unsigned len);
337
338 unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
339 const char *start, const char *end);
340
341 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
342 unsigned long addr, unsigned len);
343
344 int paravirt_disable_iospace(void);
345
346 /*
347 * This generates an indirect call based on the operation type number.
348 * The type number, computed in PARAVIRT_PATCH, is derived from the
349 * offset into the paravirt_patch_template structure, and can therefore be
350 * freely converted back into a structure offset.
351 */
352 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
353
354 /*
355 * These macros are intended to wrap calls through one of the paravirt
356 * ops structs, so that they can be later identified and patched at
357 * runtime.
358 *
359 * Normally, a call to a pv_op function is a simple indirect call:
360 * (pv_op_struct.operations)(args...).
361 *
362 * Unfortunately, this is a relatively slow operation for modern CPUs,
363 * because it cannot necessarily determine what the destination
364 * address is. In this case, the address is a runtime constant, so at
365 * the very least we can patch the call to e a simple direct call, or
366 * ideally, patch an inline implementation into the callsite. (Direct
367 * calls are essentially free, because the call and return addresses
368 * are completely predictable.)
369 *
370 * For i386, these macros rely on the standard gcc "regparm(3)" calling
371 * convention, in which the first three arguments are placed in %eax,
372 * %edx, %ecx (in that order), and the remaining arguments are placed
373 * on the stack. All caller-save registers (eax,edx,ecx) are expected
374 * to be modified (either clobbered or used for return values).
375 * X86_64, on the other hand, already specifies a register-based calling
376 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
377 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
378 * special handling for dealing with 4 arguments, unlike i386.
379 * However, x86_64 also have to clobber all caller saved registers, which
380 * unfortunately, are quite a bit (r8 - r11)
381 *
382 * The call instruction itself is marked by placing its start address
383 * and size into the .parainstructions section, so that
384 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
385 * appropriate patching under the control of the backend pv_init_ops
386 * implementation.
387 *
388 * Unfortunately there's no way to get gcc to generate the args setup
389 * for the call, and then allow the call itself to be generated by an
390 * inline asm. Because of this, we must do the complete arg setup and
391 * return value handling from within these macros. This is fairly
392 * cumbersome.
393 *
394 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
395 * It could be extended to more arguments, but there would be little
396 * to be gained from that. For each number of arguments, there are
397 * the two VCALL and CALL variants for void and non-void functions.
398 *
399 * When there is a return value, the invoker of the macro must specify
400 * the return type. The macro then uses sizeof() on that type to
401 * determine whether its a 32 or 64 bit value, and places the return
402 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
403 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
404 * the return value size.
405 *
406 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
407 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
408 * in low,high order
409 *
410 * Small structures are passed and returned in registers. The macro
411 * calling convention can't directly deal with this, so the wrapper
412 * functions must do this.
413 *
414 * These PVOP_* macros are only defined within this header. This
415 * means that all uses must be wrapped in inline functions. This also
416 * makes sure the incoming and outgoing types are always correct.
417 */
418 #ifdef CONFIG_X86_32
419 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
420 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
421 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
422 "=c" (__ecx)
423 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
424 #define EXTRA_CLOBBERS
425 #define VEXTRA_CLOBBERS
426 #else
427 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
428 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
429 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
430 "=S" (__esi), "=d" (__edx), \
431 "=c" (__ecx)
432
433 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
434
435 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
436 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
437 #endif
438
439 #define __PVOP_CALL(rettype, op, pre, post, ...) \
440 ({ \
441 rettype __ret; \
442 PVOP_CALL_ARGS; \
443 /* This is 32-bit specific, but is okay in 64-bit */ \
444 /* since this condition will never hold */ \
445 if (sizeof(rettype) > sizeof(unsigned long)) { \
446 asm volatile(pre \
447 paravirt_alt(PARAVIRT_CALL) \
448 post \
449 : PVOP_CALL_CLOBBERS \
450 : paravirt_type(op), \
451 paravirt_clobber(CLBR_ANY), \
452 ##__VA_ARGS__ \
453 : "memory", "cc" EXTRA_CLOBBERS); \
454 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
455 } else { \
456 asm volatile(pre \
457 paravirt_alt(PARAVIRT_CALL) \
458 post \
459 : PVOP_CALL_CLOBBERS \
460 : paravirt_type(op), \
461 paravirt_clobber(CLBR_ANY), \
462 ##__VA_ARGS__ \
463 : "memory", "cc" EXTRA_CLOBBERS); \
464 __ret = (rettype)__eax; \
465 } \
466 __ret; \
467 })
468 #define __PVOP_VCALL(op, pre, post, ...) \
469 ({ \
470 PVOP_VCALL_ARGS; \
471 asm volatile(pre \
472 paravirt_alt(PARAVIRT_CALL) \
473 post \
474 : PVOP_VCALL_CLOBBERS \
475 : paravirt_type(op), \
476 paravirt_clobber(CLBR_ANY), \
477 ##__VA_ARGS__ \
478 : "memory", "cc" VEXTRA_CLOBBERS); \
479 })
480
481 #define PVOP_CALL0(rettype, op) \
482 __PVOP_CALL(rettype, op, "", "")
483 #define PVOP_VCALL0(op) \
484 __PVOP_VCALL(op, "", "")
485
486 #define PVOP_CALL1(rettype, op, arg1) \
487 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
488 #define PVOP_VCALL1(op, arg1) \
489 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
490
491 #define PVOP_CALL2(rettype, op, arg1, arg2) \
492 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
493 "1" ((unsigned long)(arg2)))
494 #define PVOP_VCALL2(op, arg1, arg2) \
495 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
496 "1" ((unsigned long)(arg2)))
497
498 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
499 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
500 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
501 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
502 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
503 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
504
505 /* This is the only difference in x86_64. We can make it much simpler */
506 #ifdef CONFIG_X86_32
507 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
508 __PVOP_CALL(rettype, op, \
509 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
510 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
511 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
512 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
513 __PVOP_VCALL(op, \
514 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
515 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
516 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
517 #else
518 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
519 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
520 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
521 "3"((unsigned long)(arg4)))
522 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
523 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
524 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
525 "3"((unsigned long)(arg4)))
526 #endif
527
528 static inline int paravirt_enabled(void)
529 {
530 return pv_info.paravirt_enabled;
531 }
532
533 static inline void load_sp0(struct tss_struct *tss,
534 struct thread_struct *thread)
535 {
536 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
537 }
538
539 #define ARCH_SETUP pv_init_ops.arch_setup();
540 static inline unsigned long get_wallclock(void)
541 {
542 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
543 }
544
545 static inline int set_wallclock(unsigned long nowtime)
546 {
547 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
548 }
549
550 static inline void (*choose_time_init(void))(void)
551 {
552 return pv_time_ops.time_init;
553 }
554
555 /* The paravirtualized CPUID instruction. */
556 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
557 unsigned int *ecx, unsigned int *edx)
558 {
559 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
560 }
561
562 /*
563 * These special macros can be used to get or set a debugging register
564 */
565 static inline unsigned long paravirt_get_debugreg(int reg)
566 {
567 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
568 }
569 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
570 static inline void set_debugreg(unsigned long val, int reg)
571 {
572 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
573 }
574
575 static inline void clts(void)
576 {
577 PVOP_VCALL0(pv_cpu_ops.clts);
578 }
579
580 static inline unsigned long read_cr0(void)
581 {
582 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
583 }
584
585 static inline void write_cr0(unsigned long x)
586 {
587 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
588 }
589
590 static inline unsigned long read_cr2(void)
591 {
592 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
593 }
594
595 static inline void write_cr2(unsigned long x)
596 {
597 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
598 }
599
600 static inline unsigned long read_cr3(void)
601 {
602 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
603 }
604
605 static inline void write_cr3(unsigned long x)
606 {
607 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
608 }
609
610 static inline unsigned long read_cr4(void)
611 {
612 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
613 }
614 static inline unsigned long read_cr4_safe(void)
615 {
616 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
617 }
618
619 static inline void write_cr4(unsigned long x)
620 {
621 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
622 }
623
624 #ifdef CONFIG_X86_64
625 static inline unsigned long read_cr8(void)
626 {
627 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
628 }
629
630 static inline void write_cr8(unsigned long x)
631 {
632 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
633 }
634 #endif
635
636 static inline void raw_safe_halt(void)
637 {
638 PVOP_VCALL0(pv_irq_ops.safe_halt);
639 }
640
641 static inline void halt(void)
642 {
643 PVOP_VCALL0(pv_irq_ops.safe_halt);
644 }
645
646 static inline void wbinvd(void)
647 {
648 PVOP_VCALL0(pv_cpu_ops.wbinvd);
649 }
650
651 #define get_kernel_rpl() (pv_info.kernel_rpl)
652
653 static inline u64 paravirt_read_msr(unsigned msr, int *err)
654 {
655 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
656 }
657 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
658 {
659 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
660 }
661
662 /* These should all do BUG_ON(_err), but our headers are too tangled. */
663 #define rdmsr(msr,val1,val2) do { \
664 int _err; \
665 u64 _l = paravirt_read_msr(msr, &_err); \
666 val1 = (u32)_l; \
667 val2 = _l >> 32; \
668 } while(0)
669
670 #define wrmsr(msr,val1,val2) do { \
671 paravirt_write_msr(msr, val1, val2); \
672 } while(0)
673
674 #define rdmsrl(msr,val) do { \
675 int _err; \
676 val = paravirt_read_msr(msr, &_err); \
677 } while(0)
678
679 #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
680 #define wrmsr_safe(msr,a,b) paravirt_write_msr(msr, a, b)
681
682 /* rdmsr with exception handling */
683 #define rdmsr_safe(msr,a,b) ({ \
684 int _err; \
685 u64 _l = paravirt_read_msr(msr, &_err); \
686 (*a) = (u32)_l; \
687 (*b) = _l >> 32; \
688 _err; })
689
690
691 static inline u64 paravirt_read_tsc(void)
692 {
693 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
694 }
695
696 #define rdtscl(low) do { \
697 u64 _l = paravirt_read_tsc(); \
698 low = (int)_l; \
699 } while(0)
700
701 #define rdtscll(val) (val = paravirt_read_tsc())
702
703 static inline unsigned long long paravirt_sched_clock(void)
704 {
705 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
706 }
707 #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
708
709 static inline unsigned long long paravirt_read_pmc(int counter)
710 {
711 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
712 }
713
714 #define rdpmc(counter,low,high) do { \
715 u64 _l = paravirt_read_pmc(counter); \
716 low = (u32)_l; \
717 high = _l >> 32; \
718 } while(0)
719
720 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
721 {
722 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
723 }
724
725 #define rdtscp(low, high, aux) \
726 do { \
727 int __aux; \
728 unsigned long __val = paravirt_rdtscp(&__aux); \
729 (low) = (u32)__val; \
730 (high) = (u32)(__val >> 32); \
731 (aux) = __aux; \
732 } while (0)
733
734 #define rdtscpll(val, aux) \
735 do { \
736 unsigned long __aux; \
737 val = paravirt_rdtscp(&__aux); \
738 (aux) = __aux; \
739 } while (0)
740
741 static inline void load_TR_desc(void)
742 {
743 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
744 }
745 static inline void load_gdt(const struct desc_ptr *dtr)
746 {
747 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
748 }
749 static inline void load_idt(const struct desc_ptr *dtr)
750 {
751 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
752 }
753 static inline void set_ldt(const void *addr, unsigned entries)
754 {
755 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
756 }
757 static inline void store_gdt(struct desc_ptr *dtr)
758 {
759 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
760 }
761 static inline void store_idt(struct desc_ptr *dtr)
762 {
763 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
764 }
765 static inline unsigned long paravirt_store_tr(void)
766 {
767 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
768 }
769 #define store_tr(tr) ((tr) = paravirt_store_tr())
770 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
771 {
772 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
773 }
774
775 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
776 const void *desc)
777 {
778 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
779 }
780
781 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
782 void *desc, int type)
783 {
784 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
785 }
786
787 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
788 {
789 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
790 }
791 static inline void set_iopl_mask(unsigned mask)
792 {
793 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
794 }
795
796 /* The paravirtualized I/O functions */
797 static inline void slow_down_io(void) {
798 pv_cpu_ops.io_delay();
799 #ifdef REALLY_SLOW_IO
800 pv_cpu_ops.io_delay();
801 pv_cpu_ops.io_delay();
802 pv_cpu_ops.io_delay();
803 #endif
804 }
805
806 #ifdef CONFIG_X86_LOCAL_APIC
807 /*
808 * Basic functions accessing APICs.
809 */
810 static inline void apic_write(unsigned long reg, u32 v)
811 {
812 PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
813 }
814
815 static inline void apic_write_atomic(unsigned long reg, u32 v)
816 {
817 PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v);
818 }
819
820 static inline u32 apic_read(unsigned long reg)
821 {
822 return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
823 }
824
825 static inline void setup_boot_clock(void)
826 {
827 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
828 }
829
830 static inline void setup_secondary_clock(void)
831 {
832 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
833 }
834 #endif
835
836 static inline void paravirt_post_allocator_init(void)
837 {
838 if (pv_init_ops.post_allocator_init)
839 (*pv_init_ops.post_allocator_init)();
840 }
841
842 static inline void paravirt_pagetable_setup_start(pgd_t *base)
843 {
844 (*pv_mmu_ops.pagetable_setup_start)(base);
845 }
846
847 static inline void paravirt_pagetable_setup_done(pgd_t *base)
848 {
849 (*pv_mmu_ops.pagetable_setup_done)(base);
850 }
851
852 #ifdef CONFIG_SMP
853 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
854 unsigned long start_esp)
855 {
856 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
857 phys_apicid, start_eip, start_esp);
858 }
859 #endif
860
861 static inline void paravirt_activate_mm(struct mm_struct *prev,
862 struct mm_struct *next)
863 {
864 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
865 }
866
867 static inline void arch_dup_mmap(struct mm_struct *oldmm,
868 struct mm_struct *mm)
869 {
870 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
871 }
872
873 static inline void arch_exit_mmap(struct mm_struct *mm)
874 {
875 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
876 }
877
878 static inline void __flush_tlb(void)
879 {
880 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
881 }
882 static inline void __flush_tlb_global(void)
883 {
884 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
885 }
886 static inline void __flush_tlb_single(unsigned long addr)
887 {
888 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
889 }
890
891 static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
892 unsigned long va)
893 {
894 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
895 }
896
897 static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn)
898 {
899 PVOP_VCALL2(pv_mmu_ops.alloc_pt, mm, pfn);
900 }
901 static inline void paravirt_release_pt(unsigned pfn)
902 {
903 PVOP_VCALL1(pv_mmu_ops.release_pt, pfn);
904 }
905
906 static inline void paravirt_alloc_pd(struct mm_struct *mm, unsigned pfn)
907 {
908 PVOP_VCALL2(pv_mmu_ops.alloc_pd, mm, pfn);
909 }
910
911 static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn,
912 unsigned start, unsigned count)
913 {
914 PVOP_VCALL4(pv_mmu_ops.alloc_pd_clone, pfn, clonepfn, start, count);
915 }
916 static inline void paravirt_release_pd(unsigned pfn)
917 {
918 PVOP_VCALL1(pv_mmu_ops.release_pd, pfn);
919 }
920
921 #ifdef CONFIG_HIGHPTE
922 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
923 {
924 unsigned long ret;
925 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
926 return (void *)ret;
927 }
928 #endif
929
930 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
931 pte_t *ptep)
932 {
933 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
934 }
935
936 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
937 pte_t *ptep)
938 {
939 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
940 }
941
942 static inline pte_t __pte(pteval_t val)
943 {
944 pteval_t ret;
945
946 if (sizeof(pteval_t) > sizeof(long))
947 ret = PVOP_CALL2(pteval_t,
948 pv_mmu_ops.make_pte,
949 val, (u64)val >> 32);
950 else
951 ret = PVOP_CALL1(pteval_t,
952 pv_mmu_ops.make_pte,
953 val);
954
955 return (pte_t) { .pte = ret };
956 }
957
958 static inline pteval_t pte_val(pte_t pte)
959 {
960 pteval_t ret;
961
962 if (sizeof(pteval_t) > sizeof(long))
963 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
964 pte.pte, (u64)pte.pte >> 32);
965 else
966 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
967 pte.pte);
968
969 return ret;
970 }
971
972 static inline pgd_t __pgd(pgdval_t val)
973 {
974 pgdval_t ret;
975
976 if (sizeof(pgdval_t) > sizeof(long))
977 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
978 val, (u64)val >> 32);
979 else
980 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
981 val);
982
983 return (pgd_t) { ret };
984 }
985
986 static inline pgdval_t pgd_val(pgd_t pgd)
987 {
988 pgdval_t ret;
989
990 if (sizeof(pgdval_t) > sizeof(long))
991 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
992 pgd.pgd, (u64)pgd.pgd >> 32);
993 else
994 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
995 pgd.pgd);
996
997 return ret;
998 }
999
1000 static inline void set_pte(pte_t *ptep, pte_t pte)
1001 {
1002 if (sizeof(pteval_t) > sizeof(long))
1003 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
1004 pte.pte, (u64)pte.pte >> 32);
1005 else
1006 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
1007 pte.pte);
1008 }
1009
1010 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1011 pte_t *ptep, pte_t pte)
1012 {
1013 if (sizeof(pteval_t) > sizeof(long))
1014 /* 5 arg words */
1015 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
1016 else
1017 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
1018 }
1019
1020 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1021 {
1022 pmdval_t val = native_pmd_val(pmd);
1023
1024 if (sizeof(pmdval_t) > sizeof(long))
1025 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
1026 else
1027 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
1028 }
1029
1030 #if PAGETABLE_LEVELS >= 3
1031 static inline pmd_t __pmd(pmdval_t val)
1032 {
1033 pmdval_t ret;
1034
1035 if (sizeof(pmdval_t) > sizeof(long))
1036 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
1037 val, (u64)val >> 32);
1038 else
1039 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
1040 val);
1041
1042 return (pmd_t) { ret };
1043 }
1044
1045 static inline pmdval_t pmd_val(pmd_t pmd)
1046 {
1047 pmdval_t ret;
1048
1049 if (sizeof(pmdval_t) > sizeof(long))
1050 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
1051 pmd.pmd, (u64)pmd.pmd >> 32);
1052 else
1053 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
1054 pmd.pmd);
1055
1056 return ret;
1057 }
1058
1059 static inline void set_pud(pud_t *pudp, pud_t pud)
1060 {
1061 pudval_t val = native_pud_val(pud);
1062
1063 if (sizeof(pudval_t) > sizeof(long))
1064 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
1065 val, (u64)val >> 32);
1066 else
1067 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
1068 val);
1069 }
1070 #if PAGETABLE_LEVELS == 4
1071 static inline pud_t __pud(pudval_t val)
1072 {
1073 pudval_t ret;
1074
1075 if (sizeof(pudval_t) > sizeof(long))
1076 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
1077 val, (u64)val >> 32);
1078 else
1079 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
1080 val);
1081
1082 return (pud_t) { ret };
1083 }
1084
1085 static inline pudval_t pud_val(pud_t pud)
1086 {
1087 pudval_t ret;
1088
1089 if (sizeof(pudval_t) > sizeof(long))
1090 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
1091 pud.pud, (u64)pud.pud >> 32);
1092 else
1093 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
1094 pud.pud);
1095
1096 return ret;
1097 }
1098
1099 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1100 {
1101 pgdval_t val = native_pgd_val(pgd);
1102
1103 if (sizeof(pgdval_t) > sizeof(long))
1104 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
1105 val, (u64)val >> 32);
1106 else
1107 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
1108 val);
1109 }
1110
1111 static inline void pgd_clear(pgd_t *pgdp)
1112 {
1113 set_pgd(pgdp, __pgd(0));
1114 }
1115
1116 static inline void pud_clear(pud_t *pudp)
1117 {
1118 set_pud(pudp, __pud(0));
1119 }
1120
1121 #endif /* PAGETABLE_LEVELS == 4 */
1122
1123 #endif /* PAGETABLE_LEVELS >= 3 */
1124
1125 #ifdef CONFIG_X86_PAE
1126 /* Special-case pte-setting operations for PAE, which can't update a
1127 64-bit pte atomically */
1128 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1129 {
1130 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
1131 pte.pte, pte.pte >> 32);
1132 }
1133
1134 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1135 pte_t *ptep, pte_t pte)
1136 {
1137 /* 5 arg words */
1138 pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
1139 }
1140
1141 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1142 pte_t *ptep)
1143 {
1144 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
1145 }
1146
1147 static inline void pmd_clear(pmd_t *pmdp)
1148 {
1149 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
1150 }
1151 #else /* !CONFIG_X86_PAE */
1152 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1153 {
1154 set_pte(ptep, pte);
1155 }
1156
1157 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1158 pte_t *ptep, pte_t pte)
1159 {
1160 set_pte(ptep, pte);
1161 }
1162
1163 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1164 pte_t *ptep)
1165 {
1166 set_pte_at(mm, addr, ptep, __pte(0));
1167 }
1168
1169 static inline void pmd_clear(pmd_t *pmdp)
1170 {
1171 set_pmd(pmdp, __pmd(0));
1172 }
1173 #endif /* CONFIG_X86_PAE */
1174
1175 /* Lazy mode for batching updates / context switch */
1176 enum paravirt_lazy_mode {
1177 PARAVIRT_LAZY_NONE,
1178 PARAVIRT_LAZY_MMU,
1179 PARAVIRT_LAZY_CPU,
1180 };
1181
1182 enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
1183 void paravirt_enter_lazy_cpu(void);
1184 void paravirt_leave_lazy_cpu(void);
1185 void paravirt_enter_lazy_mmu(void);
1186 void paravirt_leave_lazy_mmu(void);
1187 void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
1188
1189 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1190 static inline void arch_enter_lazy_cpu_mode(void)
1191 {
1192 PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
1193 }
1194
1195 static inline void arch_leave_lazy_cpu_mode(void)
1196 {
1197 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1198 }
1199
1200 static inline void arch_flush_lazy_cpu_mode(void)
1201 {
1202 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1203 arch_leave_lazy_cpu_mode();
1204 arch_enter_lazy_cpu_mode();
1205 }
1206 }
1207
1208
1209 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1210 static inline void arch_enter_lazy_mmu_mode(void)
1211 {
1212 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
1213 }
1214
1215 static inline void arch_leave_lazy_mmu_mode(void)
1216 {
1217 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1218 }
1219
1220 static inline void arch_flush_lazy_mmu_mode(void)
1221 {
1222 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1223 arch_leave_lazy_mmu_mode();
1224 arch_enter_lazy_mmu_mode();
1225 }
1226 }
1227
1228 void _paravirt_nop(void);
1229 #define paravirt_nop ((void *)_paravirt_nop)
1230
1231 /* These all sit in the .parainstructions section to tell us what to patch. */
1232 struct paravirt_patch_site {
1233 u8 *instr; /* original instructions */
1234 u8 instrtype; /* type of this instruction */
1235 u8 len; /* length of original instruction */
1236 u16 clobbers; /* what registers you may clobber */
1237 };
1238
1239 extern struct paravirt_patch_site __parainstructions[],
1240 __parainstructions_end[];
1241
1242 #ifdef CONFIG_X86_32
1243 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1244 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1245 #define PV_FLAGS_ARG "0"
1246 #define PV_EXTRA_CLOBBERS
1247 #define PV_VEXTRA_CLOBBERS
1248 #else
1249 /* We save some registers, but all of them, that's too much. We clobber all
1250 * caller saved registers but the argument parameter */
1251 #define PV_SAVE_REGS "pushq %%rdi;"
1252 #define PV_RESTORE_REGS "popq %%rdi;"
1253 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx"
1254 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx"
1255 #define PV_FLAGS_ARG "D"
1256 #endif
1257
1258 static inline unsigned long __raw_local_save_flags(void)
1259 {
1260 unsigned long f;
1261
1262 asm volatile(paravirt_alt(PV_SAVE_REGS
1263 PARAVIRT_CALL
1264 PV_RESTORE_REGS)
1265 : "=a"(f)
1266 : paravirt_type(pv_irq_ops.save_fl),
1267 paravirt_clobber(CLBR_EAX)
1268 : "memory", "cc" PV_VEXTRA_CLOBBERS);
1269 return f;
1270 }
1271
1272 static inline void raw_local_irq_restore(unsigned long f)
1273 {
1274 asm volatile(paravirt_alt(PV_SAVE_REGS
1275 PARAVIRT_CALL
1276 PV_RESTORE_REGS)
1277 : "=a"(f)
1278 : PV_FLAGS_ARG(f),
1279 paravirt_type(pv_irq_ops.restore_fl),
1280 paravirt_clobber(CLBR_EAX)
1281 : "memory", "cc" PV_EXTRA_CLOBBERS);
1282 }
1283
1284 static inline void raw_local_irq_disable(void)
1285 {
1286 asm volatile(paravirt_alt(PV_SAVE_REGS
1287 PARAVIRT_CALL
1288 PV_RESTORE_REGS)
1289 :
1290 : paravirt_type(pv_irq_ops.irq_disable),
1291 paravirt_clobber(CLBR_EAX)
1292 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1293 }
1294
1295 static inline void raw_local_irq_enable(void)
1296 {
1297 asm volatile(paravirt_alt(PV_SAVE_REGS
1298 PARAVIRT_CALL
1299 PV_RESTORE_REGS)
1300 :
1301 : paravirt_type(pv_irq_ops.irq_enable),
1302 paravirt_clobber(CLBR_EAX)
1303 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1304 }
1305
1306 static inline unsigned long __raw_local_irq_save(void)
1307 {
1308 unsigned long f;
1309
1310 f = __raw_local_save_flags();
1311 raw_local_irq_disable();
1312 return f;
1313 }
1314
1315 /* Make sure as little as possible of this mess escapes. */
1316 #undef PARAVIRT_CALL
1317 #undef __PVOP_CALL
1318 #undef __PVOP_VCALL
1319 #undef PVOP_VCALL0
1320 #undef PVOP_CALL0
1321 #undef PVOP_VCALL1
1322 #undef PVOP_CALL1
1323 #undef PVOP_VCALL2
1324 #undef PVOP_CALL2
1325 #undef PVOP_VCALL3
1326 #undef PVOP_CALL3
1327 #undef PVOP_VCALL4
1328 #undef PVOP_CALL4
1329
1330 #else /* __ASSEMBLY__ */
1331
1332 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1333 771:; \
1334 ops; \
1335 772:; \
1336 .pushsection .parainstructions,"a"; \
1337 .align algn; \
1338 word 771b; \
1339 .byte ptype; \
1340 .byte 772b-771b; \
1341 .short clobbers; \
1342 .popsection
1343
1344
1345 #ifdef CONFIG_X86_64
1346 #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx
1347 #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1348 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1349 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1350 #else
1351 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1352 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1353 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1354 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1355 #endif
1356
1357 #define INTERRUPT_RETURN \
1358 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1359 jmp *%cs:pv_cpu_ops+PV_CPU_iret)
1360
1361 #define DISABLE_INTERRUPTS(clobbers) \
1362 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1363 PV_SAVE_REGS; \
1364 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
1365 PV_RESTORE_REGS;) \
1366
1367 #define ENABLE_INTERRUPTS(clobbers) \
1368 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1369 PV_SAVE_REGS; \
1370 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
1371 PV_RESTORE_REGS;)
1372
1373 #define ENABLE_INTERRUPTS_SYSCALL_RET \
1374 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\
1375 CLBR_NONE, \
1376 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)
1377
1378
1379 #ifdef CONFIG_X86_32
1380 #define GET_CR0_INTO_EAX \
1381 push %ecx; push %edx; \
1382 call *pv_cpu_ops+PV_CPU_read_cr0; \
1383 pop %edx; pop %ecx
1384 #else
1385 #define SWAPGS \
1386 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1387 PV_SAVE_REGS; \
1388 call *pv_cpu_ops+PV_CPU_swapgs; \
1389 PV_RESTORE_REGS \
1390 )
1391
1392 #define GET_CR2_INTO_RCX \
1393 call *pv_mmu_ops+PV_MMU_read_cr2; \
1394 movq %rax, %rcx; \
1395 xorq %rax, %rax;
1396
1397 #endif
1398
1399 #endif /* __ASSEMBLY__ */
1400 #endif /* CONFIG_PARAVIRT */
1401 #endif /* __ASM_PARAVIRT_H */
WRT350N Kernel Patches