drivers/serial/cpm_uart/cpm_uart_cpm1.c

   1 /*
   2  *  linux/drivers/serial/cpm_uart.c
   3  *
   4  *  Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
   5  *
   6  *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
   7  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
   8  *
   9  *  Copyright (C) 2004 Freescale Semiconductor, Inc.
  10  *            (C) 2004 Intracom, S.A.
  11  *            (C) 2006 MontaVista Software, Inc.
  12  *              Vitaly Bordug <vbordug@ru.mvista.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27  *
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/tty.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/serial.h>
  35 #include <linux/console.h>
  36 #include <linux/sysrq.h>
  37 #include <linux/device.h>
  38 #include <linux/bootmem.h>
  39 #include <linux/dma-mapping.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/fs_pd.h>
  44
  45 #include <linux/serial_core.h>
  46 #include <linux/kernel.h>
  47
  48 #include "cpm_uart.h"
  49
  50 /**************************************************************/
  51
  52 #ifdef CONFIG_PPC_CPM_NEW_BINDING
  53 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
  54 {
  55         cpm_command(port->command, cmd);
  56 }
  57 #else
  58 void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
  59 {
  60         ushort val;
  61         int line = port - cpm_uart_ports;
  62         volatile cpm8xx_t *cp = cpmp;
  63
  64         switch (line) {
  65         case UART_SMC1:
  66                 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
  67                 break;
  68         case UART_SMC2:
  69                 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
  70                 break;
  71         case UART_SCC1:
  72                 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
  73                 break;
  74         case UART_SCC2:
  75                 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
  76                 break;
  77         case UART_SCC3:
  78                 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
  79                 break;
  80         case UART_SCC4:
  81                 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
  82                 break;
  83         default:
  84                 return;
  85
  86         }
  87         cp->cp_cpcr = val;
  88         while (cp->cp_cpcr & CPM_CR_FLG) ;
  89 }
  90
  91 void smc1_lineif(struct uart_cpm_port *pinfo)
  92 {
  93         pinfo->brg = 1;
  94 }
  95
  96 void smc2_lineif(struct uart_cpm_port *pinfo)
  97 {
  98         pinfo->brg = 2;
  99 }
 100
 101 void scc1_lineif(struct uart_cpm_port *pinfo)
 102 {
 103         /* XXX SCC1: insert port configuration here */
 104         pinfo->brg = 1;
 105 }
 106
 107 void scc2_lineif(struct uart_cpm_port *pinfo)
 108 {
 109         /* XXX SCC2: insert port configuration here */
 110         pinfo->brg = 2;
 111 }
 112
 113 void scc3_lineif(struct uart_cpm_port *pinfo)
 114 {
 115         /* XXX SCC3: insert port configuration here */
 116         pinfo->brg = 3;
 117 }
 118
 119 void scc4_lineif(struct uart_cpm_port *pinfo)
 120 {
 121         /* XXX SCC4: insert port configuration here */
 122         pinfo->brg = 4;
 123 }
 124 #endif
 125
 126 /*
 127  * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
 128  * receive buffer descriptors from dual port ram, and a character
 129  * buffer area from host mem. If we are allocating for the console we need
 130  * to do it from bootmem
 131  */
 132 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 133 {
 134         int dpmemsz, memsz;
 135         u8 *dp_mem;
 136         unsigned long dp_offset;
 137         u8 *mem_addr;
 138         dma_addr_t dma_addr = 0;
 139
 140         pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
 141
 142         dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
 143         dp_offset = cpm_dpalloc(dpmemsz, 8);
 144         if (IS_ERR_VALUE(dp_offset)) {
 145                 printk(KERN_ERR
 146                        "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
 147                 return -ENOMEM;
 148         }
 149         dp_mem = cpm_dpram_addr(dp_offset);
 150
 151         memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 152             L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 153         if (is_con) {
 154                 /* was hostalloc but changed cause it blows away the */
 155                 /* large tlb mapping when pinning the kernel area    */
 156                 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
 157                 dma_addr = (u32)cpm_dpram_phys(mem_addr);
 158         } else
 159                 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
 160                                               GFP_KERNEL);
 161
 162         if (mem_addr == NULL) {
 163                 cpm_dpfree(dp_offset);
 164                 printk(KERN_ERR
 165                        "cpm_uart_cpm1.c: could not allocate coherent memory\n");
 166                 return -ENOMEM;
 167         }
 168
 169         pinfo->dp_addr = dp_offset;
 170         pinfo->mem_addr = mem_addr;             /*  virtual address*/
 171         pinfo->dma_addr = dma_addr;             /*  physical address*/
 172         pinfo->mem_size = memsz;
 173
 174         pinfo->rx_buf = mem_addr;
 175         pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
 176                                                        * pinfo->rx_fifosize);
 177
 178         pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
 179         pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
 180
 181         return 0;
 182 }
 183
 184 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
 185 {
 186         dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
 187                                                pinfo->rx_fifosize) +
 188                           L1_CACHE_ALIGN(pinfo->tx_nrfifos *
 189                                          pinfo->tx_fifosize), pinfo->mem_addr,
 190                           pinfo->dma_addr);
 191
 192         cpm_dpfree(pinfo->dp_addr);
 193 }
 194
 195 #ifndef CONFIG_PPC_CPM_NEW_BINDING
 196 /* Setup any dynamic params in the uart desc */
 197 int cpm_uart_init_portdesc(void)
 198 {
 199         pr_debug("CPM uart[-]:init portdesc\n");
 200
 201         cpm_uart_nr = 0;
 202 #ifdef CONFIG_SERIAL_CPM_SMC1
 203         cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
 204 /*
 205  *  Is SMC1 being relocated?
 206  */
 207 # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
 208         cpm_uart_ports[UART_SMC1].smcup =
 209             (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
 210 # else
 211         cpm_uart_ports[UART_SMC1].smcup =
 212             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
 213 # endif
 214         cpm_uart_ports[UART_SMC1].port.mapbase =
 215             (unsigned long)&cpmp->cp_smc[0];
 216         cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 217         cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 218         cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
 219         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
 220 #endif
 221
 222 #ifdef CONFIG_SERIAL_CPM_SMC2
 223         cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
 224         cpm_uart_ports[UART_SMC2].smcup =
 225             (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
 226         cpm_uart_ports[UART_SMC2].port.mapbase =
 227             (unsigned long)&cpmp->cp_smc[1];
 228         cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 229         cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 230         cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
 231         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
 232 #endif
 233
 234 #ifdef CONFIG_SERIAL_CPM_SCC1
 235         cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
 236         cpm_uart_ports[UART_SCC1].sccup =
 237             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
 238         cpm_uart_ports[UART_SCC1].port.mapbase =
 239             (unsigned long)&cpmp->cp_scc[0];
 240         cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
 241             ~(UART_SCCM_TX | UART_SCCM_RX);
 242         cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
 243             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 244         cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
 245         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
 246 #endif
 247
 248 #ifdef CONFIG_SERIAL_CPM_SCC2
 249         cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
 250         cpm_uart_ports[UART_SCC2].sccup =
 251             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
 252         cpm_uart_ports[UART_SCC2].port.mapbase =
 253             (unsigned long)&cpmp->cp_scc[1];
 254         cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
 255             ~(UART_SCCM_TX | UART_SCCM_RX);
 256         cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
 257             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 258         cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
 259         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
 260 #endif
 261
 262 #ifdef CONFIG_SERIAL_CPM_SCC3
 263         cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
 264         cpm_uart_ports[UART_SCC3].sccup =
 265             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
 266         cpm_uart_ports[UART_SCC3].port.mapbase =
 267             (unsigned long)&cpmp->cp_scc[2];
 268         cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
 269             ~(UART_SCCM_TX | UART_SCCM_RX);
 270         cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
 271             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 272         cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
 273         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
 274 #endif
 275
 276 #ifdef CONFIG_SERIAL_CPM_SCC4
 277         cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
 278         cpm_uart_ports[UART_SCC4].sccup =
 279             (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
 280         cpm_uart_ports[UART_SCC4].port.mapbase =
 281             (unsigned long)&cpmp->cp_scc[3];
 282         cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
 283             ~(UART_SCCM_TX | UART_SCCM_RX);
 284         cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
 285             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 286         cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
 287         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
 288 #endif
 289         return 0;
 290 }
 291 #endif