arch/alpha/kernel/time.c

   1 /*
   2  *  linux/arch/alpha/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
   5  *
   6  * This file contains the PC-specific time handling details:
   7  * reading the RTC at bootup, etc..
   8  * 1994-07-02    Alan Modra
   9  *      fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  10  * 1995-03-26    Markus Kuhn
  11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
  12  *      precision CMOS clock update
  13  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  14  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  15  * 1997-01-09    Adrian Sun
  16  *      use interval timer if CONFIG_RTC=y
  17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
  18  *      fixed tick loss calculation in timer_interrupt
  19  *      (round system clock to nearest tick instead of truncating)
  20  *      fixed algorithm in time_init for getting time from CMOS clock
  21  * 1999-04-16   Thorsten Kranzkowski (dl8bcu@gmx.net)
  22  *      fixed algorithm in do_gettimeofday() for calculating the precise time
  23  *      from processor cycle counter (now taking lost_ticks into account)
  24  * 2000-08-13   Jan-Benedict Glaw <jbglaw@lug-owl.de>
  25  *      Fixed time_init to be aware of epoches != 1900. This prevents
  26  *      booting up in 2048 for me;) Code is stolen from rtc.c.
  27  * 2003-06-03   R. Scott Bailey <scott.bailey@eds.com>
  28  *      Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
  29  */
  30 #include <linux/errno.h>
  31 #include <linux/module.h>
  32 #include <linux/sched.h>
  33 #include <linux/kernel.h>
  34 #include <linux/param.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/delay.h>
  38 #include <linux/ioport.h>
  39 #include <linux/irq.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/init.h>
  42 #include <linux/bcd.h>
  43 #include <linux/profile.h>
  44
  45 #include <asm/uaccess.h>
  46 #include <asm/io.h>
  47 #include <asm/hwrpb.h>
  48 #include <asm/8253pit.h>
  49
  50 #include <linux/mc146818rtc.h>
  51 #include <linux/time.h>
  52 #include <linux/timex.h>
  53
  54 #include "proto.h"
  55 #include "irq_impl.h"
  56
  57 static int set_rtc_mmss(unsigned long);
  58
  59 DEFINE_SPINLOCK(rtc_lock);
  60 EXPORT_SYMBOL(rtc_lock);
  61
  62 #define TICK_SIZE (tick_nsec / 1000)
  63
  64 /*
  65  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
  66  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
  67  * for large CPU clock rates.
  68  */
  69 #define FIX_SHIFT       48
  70
  71 /* lump static variables together for more efficient access: */
  72 static struct {
  73         /* cycle counter last time it got invoked */
  74         __u32 last_time;
  75         /* ticks/cycle * 2^48 */
  76         unsigned long scaled_ticks_per_cycle;
  77         /* last time the CMOS clock got updated */
  78         time_t last_rtc_update;
  79         /* partial unused tick */
  80         unsigned long partial_tick;
  81 } state;
  82
  83 unsigned long est_cycle_freq;
  84
  85
  86 static inline __u32 rpcc(void)
  87 {
  88     __u32 result;
  89     asm volatile ("rpcc %0" : "=r"(result));
  90     return result;
  91 }
  92
  93 /*
  94  * timer_interrupt() needs to keep up the real-time clock,
  95  * as well as call the "do_timer()" routine every clocktick
  96  */
  97 irqreturn_t timer_interrupt(int irq, void *dev)
  98 {
  99         unsigned long delta;
 100         __u32 now;
 101         long nticks;
 102
 103 #ifndef CONFIG_SMP
 104         /* Not SMP, do kernel PC profiling here.  */
 105         profile_tick(CPU_PROFILING);
 106 #endif
 107
 108         write_seqlock(&xtime_lock);
 109
 110         /*
 111          * Calculate how many ticks have passed since the last update,
 112          * including any previous partial leftover.  Save any resulting
 113          * fraction for the next pass.
 114          */
 115         now = rpcc();
 116         delta = now - state.last_time;
 117         state.last_time = now;
 118         delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
 119         state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
 120         nticks = delta >> FIX_SHIFT;
 121
 122         if (nticks)
 123                 do_timer(nticks);
 124
 125         /*
 126          * If we have an externally synchronized Linux clock, then update
 127          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 128          * called as close as possible to 500 ms before the new second starts.
 129          */
 130         if (ntp_synced()
 131             && xtime.tv_sec > state.last_rtc_update + 660
 132             && xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2
 133             && xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) {
 134                 int tmp = set_rtc_mmss(xtime.tv_sec);
 135                 state.last_rtc_update = xtime.tv_sec - (tmp ? 600 : 0);
 136         }
 137
 138         write_sequnlock(&xtime_lock);
 139
 140 #ifndef CONFIG_SMP
 141         while (nticks--)
 142                 update_process_times(user_mode(get_irq_regs()));
 143 #endif
 144
 145         return IRQ_HANDLED;
 146 }
 147
 148 void __init
 149 common_init_rtc(void)
 150 {
 151         unsigned char x;
 152
 153         /* Reset periodic interrupt frequency.  */
 154         x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
 155         /* Test includes known working values on various platforms
 156            where 0x26 is wrong; we refuse to change those. */
 157         if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
 158                 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
 159                 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
 160         }
 161
 162         /* Turn on periodic interrupts.  */
 163         x = CMOS_READ(RTC_CONTROL);
 164         if (!(x & RTC_PIE)) {
 165                 printk("Turning on RTC interrupts.\n");
 166                 x |= RTC_PIE;
 167                 x &= ~(RTC_AIE | RTC_UIE);
 168                 CMOS_WRITE(x, RTC_CONTROL);
 169         }
 170         (void) CMOS_READ(RTC_INTR_FLAGS);
 171
 172         outb(0x36, 0x43);       /* pit counter 0: system timer */
 173         outb(0x00, 0x40);
 174         outb(0x00, 0x40);
 175
 176         outb(0xb6, 0x43);       /* pit counter 2: speaker */
 177         outb(0x31, 0x42);
 178         outb(0x13, 0x42);
 179
 180         init_rtc_irq();
 181 }
 182
 183
 184 /* Validate a computed cycle counter result against the known bounds for
 185    the given processor core.  There's too much brokenness in the way of
 186    timing hardware for any one method to work everywhere.  :-(
 187
 188    Return 0 if the result cannot be trusted, otherwise return the argument.  */
 189
 190 static unsigned long __init
 191 validate_cc_value(unsigned long cc)
 192 {
 193         static struct bounds {
 194                 unsigned int min, max;
 195         } cpu_hz[] __initdata = {
 196                 [EV3_CPU]    = {   50000000,  200000000 },      /* guess */
 197                 [EV4_CPU]    = {  100000000,  300000000 },
 198                 [LCA4_CPU]   = {  100000000,  300000000 },      /* guess */
 199                 [EV45_CPU]   = {  200000000,  300000000 },
 200                 [EV5_CPU]    = {  250000000,  433000000 },
 201                 [EV56_CPU]   = {  333000000,  667000000 },
 202                 [PCA56_CPU]  = {  400000000,  600000000 },      /* guess */
 203                 [PCA57_CPU]  = {  500000000,  600000000 },      /* guess */
 204                 [EV6_CPU]    = {  466000000,  600000000 },
 205                 [EV67_CPU]   = {  600000000,  750000000 },
 206                 [EV68AL_CPU] = {  750000000,  940000000 },
 207                 [EV68CB_CPU] = { 1000000000, 1333333333 },
 208                 /* None of the following are shipping as of 2001-11-01.  */
 209                 [EV68CX_CPU] = { 1000000000, 1700000000 },      /* guess */
 210                 [EV69_CPU]   = { 1000000000, 1700000000 },      /* guess */
 211                 [EV7_CPU]    = {  800000000, 1400000000 },      /* guess */
 212                 [EV79_CPU]   = { 1000000000, 2000000000 },      /* guess */
 213         };
 214
 215         /* Allow for some drift in the crystal.  10MHz is more than enough.  */
 216         const unsigned int deviation = 10000000;
 217
 218         struct percpu_struct *cpu;
 219         unsigned int index;
 220
 221         cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
 222         index = cpu->type & 0xffffffff;
 223
 224         /* If index out of bounds, no way to validate.  */
 225         if (index >= ARRAY_SIZE(cpu_hz))
 226                 return cc;
 227
 228         /* If index contains no data, no way to validate.  */
 229         if (cpu_hz[index].max == 0)
 230                 return cc;
 231
 232         if (cc < cpu_hz[index].min - deviation
 233             || cc > cpu_hz[index].max + deviation)
 234                 return 0;
 235
 236         return cc;
 237 }
 238
 239
 240 /*
 241  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
 242  * arch/i386/time.c.
 243  */
 244
 245 #define CALIBRATE_LATCH 0xffff
 246 #define TIMEOUT_COUNT   0x100000
 247
 248 static unsigned long __init
 249 calibrate_cc_with_pit(void)
 250 {
 251         int cc, count = 0;
 252
 253         /* Set the Gate high, disable speaker */
 254         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 255
 256         /*
 257          * Now let's take care of CTC channel 2
 258          *
 259          * Set the Gate high, program CTC channel 2 for mode 0,
 260          * (interrupt on terminal count mode), binary count,
 261          * load 5 * LATCH count, (LSB and MSB) to begin countdown.
 262          */
 263         outb(0xb0, 0x43);               /* binary, mode 0, LSB/MSB, Ch 2 */
 264         outb(CALIBRATE_LATCH & 0xff, 0x42);     /* LSB of count */
 265         outb(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
 266
 267         cc = rpcc();
 268         do {
 269                 count++;
 270         } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
 271         cc = rpcc() - cc;
 272
 273         /* Error: ECTCNEVERSET or ECPUTOOFAST.  */
 274         if (count <= 1 || count == TIMEOUT_COUNT)
 275                 return 0;
 276
 277         return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
 278 }
 279
 280 /* The Linux interpretation of the CMOS clock register contents:
 281    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
 282    RTC registers show the second which has precisely just started.
 283    Let's hope other operating systems interpret the RTC the same way.  */
 284
 285 static unsigned long __init
 286 rpcc_after_update_in_progress(void)
 287 {
 288         do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
 289         do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
 290
 291         return rpcc();
 292 }
 293
 294 void __init
 295 time_init(void)
 296 {
 297         unsigned int year, mon, day, hour, min, sec, cc1, cc2, epoch;
 298         unsigned long cycle_freq, tolerance;
 299         long diff;
 300
 301         /* Calibrate CPU clock -- attempt #1.  */
 302         if (!est_cycle_freq)
 303                 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
 304
 305         cc1 = rpcc();
 306
 307         /* Calibrate CPU clock -- attempt #2.  */
 308         if (!est_cycle_freq) {
 309                 cc1 = rpcc_after_update_in_progress();
 310                 cc2 = rpcc_after_update_in_progress();
 311                 est_cycle_freq = validate_cc_value(cc2 - cc1);
 312                 cc1 = cc2;
 313         }
 314
 315         cycle_freq = hwrpb->cycle_freq;
 316         if (est_cycle_freq) {
 317                 /* If the given value is within 250 PPM of what we calculated,
 318                    accept it.  Otherwise, use what we found.  */
 319                 tolerance = cycle_freq / 4000;
 320                 diff = cycle_freq - est_cycle_freq;
 321                 if (diff < 0)
 322                         diff = -diff;
 323                 if ((unsigned long)diff > tolerance) {
 324                         cycle_freq = est_cycle_freq;
 325                         printk("HWRPB cycle frequency bogus.  "
 326                                "Estimated %lu Hz\n", cycle_freq);
 327                 } else {
 328                         est_cycle_freq = 0;
 329                 }
 330         } else if (! validate_cc_value (cycle_freq)) {
 331                 printk("HWRPB cycle frequency bogus, "
 332                        "and unable to estimate a proper value!\n");
 333         }
 334
 335         /* From John Bowman <bowman@math.ualberta.ca>: allow the values
 336            to settle, as the Update-In-Progress bit going low isn't good
 337            enough on some hardware.  2ms is our guess; we haven't found
 338            bogomips yet, but this is close on a 500Mhz box.  */
 339         __delay(1000000);
 340
 341         sec = CMOS_READ(RTC_SECONDS);
 342         min = CMOS_READ(RTC_MINUTES);
 343         hour = CMOS_READ(RTC_HOURS);
 344         day = CMOS_READ(RTC_DAY_OF_MONTH);
 345         mon = CMOS_READ(RTC_MONTH);
 346         year = CMOS_READ(RTC_YEAR);
 347
 348         if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 349                 BCD_TO_BIN(sec);
 350                 BCD_TO_BIN(min);
 351                 BCD_TO_BIN(hour);
 352                 BCD_TO_BIN(day);
 353                 BCD_TO_BIN(mon);
 354                 BCD_TO_BIN(year);
 355         }
 356
 357         /* PC-like is standard; used for year >= 70 */
 358         epoch = 1900;
 359         if (year < 20)
 360                 epoch = 2000;
 361         else if (year >= 20 && year < 48)
 362                 /* NT epoch */
 363                 epoch = 1980;
 364         else if (year >= 48 && year < 70)
 365                 /* Digital UNIX epoch */
 366                 epoch = 1952;
 367
 368         printk(KERN_INFO "Using epoch = %d\n", epoch);
 369
 370         if ((year += epoch) < 1970)
 371                 year += 100;
 372
 373         xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
 374         xtime.tv_nsec = 0;
 375
 376         wall_to_monotonic.tv_sec -= xtime.tv_sec;
 377         wall_to_monotonic.tv_nsec = 0;
 378
 379         if (HZ > (1<<16)) {
 380                 extern void __you_loose (void);
 381                 __you_loose();
 382         }
 383
 384         state.last_time = cc1;
 385         state.scaled_ticks_per_cycle
 386                 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
 387         state.last_rtc_update = 0;
 388         state.partial_tick = 0L;
 389
 390         /* Startup the timer source. */
 391         alpha_mv.init_rtc();
 392 }
 393
 394 /*
 395  * Use the cycle counter to estimate an displacement from the last time
 396  * tick.  Unfortunately the Alpha designers made only the low 32-bits of
 397  * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
 398  * part.  So we can't do the "find absolute time in terms of cycles" thing
 399  * that the other ports do.
 400  */
 401 void
 402 do_gettimeofday(struct timeval *tv)
 403 {
 404         unsigned long flags;
 405         unsigned long sec, usec, seq;
 406         unsigned long delta_cycles, delta_usec, partial_tick;
 407
 408         do {
 409                 seq = read_seqbegin_irqsave(&xtime_lock, flags);
 410
 411                 delta_cycles = rpcc() - state.last_time;
 412                 sec = xtime.tv_sec;
 413                 usec = (xtime.tv_nsec / 1000);
 414                 partial_tick = state.partial_tick;
 415
 416         } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
 417
 418 #ifdef CONFIG_SMP
 419         /* Until and unless we figure out how to get cpu cycle counters
 420            in sync and keep them there, we can't use the rpcc tricks.  */
 421         delta_usec = 0;
 422 #else
 423         /*
 424          * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
 425          *      = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
 426          *      = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
 427          *
 428          * which, given a 600MHz cycle and a 1024Hz tick, has a
 429          * dynamic range of about 1.7e17, which is less than the
 430          * 1.8e19 in an unsigned long, so we are safe from overflow.
 431          *
 432          * Round, but with .5 up always, since .5 to even is harder
 433          * with no clear gain.
 434          */
 435
 436         delta_usec = (delta_cycles * state.scaled_ticks_per_cycle
 437                       + partial_tick) * 15625;
 438         delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
 439 #endif
 440
 441         usec += delta_usec;
 442         if (usec >= 1000000) {
 443                 sec += 1;
 444                 usec -= 1000000;
 445         }
 446
 447         tv->tv_sec = sec;
 448         tv->tv_usec = usec;
 449 }
 450
 451 EXPORT_SYMBOL(do_gettimeofday);
 452
 453 int
 454 do_settimeofday(struct timespec *tv)
 455 {
 456         time_t wtm_sec, sec = tv->tv_sec;
 457         long wtm_nsec, nsec = tv->tv_nsec;
 458         unsigned long delta_nsec;
 459
 460         if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
 461                 return -EINVAL;
 462
 463         write_seqlock_irq(&xtime_lock);
 464
 465         /* The offset that is added into time in do_gettimeofday above
 466            must be subtracted out here to keep a coherent view of the
 467            time.  Without this, a full-tick error is possible.  */
 468
 469 #ifdef CONFIG_SMP
 470         delta_nsec = 0;
 471 #else
 472         delta_nsec = rpcc() - state.last_time;
 473         delta_nsec = (delta_nsec * state.scaled_ticks_per_cycle
 474                       + state.partial_tick) * 15625;
 475         delta_nsec = ((delta_nsec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
 476         delta_nsec *= 1000;
 477 #endif
 478
 479         nsec -= delta_nsec;
 480
 481         wtm_sec  = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
 482         wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
 483
 484         set_normalized_timespec(&xtime, sec, nsec);
 485         set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
 486
 487         ntp_clear();
 488
 489         write_sequnlock_irq(&xtime_lock);
 490         clock_was_set();
 491         return 0;
 492 }
 493
 494 EXPORT_SYMBOL(do_settimeofday);
 495
 496
 497 /*
 498  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
 499  * called 500 ms after the second nowtime has started, because when
 500  * nowtime is written into the registers of the CMOS clock, it will
 501  * jump to the next second precisely 500 ms later. Check the Motorola
 502  * MC146818A or Dallas DS12887 data sheet for details.
 503  *
 504  * BUG: This routine does not handle hour overflow properly; it just
 505  *      sets the minutes. Usually you won't notice until after reboot!
 506  */
 507
 508
 509 static int
 510 set_rtc_mmss(unsigned long nowtime)
 511 {
 512         int retval = 0;
 513         int real_seconds, real_minutes, cmos_minutes;
 514         unsigned char save_control, save_freq_select;
 515
 516         /* irq are locally disabled here */
 517         spin_lock(&rtc_lock);
 518         /* Tell the clock it's being set */
 519         save_control = CMOS_READ(RTC_CONTROL);
 520         CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
 521
 522         /* Stop and reset prescaler */
 523         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
 524         CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
 525
 526         cmos_minutes = CMOS_READ(RTC_MINUTES);
 527         if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
 528                 BCD_TO_BIN(cmos_minutes);
 529
 530         /*
 531          * since we're only adjusting minutes and seconds,
 532          * don't interfere with hour overflow. This avoids
 533          * messing with unknown time zones but requires your
 534          * RTC not to be off by more than 15 minutes
 535          */
 536         real_seconds = nowtime % 60;
 537         real_minutes = nowtime / 60;
 538         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
 539                 /* correct for half hour time zone */
 540                 real_minutes += 30;
 541         }
 542         real_minutes %= 60;
 543
 544         if (abs(real_minutes - cmos_minutes) < 30) {
 545                 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 546                         BIN_TO_BCD(real_seconds);
 547                         BIN_TO_BCD(real_minutes);
 548                 }
 549                 CMOS_WRITE(real_seconds,RTC_SECONDS);
 550                 CMOS_WRITE(real_minutes,RTC_MINUTES);
 551         } else {
 552                 printk(KERN_WARNING
 553                        "set_rtc_mmss: can't update from %d to %d\n",
 554                        cmos_minutes, real_minutes);
 555                 retval = -1;
 556         }
 557
 558         /* The following flags have to be released exactly in this order,
 559          * otherwise the DS12887 (popular MC146818A clone with integrated
 560          * battery and quartz) will not reset the oscillator and will not
 561          * update precisely 500 ms later. You won't find this mentioned in
 562          * the Dallas Semiconductor data sheets, but who believes data
 563          * sheets anyway ...                           -- Markus Kuhn
 564          */
 565         CMOS_WRITE(save_control, RTC_CONTROL);
 566         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 567         spin_unlock(&rtc_lock);
 568
 569         return retval;
 570 }