arch/arm/mach-pxa/cpu-pxa.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/cpu-pxa.c
   3  *
   4  *  Copyright (C) 2002,2003 Intrinsyc Software
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  * History:
  21  *   31-Jul-2002 : Initial version [FB]
  22  *   29-Jan-2003 : added PXA255 support [FB]
  23  *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
  24  *
  25  * Note:
  26  *   This driver may change the memory bus clock rate, but will not do any
  27  *   platform specific access timing changes... for example if you have flash
  28  *   memory connected to CS0, you will need to register a platform specific
  29  *   notifier which will adjust the memory access strobes to maintain a
  30  *   minimum strobe width.
  31  *
  32  */
  33
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/sched.h>
  37 #include <linux/init.h>
  38 #include <linux/cpufreq.h>
  39
  40 #include <asm/hardware.h>
  41 #include <asm/arch/pxa-regs.h>
  42 #include <asm/arch/pxa2xx-regs.h>
  43
  44 #ifdef DEBUG
  45 static unsigned int freq_debug;
  46 <<<<<<< HEAD:arch/arm/mach-pxa/cpu-pxa.c
  47 MODULE_PARM(freq_debug, "i");
  48 =======
  49 module_param(freq_debug, uint, 0);
  50 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-pxa/cpu-pxa.c
  51 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
  52 #else
  53 #define freq_debug  0
  54 #endif
  55
  56 typedef struct {
  57         unsigned int khz;
  58         unsigned int membus;
  59         unsigned int cccr;
  60         unsigned int div2;
  61 } pxa_freqs_t;
  62
  63 /* Define the refresh period in mSec for the SDRAM and the number of rows */
  64 #define SDRAM_TREF          64      /* standard 64ms SDRAM */
  65 #define SDRAM_ROWS          4096    /* 64MB=8192 32MB=4096 */
  66 #define MDREFR_DRI(x)       (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
  67
  68 #define CCLKCFG_TURBO       0x1
  69 #define CCLKCFG_FCS         0x2
  70 #define PXA25x_MIN_FREQ     99500
  71 #define PXA25x_MAX_FREQ     398100
  72 #define MDREFR_DB2_MASK     (MDREFR_K2DB2 | MDREFR_K1DB2)
  73 #define MDREFR_DRI_MASK     0xFFF
  74
  75
  76 /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
  77 static pxa_freqs_t pxa255_run_freqs[] =
  78 {
  79     /* CPU   MEMBUS  CCCR  DIV2*/
  80     { 99500,  99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50,  SDRAM=50 */
  81     {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66,  SDRAM=66 */
  82     {199100,  99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99,  SDRAM=99 */
  83     {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
  84     {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
  85     {398100,  99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
  86     {0,}
  87 };
  88 #define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
  89
  90 static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
  91
  92 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
  93 static pxa_freqs_t pxa255_turbo_freqs[] =
  94 {
  95     /* CPU   MEMBUS  CCCR  DIV2*/
  96     { 99500, 99500,  0x121, 1}, /* run=99,  turbo= 99, PXbus=50, SDRAM=50 */
  97     {199100, 99500,  0x221, 0}, /* run=99,  turbo=199, PXbus=50, SDRAM=99 */
  98     {298500, 99500,  0x321, 0}, /* run=99,  turbo=287, PXbus=50, SDRAM=99 */
  99     {298600, 99500,  0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
 100     {398100, 99500,  0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
 101     {0,}
 102 };
 103 #define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
 104
 105 static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
 106
 107 extern unsigned get_clk_frequency_khz(int info);
 108
 109 /* find a valid frequency point */
 110 static int pxa_verify_policy(struct cpufreq_policy *policy)
 111 {
 112         struct cpufreq_frequency_table *pxa_freqs_table;
 113         int ret;
 114
 115         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
 116                 pxa_freqs_table = pxa255_run_freq_table;
 117         } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
 118                 pxa_freqs_table = pxa255_turbo_freq_table;
 119         } else {
 120                 printk("CPU PXA: Unknown policy found. "
 121                        "Using CPUFREQ_POLICY_PERFORMANCE\n");
 122                 pxa_freqs_table = pxa255_run_freq_table;
 123         }
 124
 125         ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
 126
 127         if (freq_debug)
 128                 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
 129                        policy->min, policy->max);
 130
 131         return ret;
 132 }
 133
 134 static int pxa_set_target(struct cpufreq_policy *policy,
 135                            unsigned int target_freq,
 136                            unsigned int relation)
 137 {
 138         struct cpufreq_frequency_table *pxa_freqs_table;
 139         pxa_freqs_t *pxa_freq_settings;
 140         struct cpufreq_freqs freqs;
 141 <<<<<<< HEAD:arch/arm/mach-pxa/cpu-pxa.c
 142         int idx;
 143 =======
 144         unsigned int idx;
 145 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-pxa/cpu-pxa.c
 146         unsigned long flags;
 147         unsigned int unused, preset_mdrefr, postset_mdrefr;
 148         void *ramstart = phys_to_virt(0xa0000000);
 149
 150         /* Get the current policy */
 151         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
 152                 pxa_freq_settings = pxa255_run_freqs;
 153                 pxa_freqs_table   = pxa255_run_freq_table;
 154         } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
 155                 pxa_freq_settings = pxa255_turbo_freqs;
 156                 pxa_freqs_table   = pxa255_turbo_freq_table;
 157         } else {
 158                 printk("CPU PXA: Unknown policy found. "
 159                        "Using CPUFREQ_POLICY_PERFORMANCE\n");
 160                 pxa_freq_settings = pxa255_run_freqs;
 161                 pxa_freqs_table   = pxa255_run_freq_table;
 162         }
 163
 164         /* Lookup the next frequency */
 165         if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
 166                                            target_freq, relation, &idx)) {
 167                 return -EINVAL;
 168         }
 169
 170         freqs.old = policy->cur;
 171         freqs.new = pxa_freq_settings[idx].khz;
 172         freqs.cpu = policy->cpu;
 173
 174         if (freq_debug)
 175                 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
 176                        freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
 177                        (pxa_freq_settings[idx].membus / 2000) :
 178                        (pxa_freq_settings[idx].membus / 1000));
 179
 180         /*
 181          * Tell everyone what we're about to do...
 182          * you should add a notify client with any platform specific
 183          * Vcc changing capability
 184          */
 185         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 186
 187         /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
 188          * we need to preset the smaller DRI before the change.  If we're speeding
 189          * up we need to set the larger DRI value after the change.
 190          */
 191         preset_mdrefr = postset_mdrefr = MDREFR;
 192         if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
 193                 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
 194                                 MDREFR_DRI(pxa_freq_settings[idx].membus);
 195         }
 196         postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
 197                             MDREFR_DRI(pxa_freq_settings[idx].membus);
 198
 199         /* If we're dividing the memory clock by two for the SDRAM clock, this
 200          * must be set prior to the change.  Clearing the divide must be done
 201          * after the change.
 202          */
 203         if (pxa_freq_settings[idx].div2) {
 204                 preset_mdrefr  |= MDREFR_DB2_MASK;
 205                 postset_mdrefr |= MDREFR_DB2_MASK;
 206         } else {
 207                 postset_mdrefr &= ~MDREFR_DB2_MASK;
 208         }
 209
 210         local_irq_save(flags);
 211
 212         /* Set new the CCCR */
 213         CCCR = pxa_freq_settings[idx].cccr;
 214
 215         asm volatile("                                                  \n\
 216                 ldr     r4, [%1]                /* load MDREFR */       \n\
 217                 b       2f                                              \n\
 218                 .align  5                                               \n\
 219 1:                                                                      \n\
 220                 str     %4, [%1]                /* preset the MDREFR */ \n\
 221                 mcr     p14, 0, %2, c6, c0, 0   /* set CCLKCFG[FCS] */  \n\
 222                 str     %5, [%1]                /* postset the MDREFR */ \n\
 223                                                                         \n\
 224                 b       3f                                              \n\
 225 2:              b       1b                                              \n\
 226 3:              nop                                                     \n\
 227           "
 228           : "=&r" (unused)
 229           : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
 230             "r" (preset_mdrefr), "r" (postset_mdrefr)
 231           : "r4", "r5");
 232         local_irq_restore(flags);
 233
 234         /*
 235          * Tell everyone what we've just done...
 236          * you should add a notify client with any platform specific
 237          * SDRAM refresh timer adjustments
 238          */
 239         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 240
 241         return 0;
 242 }
 243
 244 <<<<<<< HEAD:arch/arm/mach-pxa/cpu-pxa.c
 245 =======
 246 static unsigned int pxa_cpufreq_get(unsigned int cpu)
 247 {
 248         return get_clk_frequency_khz(0);
 249 }
 250
 251 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-pxa/cpu-pxa.c
 252 static int pxa_cpufreq_init(struct cpufreq_policy *policy)
 253 {
 254         int i;
 255
 256         /* set default policy and cpuinfo */
 257         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 258         policy->policy = CPUFREQ_POLICY_PERFORMANCE;
 259         policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
 260         policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
 261         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
 262         policy->cur = get_clk_frequency_khz(0);    /* current freq */
 263         policy->min = policy->max = policy->cur;
 264
 265         /* Generate the run cpufreq_frequency_table struct */
 266         for (i = 0; i < NUM_RUN_FREQS; i++) {
 267                 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
 268                 pxa255_run_freq_table[i].index = i;
 269         }
 270
 271         pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
 272         /* Generate the turbo cpufreq_frequency_table struct */
 273         for (i = 0; i < NUM_TURBO_FREQS; i++) {
 274                 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
 275                 pxa255_turbo_freq_table[i].index = i;
 276         }
 277         pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
 278
 279         printk(KERN_INFO "PXA CPU frequency change support initialized\n");
 280
 281         return 0;
 282 }
 283
 284 static struct cpufreq_driver pxa_cpufreq_driver = {
 285         .verify = pxa_verify_policy,
 286         .target = pxa_set_target,
 287         .init   = pxa_cpufreq_init,
 288 <<<<<<< HEAD:arch/arm/mach-pxa/cpu-pxa.c
 289 =======
 290         .get    = pxa_cpufreq_get,
 291 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-pxa/cpu-pxa.c
 292         .name   = "PXA25x",
 293 };
 294
 295 static int __init pxa_cpu_init(void)
 296 {
 297         int ret = -ENODEV;
 298         if (cpu_is_pxa25x())
 299                 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
 300         return ret;
 301 }
 302
 303 static void __exit pxa_cpu_exit(void)
 304 {
 305         if (cpu_is_pxa25x())
 306                 cpufreq_unregister_driver(&pxa_cpufreq_driver);
 307 }
 308
 309
 310 MODULE_AUTHOR ("Intrinsyc Software Inc.");
 311 MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
 312 MODULE_LICENSE("GPL");
 313 module_init(pxa_cpu_init);
 314 module_exit(pxa_cpu_exit);