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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / arm / plat-s3c24xx / dma.c
blobe75dfd3ec00570745e55f9adb9c1efd84100bfa4
1 /* linux/arch/arm/plat-s3c24xx/dma.c
2 *
3 * Copyright (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA core
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
17 #define DEBUG
18 #endif
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/delay.h>
29
30 #include <asm/system.h>
31 #include <asm/irq.h>
32 #include <asm/hardware.h>
33 #include <asm/io.h>
34 #include <asm/dma.h>
35
36 #include <asm/mach/dma.h>
37 #include <asm/arch/map.h>
38
39 #include <asm/plat-s3c24xx/dma.h>
40
41 /* io map for dma */
42 static void __iomem *dma_base;
43 static struct kmem_cache *dma_kmem;
44
45 static int dma_channels;
46
47 static struct s3c24xx_dma_selection dma_sel;
48
49 /* dma channel state information */
50 struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
51
52 /* debugging functions */
53
54 #define BUF_MAGIC (0xcafebabe)
55
56 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
57
58 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
59
60 #if 1
61 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
62 #else
63 static inline void
64 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
65 {
66 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
67 writel(val, dma_regaddr(chan, reg));
68 }
69 #endif
70
71 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
72
73 /* captured register state for debug */
74
75 struct s3c2410_dma_regstate {
76 unsigned long dcsrc;
77 unsigned long disrc;
78 unsigned long dstat;
79 unsigned long dcon;
80 unsigned long dmsktrig;
81 };
82
83 #ifdef CONFIG_S3C2410_DMA_DEBUG
84
85 /* dmadbg_showregs
86 *
87 * simple debug routine to print the current state of the dma registers
88 */
89
90 static void
91 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
92 {
93 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
94 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
95 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
96 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
97 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
98 }
99
100 static void
101 dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
102 struct s3c2410_dma_regstate *regs)
103 {
104 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
105 chan->number, fname, line,
106 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
107 regs->dcon);
108 }
109
110 static void
111 dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
112 {
113 struct s3c2410_dma_regstate state;
114
115 dmadbg_capture(chan, &state);
116
117 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
118 chan->number, fname, line, chan->load_state,
119 chan->curr, chan->next, chan->end);
120
121 dmadbg_dumpregs(fname, line, chan, &state);
122 }
123
124 static void
125 dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
126 {
127 struct s3c2410_dma_regstate state;
128
129 dmadbg_capture(chan, &state);
130 dmadbg_dumpregs(fname, line, chan, &state);
131 }
132
133 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
134 #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
135 #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
136 =======
137 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
138 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
139 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
140 #else
141 #define dbg_showregs(chan) do { } while(0)
142 #define dbg_showchan(chan) do { } while(0)
143 #endif /* CONFIG_S3C2410_DMA_DEBUG */
144
145 static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
146
147 /* lookup_dma_channel
148 *
149 * change the dma channel number given into a real dma channel id
150 */
151
152 static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
153 {
154 if (channel & DMACH_LOW_LEVEL)
155 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
156 else
157 return dma_chan_map[channel];
158 }
159
160 /* s3c2410_dma_stats_timeout
161 *
162 * Update DMA stats from timeout info
163 */
164
165 static void
166 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
167 {
168 if (stats == NULL)
169 return;
170
171 if (val > stats->timeout_longest)
172 stats->timeout_longest = val;
173 if (val < stats->timeout_shortest)
174 stats->timeout_shortest = val;
175
176 stats->timeout_avg += val;
177 }
178
179 /* s3c2410_dma_waitforload
180 *
181 * wait for the DMA engine to load a buffer, and update the state accordingly
182 */
183
184 static int
185 s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
186 {
187 int timeout = chan->load_timeout;
188 int took;
189
190 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
191 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
192 return 0;
193 }
194
195 if (chan->stats != NULL)
196 chan->stats->loads++;
197
198 while (--timeout > 0) {
199 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
200 took = chan->load_timeout - timeout;
201
202 s3c2410_dma_stats_timeout(chan->stats, took);
203
204 switch (chan->load_state) {
205 case S3C2410_DMALOAD_1LOADED:
206 chan->load_state = S3C2410_DMALOAD_1RUNNING;
207 break;
208
209 default:
210 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
211 }
212
213 return 1;
214 }
215 }
216
217 if (chan->stats != NULL) {
218 chan->stats->timeout_failed++;
219 }
220
221 return 0;
222 }
223
224
225
226 /* s3c2410_dma_loadbuffer
227 *
228 * load a buffer, and update the channel state
229 */
230
231 static inline int
232 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
233 struct s3c2410_dma_buf *buf)
234 {
235 unsigned long reload;
236
237 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
238 buf, (unsigned long)buf->data, buf->size);
239
240 if (buf == NULL) {
241 dmawarn("buffer is NULL\n");
242 return -EINVAL;
243 }
244
245 /* check the state of the channel before we do anything */
246
247 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
248 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
249 }
250
251 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
252 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
253 }
254
255 /* it would seem sensible if we are the last buffer to not bother
256 * with the auto-reload bit, so that the DMA engine will not try
257 * and load another transfer after this one has finished...
258 */
259 if (chan->load_state == S3C2410_DMALOAD_NONE) {
260 pr_debug("load_state is none, checking for noreload (next=%p)\n",
261 buf->next);
262 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
263 } else {
264 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
265 reload = S3C2410_DCON_AUTORELOAD;
266 }
267
268 if ((buf->data & 0xf0000000) != 0x30000000) {
269 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
270 }
271
272 writel(buf->data, chan->addr_reg);
273
274 dma_wrreg(chan, S3C2410_DMA_DCON,
275 chan->dcon | reload | (buf->size/chan->xfer_unit));
276
277 chan->next = buf->next;
278
279 /* update the state of the channel */
280
281 switch (chan->load_state) {
282 case S3C2410_DMALOAD_NONE:
283 chan->load_state = S3C2410_DMALOAD_1LOADED;
284 break;
285
286 case S3C2410_DMALOAD_1RUNNING:
287 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
288 break;
289
290 default:
291 dmawarn("dmaload: unknown state %d in loadbuffer\n",
292 chan->load_state);
293 break;
294 }
295
296 return 0;
297 }
298
299 /* s3c2410_dma_call_op
300 *
301 * small routine to call the op routine with the given op if it has been
302 * registered
303 */
304
305 static void
306 s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
307 {
308 if (chan->op_fn != NULL) {
309 (chan->op_fn)(chan, op);
310 }
311 }
312
313 /* s3c2410_dma_buffdone
314 *
315 * small wrapper to check if callback routine needs to be called, and
316 * if so, call it
317 */
318
319 static inline void
320 s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
321 enum s3c2410_dma_buffresult result)
322 {
323 #if 0
324 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
325 chan->callback_fn, buf, buf->id, buf->size, result);
326 #endif
327
328 if (chan->callback_fn != NULL) {
329 (chan->callback_fn)(chan, buf->id, buf->size, result);
330 }
331 }
332
333 /* s3c2410_dma_start
334 *
335 * start a dma channel going
336 */
337
338 static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
339 {
340 unsigned long tmp;
341 unsigned long flags;
342
343 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
344
345 local_irq_save(flags);
346
347 if (chan->state == S3C2410_DMA_RUNNING) {
348 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
349 local_irq_restore(flags);
350 return 0;
351 }
352
353 chan->state = S3C2410_DMA_RUNNING;
354
355 /* check wether there is anything to load, and if not, see
356 * if we can find anything to load
357 */
358
359 if (chan->load_state == S3C2410_DMALOAD_NONE) {
360 if (chan->next == NULL) {
361 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
362 chan->number);
363 chan->state = S3C2410_DMA_IDLE;
364 local_irq_restore(flags);
365 return -EINVAL;
366 }
367
368 s3c2410_dma_loadbuffer(chan, chan->next);
369 }
370
371 dbg_showchan(chan);
372
373 /* enable the channel */
374
375 if (!chan->irq_enabled) {
376 enable_irq(chan->irq);
377 chan->irq_enabled = 1;
378 }
379
380 /* start the channel going */
381
382 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
383 tmp &= ~S3C2410_DMASKTRIG_STOP;
384 tmp |= S3C2410_DMASKTRIG_ON;
385 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
386
387 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
388
389 #if 0
390 /* the dma buffer loads should take care of clearing the AUTO
391 * reloading feature */
392 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
393 tmp &= ~S3C2410_DCON_NORELOAD;
394 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
395 #endif
396
397 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
398
399 dbg_showchan(chan);
400
401 /* if we've only loaded one buffer onto the channel, then chec
402 * to see if we have another, and if so, try and load it so when
403 * the first buffer is finished, the new one will be loaded onto
404 * the channel */
405
406 if (chan->next != NULL) {
407 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
408
409 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
410 pr_debug("%s: buff not yet loaded, no more todo\n",
411 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
412 __FUNCTION__);
413 =======
414 __func__);
415 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
416 } else {
417 chan->load_state = S3C2410_DMALOAD_1RUNNING;
418 s3c2410_dma_loadbuffer(chan, chan->next);
419 }
420
421 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
422 s3c2410_dma_loadbuffer(chan, chan->next);
423 }
424 }
425
426
427 local_irq_restore(flags);
428
429 return 0;
430 }
431
432 /* s3c2410_dma_canload
433 *
434 * work out if we can queue another buffer into the DMA engine
435 */
436
437 static int
438 s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
439 {
440 if (chan->load_state == S3C2410_DMALOAD_NONE ||
441 chan->load_state == S3C2410_DMALOAD_1RUNNING)
442 return 1;
443
444 return 0;
445 }
446
447 /* s3c2410_dma_enqueue
448 *
449 * queue an given buffer for dma transfer.
450 *
451 * id the device driver's id information for this buffer
452 * data the physical address of the buffer data
453 * size the size of the buffer in bytes
454 *
455 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
456 * is checked, and if set, the channel is started. If this flag isn't set,
457 * then an error will be returned.
458 *
459 * It is possible to queue more than one DMA buffer onto a channel at
460 * once, and the code will deal with the re-loading of the next buffer
461 * when necessary.
462 */
463
464 int s3c2410_dma_enqueue(unsigned int channel, void *id,
465 dma_addr_t data, int size)
466 {
467 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
468 struct s3c2410_dma_buf *buf;
469 unsigned long flags;
470
471 if (chan == NULL)
472 return -EINVAL;
473
474 pr_debug("%s: id=%p, data=%08x, size=%d\n",
475 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
476 __FUNCTION__, id, (unsigned int)data, size);
477 =======
478 __func__, id, (unsigned int)data, size);
479 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
480
481 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
482 if (buf == NULL) {
483 pr_debug("%s: out of memory (%ld alloc)\n",
484 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
485 __FUNCTION__, (long)sizeof(*buf));
486 =======
487 __func__, (long)sizeof(*buf));
488 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
489 return -ENOMEM;
490 }
491
492 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
493 //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
494 =======
495 //pr_debug("%s: new buffer %p\n", __func__, buf);
496 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
497 //dbg_showchan(chan);
498
499 buf->next = NULL;
500 buf->data = buf->ptr = data;
501 buf->size = size;
502 buf->id = id;
503 buf->magic = BUF_MAGIC;
504
505 local_irq_save(flags);
506
507 if (chan->curr == NULL) {
508 /* we've got nothing loaded... */
509 pr_debug("%s: buffer %p queued onto empty channel\n",
510 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
511 __FUNCTION__, buf);
512 =======
513 __func__, buf);
514 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
515
516 chan->curr = buf;
517 chan->end = buf;
518 chan->next = NULL;
519 } else {
520 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
521 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
522 chan->number, __FUNCTION__, buf);
523 =======
524 chan->number, __func__, buf);
525 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
526
527 if (chan->end == NULL)
528 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
529 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
530 chan->number, __FUNCTION__, chan);
531 =======
532 chan->number, __func__, chan);
533 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
534
535 chan->end->next = buf;
536 chan->end = buf;
537 }
538
539 /* if necessary, update the next buffer field */
540 if (chan->next == NULL)
541 chan->next = buf;
542
543 /* check to see if we can load a buffer */
544 if (chan->state == S3C2410_DMA_RUNNING) {
545 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
546 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
547 printk(KERN_ERR "dma%d: loadbuffer:"
548 "timeout loading buffer\n",
549 chan->number);
550 dbg_showchan(chan);
551 local_irq_restore(flags);
552 return -EINVAL;
553 }
554 }
555
556 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
557 s3c2410_dma_loadbuffer(chan, chan->next);
558 }
559 } else if (chan->state == S3C2410_DMA_IDLE) {
560 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
561 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
562 S3C2410_DMAOP_START);
563 }
564 }
565
566 local_irq_restore(flags);
567 return 0;
568 }
569
570 EXPORT_SYMBOL(s3c2410_dma_enqueue);
571
572 static inline void
573 s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
574 {
575 int magicok = (buf->magic == BUF_MAGIC);
576
577 buf->magic = -1;
578
579 if (magicok) {
580 kmem_cache_free(dma_kmem, buf);
581 } else {
582 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
583 }
584 }
585
586 /* s3c2410_dma_lastxfer
587 *
588 * called when the system is out of buffers, to ensure that the channel
589 * is prepared for shutdown.
590 */
591
592 static inline void
593 s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
594 {
595 #if 0
596 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
597 chan->number, chan->load_state);
598 #endif
599
600 switch (chan->load_state) {
601 case S3C2410_DMALOAD_NONE:
602 break;
603
604 case S3C2410_DMALOAD_1LOADED:
605 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
606 /* flag error? */
607 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
608 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
609 chan->number, __FUNCTION__);
610 =======
611 chan->number, __func__);
612 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
613 return;
614 }
615 break;
616
617 case S3C2410_DMALOAD_1LOADED_1RUNNING:
618 /* I belive in this case we do not have anything to do
619 * until the next buffer comes along, and we turn off the
620 * reload */
621 return;
622
623 default:
624 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
625 chan->number, chan->load_state);
626 return;
627
628 }
629
630 /* hopefully this'll shut the damned thing up after the transfer... */
631 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
632 }
633
634
635 #define dmadbg2(x...)
636
637 static irqreturn_t
638 s3c2410_dma_irq(int irq, void *devpw)
639 {
640 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
641 struct s3c2410_dma_buf *buf;
642
643 buf = chan->curr;
644
645 dbg_showchan(chan);
646
647 /* modify the channel state */
648
649 switch (chan->load_state) {
650 case S3C2410_DMALOAD_1RUNNING:
651 /* TODO - if we are running only one buffer, we probably
652 * want to reload here, and then worry about the buffer
653 * callback */
654
655 chan->load_state = S3C2410_DMALOAD_NONE;
656 break;
657
658 case S3C2410_DMALOAD_1LOADED:
659 /* iirc, we should go back to NONE loaded here, we
660 * had a buffer, and it was never verified as being
661 * loaded.
662 */
663
664 chan->load_state = S3C2410_DMALOAD_NONE;
665 break;
666
667 case S3C2410_DMALOAD_1LOADED_1RUNNING:
668 /* we'll worry about checking to see if another buffer is
669 * ready after we've called back the owner. This should
670 * ensure we do not wait around too long for the DMA
671 * engine to start the next transfer
672 */
673
674 chan->load_state = S3C2410_DMALOAD_1LOADED;
675 break;
676
677 case S3C2410_DMALOAD_NONE:
678 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
679 chan->number);
680 break;
681
682 default:
683 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
684 chan->number, chan->load_state);
685 break;
686 }
687
688 if (buf != NULL) {
689 /* update the chain to make sure that if we load any more
690 * buffers when we call the callback function, things should
691 * work properly */
692
693 chan->curr = buf->next;
694 buf->next = NULL;
695
696 if (buf->magic != BUF_MAGIC) {
697 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
698 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
699 chan->number, __FUNCTION__, buf);
700 =======
701 chan->number, __func__, buf);
702 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
703 return IRQ_HANDLED;
704 }
705
706 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
707
708 /* free resouces */
709 s3c2410_dma_freebuf(buf);
710 } else {
711 }
712
713 /* only reload if the channel is still running... our buffer done
714 * routine may have altered the state by requesting the dma channel
715 * to stop or shutdown... */
716
717 /* todo: check that when the channel is shut-down from inside this
718 * function, we cope with unsetting reload, etc */
719
720 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
721 unsigned long flags;
722
723 switch (chan->load_state) {
724 case S3C2410_DMALOAD_1RUNNING:
725 /* don't need to do anything for this state */
726 break;
727
728 case S3C2410_DMALOAD_NONE:
729 /* can load buffer immediately */
730 break;
731
732 case S3C2410_DMALOAD_1LOADED:
733 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
734 /* flag error? */
735 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
736 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
737 chan->number, __FUNCTION__);
738 =======
739 chan->number, __func__);
740 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
741 return IRQ_HANDLED;
742 }
743
744 break;
745
746 case S3C2410_DMALOAD_1LOADED_1RUNNING:
747 goto no_load;
748
749 default:
750 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
751 chan->number, chan->load_state);
752 return IRQ_HANDLED;
753 }
754
755 local_irq_save(flags);
756 s3c2410_dma_loadbuffer(chan, chan->next);
757 local_irq_restore(flags);
758 } else {
759 s3c2410_dma_lastxfer(chan);
760
761 /* see if we can stop this channel.. */
762 if (chan->load_state == S3C2410_DMALOAD_NONE) {
763 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
764 chan->number, jiffies);
765 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
766 S3C2410_DMAOP_STOP);
767 }
768 }
769
770 no_load:
771 return IRQ_HANDLED;
772 }
773
774 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
775
776 /* s3c2410_request_dma
777 *
778 * get control of an dma channel
779 */
780
781 int s3c2410_dma_request(unsigned int channel,
782 struct s3c2410_dma_client *client,
783 void *dev)
784 {
785 struct s3c2410_dma_chan *chan;
786 unsigned long flags;
787 int err;
788
789 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
790 channel, client->name, dev);
791
792 local_irq_save(flags);
793
794 chan = s3c2410_dma_map_channel(channel);
795 if (chan == NULL) {
796 local_irq_restore(flags);
797 return -EBUSY;
798 }
799
800 dbg_showchan(chan);
801
802 chan->client = client;
803 chan->in_use = 1;
804
805 if (!chan->irq_claimed) {
806 pr_debug("dma%d: %s : requesting irq %d\n",
807 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
808 channel, __FUNCTION__, chan->irq);
809 =======
810 channel, __func__, chan->irq);
811 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
812
813 chan->irq_claimed = 1;
814 local_irq_restore(flags);
815
816 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
817 client->name, (void *)chan);
818
819 local_irq_save(flags);
820
821 if (err) {
822 chan->in_use = 0;
823 chan->irq_claimed = 0;
824 local_irq_restore(flags);
825
826 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
827 client->name, chan->irq, chan->number);
828 return err;
829 }
830
831 chan->irq_enabled = 1;
832 }
833
834 local_irq_restore(flags);
835
836 /* need to setup */
837
838 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
839 pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
840 =======
841 pr_debug("%s: channel initialised, %p\n", __func__, chan);
842 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
843
844 return chan->number | DMACH_LOW_LEVEL;
845 }
846
847 EXPORT_SYMBOL(s3c2410_dma_request);
848
849 /* s3c2410_dma_free
850 *
851 * release the given channel back to the system, will stop and flush
852 * any outstanding transfers, and ensure the channel is ready for the
853 * next claimant.
854 *
855 * Note, although a warning is currently printed if the freeing client
856 * info is not the same as the registrant's client info, the free is still
857 * allowed to go through.
858 */
859
860 int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
861 {
862 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
863 unsigned long flags;
864
865 if (chan == NULL)
866 return -EINVAL;
867
868 local_irq_save(flags);
869
870 if (chan->client != client) {
871 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
872 channel, chan->client, client);
873 }
874
875 /* sort out stopping and freeing the channel */
876
877 if (chan->state != S3C2410_DMA_IDLE) {
878 pr_debug("%s: need to stop dma channel %p\n",
879 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
880 __FUNCTION__, chan);
881 =======
882 __func__, chan);
883 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
884
885 /* possibly flush the channel */
886 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
887 }
888
889 chan->client = NULL;
890 chan->in_use = 0;
891
892 if (chan->irq_claimed)
893 free_irq(chan->irq, (void *)chan);
894
895 chan->irq_claimed = 0;
896
897 if (!(channel & DMACH_LOW_LEVEL))
898 dma_chan_map[channel] = NULL;
899
900 local_irq_restore(flags);
901
902 return 0;
903 }
904
905 EXPORT_SYMBOL(s3c2410_dma_free);
906
907 static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
908 {
909 unsigned long flags;
910 unsigned long tmp;
911
912 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
913 pr_debug("%s:\n", __FUNCTION__);
914 =======
915 pr_debug("%s:\n", __func__);
916 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
917
918 dbg_showchan(chan);
919
920 local_irq_save(flags);
921
922 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
923
924 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
925 tmp |= S3C2410_DMASKTRIG_STOP;
926 //tmp &= ~S3C2410_DMASKTRIG_ON;
927 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
928
929 #if 0
930 /* should also clear interrupts, according to WinCE BSP */
931 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
932 tmp |= S3C2410_DCON_NORELOAD;
933 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
934 #endif
935
936 /* should stop do this, or should we wait for flush? */
937 chan->state = S3C2410_DMA_IDLE;
938 chan->load_state = S3C2410_DMALOAD_NONE;
939
940 local_irq_restore(flags);
941
942 return 0;
943 }
944
945 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
946 {
947 unsigned long tmp;
948 unsigned int timeout = 0x10000;
949
950 while (timeout-- > 0) {
951 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
952
953 if (!(tmp & S3C2410_DMASKTRIG_ON))
954 return;
955 }
956
957 pr_debug("dma%d: failed to stop?\n", chan->number);
958 }
959
960
961 /* s3c2410_dma_flush
962 *
963 * stop the channel, and remove all current and pending transfers
964 */
965
966 static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
967 {
968 struct s3c2410_dma_buf *buf, *next;
969 unsigned long flags;
970
971 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
972 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
973 =======
974 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
975 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
976
977 dbg_showchan(chan);
978
979 local_irq_save(flags);
980
981 if (chan->state != S3C2410_DMA_IDLE) {
982 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
983 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
984 =======
985 pr_debug("%s: stopping channel...\n", __func__ );
986 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
987 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
988 }
989
990 buf = chan->curr;
991 if (buf == NULL)
992 buf = chan->next;
993
994 chan->curr = chan->next = chan->end = NULL;
995
996 if (buf != NULL) {
997 for ( ; buf != NULL; buf = next) {
998 next = buf->next;
999
1000 pr_debug("%s: free buffer %p, next %p\n",
1001 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1002 __FUNCTION__, buf, buf->next);
1003 =======
1004 __func__, buf, buf->next);
1005 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1006
1007 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
1008 s3c2410_dma_freebuf(buf);
1009 }
1010 }
1011
1012 dbg_showregs(chan);
1013
1014 s3c2410_dma_waitforstop(chan);
1015
1016 #if 0
1017 /* should also clear interrupts, according to WinCE BSP */
1018 {
1019 unsigned long tmp;
1020
1021 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
1022 tmp |= S3C2410_DCON_NORELOAD;
1023 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
1024 }
1025 #endif
1026
1027 dbg_showregs(chan);
1028
1029 local_irq_restore(flags);
1030
1031 return 0;
1032 }
1033
1034 static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
1035 {
1036 unsigned long flags;
1037
1038 local_irq_save(flags);
1039
1040 dbg_showchan(chan);
1041
1042 /* if we've only loaded one buffer onto the channel, then chec
1043 * to see if we have another, and if so, try and load it so when
1044 * the first buffer is finished, the new one will be loaded onto
1045 * the channel */
1046
1047 if (chan->next != NULL) {
1048 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
1049
1050 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
1051 pr_debug("%s: buff not yet loaded, no more todo\n",
1052 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1053 __FUNCTION__);
1054 =======
1055 __func__);
1056 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1057 } else {
1058 chan->load_state = S3C2410_DMALOAD_1RUNNING;
1059 s3c2410_dma_loadbuffer(chan, chan->next);
1060 }
1061
1062 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
1063 s3c2410_dma_loadbuffer(chan, chan->next);
1064 }
1065 }
1066
1067
1068 local_irq_restore(flags);
1069
1070 return 0;
1071
1072 }
1073
1074 int
1075 s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
1076 {
1077 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1078
1079 if (chan == NULL)
1080 return -EINVAL;
1081
1082 switch (op) {
1083 case S3C2410_DMAOP_START:
1084 return s3c2410_dma_start(chan);
1085
1086 case S3C2410_DMAOP_STOP:
1087 return s3c2410_dma_dostop(chan);
1088
1089 case S3C2410_DMAOP_PAUSE:
1090 case S3C2410_DMAOP_RESUME:
1091 return -ENOENT;
1092
1093 case S3C2410_DMAOP_FLUSH:
1094 return s3c2410_dma_flush(chan);
1095
1096 case S3C2410_DMAOP_STARTED:
1097 return s3c2410_dma_started(chan);
1098
1099 case S3C2410_DMAOP_TIMEOUT:
1100 return 0;
1101
1102 }
1103
1104 return -ENOENT; /* unknown, don't bother */
1105 }
1106
1107 EXPORT_SYMBOL(s3c2410_dma_ctrl);
1108
1109 /* DMA configuration for each channel
1110 *
1111 * DISRCC -> source of the DMA (AHB,APB)
1112 * DISRC -> source address of the DMA
1113 * DIDSTC -> destination of the DMA (AHB,APD)
1114 * DIDST -> destination address of the DMA
1115 */
1116
1117 /* s3c2410_dma_config
1118 *
1119 * xfersize: size of unit in bytes (1,2,4)
1120 * dcon: base value of the DCONx register
1121 */
1122
1123 int s3c2410_dma_config(dmach_t channel,
1124 int xferunit,
1125 int dcon)
1126 {
1127 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1128
1129 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1130 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1131 __FUNCTION__, channel, xferunit, dcon);
1132 =======
1133 __func__, channel, xferunit, dcon);
1134 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1135
1136 if (chan == NULL)
1137 return -EINVAL;
1138
1139 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1140 pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
1141 =======
1142 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1143 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1144
1145 dcon |= chan->dcon & dma_sel.dcon_mask;
1146
1147 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1148 pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
1149 =======
1150 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1151 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1152
1153 switch (xferunit) {
1154 case 1:
1155 dcon |= S3C2410_DCON_BYTE;
1156 break;
1157
1158 case 2:
1159 dcon |= S3C2410_DCON_HALFWORD;
1160 break;
1161
1162 case 4:
1163 dcon |= S3C2410_DCON_WORD;
1164 break;
1165
1166 default:
1167 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1168 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
1169 =======
1170 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1171 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1172 return -EINVAL;
1173 }
1174
1175 dcon |= S3C2410_DCON_HWTRIG;
1176 dcon |= S3C2410_DCON_INTREQ;
1177
1178 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1179 pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
1180 =======
1181 pr_debug("%s: dcon now %08x\n", __func__, dcon);
1182 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1183
1184 chan->dcon = dcon;
1185 chan->xfer_unit = xferunit;
1186
1187 return 0;
1188 }
1189
1190 EXPORT_SYMBOL(s3c2410_dma_config);
1191
1192 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1193 {
1194 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1195
1196 if (chan == NULL)
1197 return -EINVAL;
1198
1199 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1200 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
1201 =======
1202 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1203 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1204
1205 chan->flags = flags;
1206
1207 return 0;
1208 }
1209
1210 EXPORT_SYMBOL(s3c2410_dma_setflags);
1211
1212
1213 /* do we need to protect the settings of the fields from
1214 * irq?
1215 */
1216
1217 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1218 {
1219 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1220
1221 if (chan == NULL)
1222 return -EINVAL;
1223
1224 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1225 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
1226 =======
1227 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1228 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1229
1230 chan->op_fn = rtn;
1231
1232 return 0;
1233 }
1234
1235 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1236
1237 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1238 {
1239 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1240
1241 if (chan == NULL)
1242 return -EINVAL;
1243
1244 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1245 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1246 =======
1247 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1248 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1249
1250 chan->callback_fn = rtn;
1251
1252 return 0;
1253 }
1254
1255 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1256
1257 /* s3c2410_dma_devconfig
1258 *
1259 * configure the dma source/destination hardware type and address
1260 *
1261 * source: S3C2410_DMASRC_HW: source is hardware
1262 * S3C2410_DMASRC_MEM: source is memory
1263 *
1264 * hwcfg: the value for xxxSTCn register,
1265 * bit 0: 0=increment pointer, 1=leave pointer
1266 * bit 1: 0=source is AHB, 1=source is APB
1267 *
1268 * devaddr: physical address of the source
1269 */
1270
1271 int s3c2410_dma_devconfig(int channel,
1272 enum s3c2410_dmasrc source,
1273 int hwcfg,
1274 unsigned long devaddr)
1275 {
1276 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1277
1278 if (chan == NULL)
1279 return -EINVAL;
1280
1281 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1282 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1283 __FUNCTION__, (int)source, hwcfg, devaddr);
1284 =======
1285 __func__, (int)source, hwcfg, devaddr);
1286 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1287
1288 chan->source = source;
1289 chan->dev_addr = devaddr;
1290 chan->hw_cfg = hwcfg;
1291
1292 switch (source) {
1293 case S3C2410_DMASRC_HW:
1294 /* source is hardware */
1295 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1296 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1297 __FUNCTION__, devaddr, hwcfg);
1298 =======
1299 __func__, devaddr, hwcfg);
1300 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1301 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1302 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1303 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1304
1305 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1306 break;
1307
1308 case S3C2410_DMASRC_MEM:
1309 /* source is memory */
1310 <<<<<<< HEAD:arch/arm/plat-s3c24xx/dma.c
1311 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1312 __FUNCTION__, devaddr, hwcfg);
1313 =======
1314 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1315 __func__, devaddr, hwcfg);
1316 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-s3c24xx/dma.c
1317 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1318 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1319 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1320
1321 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1322 break;
1323
1324 default:
1325 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1326 channel, source);
1327
1328 return -EINVAL;
1329 }
1330
1331 if (dma_sel.direction != NULL)
1332 (dma_sel.direction)(chan, chan->map, source);
1333
1334 return 0;
1335 }
1336
1337 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1338
1339 /* s3c2410_dma_getposition
1340 *
1341 * returns the current transfer points for the dma source and destination
1342 */
1343
1344 int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1345 {
1346 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1347
1348 if (chan == NULL)
1349 return -EINVAL;
1350
1351 if (src != NULL)
1352 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1353
1354 if (dst != NULL)
1355 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1356
1357 return 0;
1358 }
1359
1360 EXPORT_SYMBOL(s3c2410_dma_getposition);
1361
1362 static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
1363 {
1364 return container_of(dev, struct s3c2410_dma_chan, dev);
1365 }
1366
1367 /* system device class */
1368
1369 #ifdef CONFIG_PM
1370
1371 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1372 {
1373 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1374
1375 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1376
1377 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1378 /* the dma channel is still working, which is probably
1379 * a bad thing to do over suspend/resume. We stop the
1380 * channel and assume that the client is either going to
1381 * retry after resume, or that it is broken.
1382 */
1383
1384 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1385 cp->number);
1386
1387 s3c2410_dma_dostop(cp);
1388 }
1389
1390 return 0;
1391 }
1392
1393 static int s3c2410_dma_resume(struct sys_device *dev)
1394 {
1395 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1396 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1397
1398 /* restore channel's hardware configuration */
1399
1400 if (!cp->in_use)
1401 return 0;
1402
1403 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1404
1405 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
1406 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
1407
1408 /* re-select the dma source for this channel */
1409
1410 if (cp->map != NULL)
1411 dma_sel.select(cp, cp->map);
1412
1413 return 0;
1414 }
1415
1416 #else
1417 #define s3c2410_dma_suspend NULL
1418 #define s3c2410_dma_resume NULL
1419 #endif /* CONFIG_PM */
1420
1421 struct sysdev_class dma_sysclass = {
1422 .name = "s3c24xx-dma",
1423 .suspend = s3c2410_dma_suspend,
1424 .resume = s3c2410_dma_resume,
1425 };
1426
1427 /* kmem cache implementation */
1428
1429 static void s3c2410_dma_cache_ctor(struct kmem_cache *c, void *p)
1430 {
1431 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1432 }
1433
1434 /* initialisation code */
1435
1436 static int __init s3c24xx_dma_sysclass_init(void)
1437 {
1438 int ret = sysdev_class_register(&dma_sysclass);
1439
1440 if (ret != 0)
1441 printk(KERN_ERR "dma sysclass registration failed\n");
1442
1443 return ret;
1444 }
1445
1446 core_initcall(s3c24xx_dma_sysclass_init);
1447
1448 static int __init s3c24xx_dma_sysdev_register(void)
1449 {
1450 struct s3c2410_dma_chan *cp = s3c2410_chans;
1451 int channel, ret;
1452
1453 for (channel = 0; channel < dma_channels; cp++, channel++) {
1454 cp->dev.cls = &dma_sysclass;
1455 cp->dev.id = channel;
1456 ret = sysdev_register(&cp->dev);
1457
1458 if (ret) {
1459 printk(KERN_ERR "error registering dev for dma %d\n",
1460 channel);
1461 return ret;
1462 }
1463 }
1464
1465 return 0;
1466 }
1467
1468 late_initcall(s3c24xx_dma_sysdev_register);
1469
1470 int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1471 unsigned int stride)
1472 {
1473 struct s3c2410_dma_chan *cp;
1474 int channel;
1475 int ret;
1476
1477 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1478
1479 dma_channels = channels;
1480
1481 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1482 if (dma_base == NULL) {
1483 printk(KERN_ERR "dma failed to remap register block\n");
1484 return -ENOMEM;
1485 }
1486
1487 dma_kmem = kmem_cache_create("dma_desc",
1488 sizeof(struct s3c2410_dma_buf), 0,
1489 SLAB_HWCACHE_ALIGN,
1490 s3c2410_dma_cache_ctor);
1491
1492 if (dma_kmem == NULL) {
1493 printk(KERN_ERR "dma failed to make kmem cache\n");
1494 ret = -ENOMEM;
1495 goto err;
1496 }
1497
1498 for (channel = 0; channel < channels; channel++) {
1499 cp = &s3c2410_chans[channel];
1500
1501 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1502
1503 /* dma channel irqs are in order.. */
1504 cp->number = channel;
1505 cp->irq = channel + irq;
1506 cp->regs = dma_base + (channel * stride);
1507
1508 /* point current stats somewhere */
1509 cp->stats = &cp->stats_store;
1510 cp->stats_store.timeout_shortest = LONG_MAX;
1511
1512 /* basic channel configuration */
1513
1514 cp->load_timeout = 1<<18;
1515
1516 printk("DMA channel %d at %p, irq %d\n",
1517 cp->number, cp->regs, cp->irq);
1518 }
1519
1520 return 0;
1521
1522 err:
1523 kmem_cache_destroy(dma_kmem);
1524 iounmap(dma_base);
1525 dma_base = NULL;
1526 return ret;
1527 }
1528
1529 int __init s3c2410_dma_init(void)
1530 {
1531 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1532 }
1533
1534 static inline int is_channel_valid(unsigned int channel)
1535 {
1536 return (channel & DMA_CH_VALID);
1537 }
1538
1539 static struct s3c24xx_dma_order *dma_order;
1540
1541
1542 /* s3c2410_dma_map_channel()
1543 *
1544 * turn the virtual channel number into a real, and un-used hardware
1545 * channel.
1546 *
1547 * first, try the dma ordering given to us by either the relevant
1548 * dma code, or the board. Then just find the first usable free
1549 * channel
1550 */
1551
1552 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1553 {
1554 struct s3c24xx_dma_order_ch *ord = NULL;
1555 struct s3c24xx_dma_map *ch_map;
1556 struct s3c2410_dma_chan *dmach;
1557 int ch;
1558
1559 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1560 return NULL;
1561
1562 ch_map = dma_sel.map + channel;
1563
1564 /* first, try the board mapping */
1565
1566 if (dma_order) {
1567 ord = &dma_order->channels[channel];
1568
1569 for (ch = 0; ch < dma_channels; ch++) {
1570 if (!is_channel_valid(ord->list[ch]))
1571 continue;
1572
1573 if (s3c2410_chans[ord->list[ch]].in_use == 0) {
1574 ch = ord->list[ch] & ~DMA_CH_VALID;
1575 goto found;
1576 }
1577 }
1578
1579 if (ord->flags & DMA_CH_NEVER)
1580 return NULL;
1581 }
1582
1583 /* second, search the channel map for first free */
1584
1585 for (ch = 0; ch < dma_channels; ch++) {
1586 if (!is_channel_valid(ch_map->channels[ch]))
1587 continue;
1588
1589 if (s3c2410_chans[ch].in_use == 0) {
1590 printk("mapped channel %d to %d\n", channel, ch);
1591 break;
1592 }
1593 }
1594
1595 if (ch >= dma_channels)
1596 return NULL;
1597
1598 /* update our channel mapping */
1599
1600 found:
1601 dmach = &s3c2410_chans[ch];
1602 dmach->map = ch_map;
1603 dma_chan_map[channel] = dmach;
1604
1605 /* select the channel */
1606
1607 (dma_sel.select)(dmach, ch_map);
1608
1609 return dmach;
1610 }
1611
1612 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1613 {
1614 return 0;
1615 }
1616
1617 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1618 {
1619 struct s3c24xx_dma_map *nmap;
1620 size_t map_sz = sizeof(*nmap) * sel->map_size;
1621 int ptr;
1622
1623 nmap = kmalloc(map_sz, GFP_KERNEL);
1624 if (nmap == NULL)
1625 return -ENOMEM;
1626
1627 memcpy(nmap, sel->map, map_sz);
1628 memcpy(&dma_sel, sel, sizeof(*sel));
1629
1630 dma_sel.map = nmap;
1631
1632 for (ptr = 0; ptr < sel->map_size; ptr++)
1633 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1634
1635 return 0;
1636 }
1637
1638 int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1639 {
1640 struct s3c24xx_dma_order *nord = dma_order;
1641
1642 if (nord == NULL)
1643 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1644
1645 if (nord == NULL) {
1646 printk(KERN_ERR "no memory to store dma channel order\n");
1647 return -ENOMEM;
1648 }
1649
1650 dma_order = nord;
1651 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1652 return 0;
1653 }
WRT350N Kernel Patches