1 /* linux/arch/arm/plat-s3c24xx/irq.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
46 * 28-Jun-2005 Ben Dooks
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to separate file
53 #include <linux/init.h>
54 #include <linux/module.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/sysdev.h>
59 #include <asm/hardware.h>
63 #include <asm/mach/irq.h>
65 #include <asm/arch/regs-irq.h>
66 #include <asm/arch/regs-gpio.h>
68 #include <asm/plat-s3c24xx/cpu.h>
69 #include <asm/plat-s3c24xx/pm.h>
70 #include <asm/plat-s3c24xx/irq.h>
72 /* wakeup irq control */
76 /* state for IRQs over sleep */
78 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 * set bit to 1 in allow bitfield to enable the wakeup settings on it
83 unsigned long s3c_irqwake_intallow
= 1L << (IRQ_RTC
- IRQ_EINT0
) | 0xfL
;
84 unsigned long s3c_irqwake_intmask
= 0xffffffffL
;
85 unsigned long s3c_irqwake_eintallow
= 0x0000fff0L
;
86 unsigned long s3c_irqwake_eintmask
= 0xffffffffL
;
89 s3c_irq_wake(unsigned int irqno
, unsigned int state
)
91 unsigned long irqbit
= 1 << (irqno
- IRQ_EINT0
);
93 if (!(s3c_irqwake_intallow
& irqbit
))
96 printk(KERN_INFO
"wake %s for irq %d\n",
97 state
? "enabled" : "disabled", irqno
);
100 s3c_irqwake_intmask
|= irqbit
;
102 s3c_irqwake_intmask
&= ~irqbit
;
108 s3c_irqext_wake(unsigned int irqno
, unsigned int state
)
110 unsigned long bit
= 1L << (irqno
- EXTINT_OFF
);
112 if (!(s3c_irqwake_eintallow
& bit
))
115 printk(KERN_INFO
"wake %s for irq %d\n",
116 state
? "enabled" : "disabled", irqno
);
119 s3c_irqwake_eintmask
|= bit
;
121 s3c_irqwake_eintmask
&= ~bit
;
127 #define s3c_irqext_wake NULL
128 #define s3c_irq_wake NULL
133 s3c_irq_mask(unsigned int irqno
)
139 mask
= __raw_readl(S3C2410_INTMSK
);
140 mask
|= 1UL << irqno
;
141 __raw_writel(mask
, S3C2410_INTMSK
);
145 s3c_irq_ack(unsigned int irqno
)
147 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
149 __raw_writel(bitval
, S3C2410_SRCPND
);
150 __raw_writel(bitval
, S3C2410_INTPND
);
154 s3c_irq_maskack(unsigned int irqno
)
156 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
159 mask
= __raw_readl(S3C2410_INTMSK
);
160 __raw_writel(mask
|bitval
, S3C2410_INTMSK
);
162 __raw_writel(bitval
, S3C2410_SRCPND
);
163 __raw_writel(bitval
, S3C2410_INTPND
);
168 s3c_irq_unmask(unsigned int irqno
)
172 if (irqno
!= IRQ_TIMER4
&& irqno
!= IRQ_EINT8t23
)
173 irqdbf2("s3c_irq_unmask %d\n", irqno
);
177 mask
= __raw_readl(S3C2410_INTMSK
);
178 mask
&= ~(1UL << irqno
);
179 __raw_writel(mask
, S3C2410_INTMSK
);
182 struct irq_chip s3c_irq_level_chip
= {
184 .ack
= s3c_irq_maskack
,
185 .mask
= s3c_irq_mask
,
186 .unmask
= s3c_irq_unmask
,
187 .set_wake
= s3c_irq_wake
190 struct irq_chip s3c_irq_chip
= {
193 .mask
= s3c_irq_mask
,
194 .unmask
= s3c_irq_unmask
,
195 .set_wake
= s3c_irq_wake
199 s3c_irqext_mask(unsigned int irqno
)
205 mask
= __raw_readl(S3C24XX_EINTMASK
);
206 mask
|= ( 1UL << irqno
);
207 __raw_writel(mask
, S3C24XX_EINTMASK
);
211 s3c_irqext_ack(unsigned int irqno
)
217 bit
= 1UL << (irqno
- EXTINT_OFF
);
219 mask
= __raw_readl(S3C24XX_EINTMASK
);
221 __raw_writel(bit
, S3C24XX_EINTPEND
);
223 req
= __raw_readl(S3C24XX_EINTPEND
);
226 /* not sure if we should be acking the parent irq... */
228 if (irqno
<= IRQ_EINT7
) {
229 if ((req
& 0xf0) == 0)
230 s3c_irq_ack(IRQ_EINT4t7
);
233 s3c_irq_ack(IRQ_EINT8t23
);
238 s3c_irqext_unmask(unsigned int irqno
)
244 mask
= __raw_readl(S3C24XX_EINTMASK
);
245 mask
&= ~( 1UL << irqno
);
246 __raw_writel(mask
, S3C24XX_EINTMASK
);
250 s3c_irqext_type(unsigned int irq
, unsigned int type
)
252 void __iomem
*extint_reg
;
253 void __iomem
*gpcon_reg
;
254 unsigned long gpcon_offset
, extint_offset
;
255 unsigned long newvalue
= 0, value
;
257 if ((irq
>= IRQ_EINT0
) && (irq
<= IRQ_EINT3
))
259 gpcon_reg
= S3C2410_GPFCON
;
260 extint_reg
= S3C24XX_EXTINT0
;
261 gpcon_offset
= (irq
- IRQ_EINT0
) * 2;
262 extint_offset
= (irq
- IRQ_EINT0
) * 4;
264 else if ((irq
>= IRQ_EINT4
) && (irq
<= IRQ_EINT7
))
266 gpcon_reg
= S3C2410_GPFCON
;
267 extint_reg
= S3C24XX_EXTINT0
;
268 gpcon_offset
= (irq
- (EXTINT_OFF
)) * 2;
269 extint_offset
= (irq
- (EXTINT_OFF
)) * 4;
271 else if ((irq
>= IRQ_EINT8
) && (irq
<= IRQ_EINT15
))
273 gpcon_reg
= S3C2410_GPGCON
;
274 extint_reg
= S3C24XX_EXTINT1
;
275 gpcon_offset
= (irq
- IRQ_EINT8
) * 2;
276 extint_offset
= (irq
- IRQ_EINT8
) * 4;
278 else if ((irq
>= IRQ_EINT16
) && (irq
<= IRQ_EINT23
))
280 gpcon_reg
= S3C2410_GPGCON
;
281 extint_reg
= S3C24XX_EXTINT2
;
282 gpcon_offset
= (irq
- IRQ_EINT8
) * 2;
283 extint_offset
= (irq
- IRQ_EINT16
) * 4;
287 /* Set the GPIO to external interrupt mode */
288 value
= __raw_readl(gpcon_reg
);
289 value
= (value
& ~(3 << gpcon_offset
)) | (0x02 << gpcon_offset
);
290 __raw_writel(value
, gpcon_reg
);
292 /* Set the external interrupt to pointed trigger type */
296 printk(KERN_WARNING
"No edge setting!\n");
300 newvalue
= S3C2410_EXTINT_RISEEDGE
;
304 newvalue
= S3C2410_EXTINT_FALLEDGE
;
308 newvalue
= S3C2410_EXTINT_BOTHEDGE
;
312 newvalue
= S3C2410_EXTINT_LOWLEV
;
316 newvalue
= S3C2410_EXTINT_HILEV
;
320 printk(KERN_ERR
"No such irq type %d", type
);
324 value
= __raw_readl(extint_reg
);
325 value
= (value
& ~(7 << extint_offset
)) | (newvalue
<< extint_offset
);
326 __raw_writel(value
, extint_reg
);
331 static struct irq_chip s3c_irqext_chip
= {
333 .mask
= s3c_irqext_mask
,
334 .unmask
= s3c_irqext_unmask
,
335 .ack
= s3c_irqext_ack
,
336 .set_type
= s3c_irqext_type
,
337 .set_wake
= s3c_irqext_wake
340 static struct irq_chip s3c_irq_eint0t4
= {
343 .mask
= s3c_irq_mask
,
344 .unmask
= s3c_irq_unmask
,
345 .set_wake
= s3c_irq_wake
,
346 .set_type
= s3c_irqext_type
,
349 /* mask values for the parent registers for each of the interrupt types */
351 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
352 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
353 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
354 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
360 s3c_irq_uart0_mask(unsigned int irqno
)
362 s3c_irqsub_mask(irqno
, INTMSK_UART0
, 7);
366 s3c_irq_uart0_unmask(unsigned int irqno
)
368 s3c_irqsub_unmask(irqno
, INTMSK_UART0
);
372 s3c_irq_uart0_ack(unsigned int irqno
)
374 s3c_irqsub_maskack(irqno
, INTMSK_UART0
, 7);
377 static struct irq_chip s3c_irq_uart0
= {
379 .mask
= s3c_irq_uart0_mask
,
380 .unmask
= s3c_irq_uart0_unmask
,
381 .ack
= s3c_irq_uart0_ack
,
387 s3c_irq_uart1_mask(unsigned int irqno
)
389 s3c_irqsub_mask(irqno
, INTMSK_UART1
, 7 << 3);
393 s3c_irq_uart1_unmask(unsigned int irqno
)
395 s3c_irqsub_unmask(irqno
, INTMSK_UART1
);
399 s3c_irq_uart1_ack(unsigned int irqno
)
401 s3c_irqsub_maskack(irqno
, INTMSK_UART1
, 7 << 3);
404 static struct irq_chip s3c_irq_uart1
= {
406 .mask
= s3c_irq_uart1_mask
,
407 .unmask
= s3c_irq_uart1_unmask
,
408 .ack
= s3c_irq_uart1_ack
,
414 s3c_irq_uart2_mask(unsigned int irqno
)
416 s3c_irqsub_mask(irqno
, INTMSK_UART2
, 7 << 6);
420 s3c_irq_uart2_unmask(unsigned int irqno
)
422 s3c_irqsub_unmask(irqno
, INTMSK_UART2
);
426 s3c_irq_uart2_ack(unsigned int irqno
)
428 s3c_irqsub_maskack(irqno
, INTMSK_UART2
, 7 << 6);
431 static struct irq_chip s3c_irq_uart2
= {
433 .mask
= s3c_irq_uart2_mask
,
434 .unmask
= s3c_irq_uart2_unmask
,
435 .ack
= s3c_irq_uart2_ack
,
438 /* ADC and Touchscreen */
441 s3c_irq_adc_mask(unsigned int irqno
)
443 s3c_irqsub_mask(irqno
, INTMSK_ADCPARENT
, 3 << 9);
447 s3c_irq_adc_unmask(unsigned int irqno
)
449 s3c_irqsub_unmask(irqno
, INTMSK_ADCPARENT
);
453 s3c_irq_adc_ack(unsigned int irqno
)
455 s3c_irqsub_ack(irqno
, INTMSK_ADCPARENT
, 3 << 9);
458 static struct irq_chip s3c_irq_adc
= {
460 .mask
= s3c_irq_adc_mask
,
461 .unmask
= s3c_irq_adc_unmask
,
462 .ack
= s3c_irq_adc_ack
,
465 /* irq demux for adc */
466 static void s3c_irq_demux_adc(unsigned int irq
,
467 struct irq_desc
*desc
)
469 unsigned int subsrc
, submsk
;
470 unsigned int offset
= 9;
471 struct irq_desc
*mydesc
;
473 /* read the current pending interrupts, and the mask
474 * for what it is available */
476 subsrc
= __raw_readl(S3C2410_SUBSRCPND
);
477 submsk
= __raw_readl(S3C2410_INTSUBMSK
);
485 mydesc
= irq_desc
+ IRQ_TC
;
486 desc_handle_irq(IRQ_TC
, mydesc
);
489 mydesc
= irq_desc
+ IRQ_ADC
;
490 desc_handle_irq(IRQ_ADC
, mydesc
);
495 static void s3c_irq_demux_uart(unsigned int start
)
497 unsigned int subsrc
, submsk
;
498 unsigned int offset
= start
- IRQ_S3CUART_RX0
;
499 struct irq_desc
*desc
;
501 /* read the current pending interrupts, and the mask
502 * for what it is available */
504 subsrc
= __raw_readl(S3C2410_SUBSRCPND
);
505 submsk
= __raw_readl(S3C2410_INTSUBMSK
);
507 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
508 start
, offset
, subsrc
, submsk
);
515 desc
= irq_desc
+ start
;
518 desc_handle_irq(start
, desc
);
523 desc_handle_irq(start
+1, desc
);
528 desc_handle_irq(start
+2, desc
);
532 /* uart demux entry points */
535 s3c_irq_demux_uart0(unsigned int irq
,
536 struct irq_desc
*desc
)
539 s3c_irq_demux_uart(IRQ_S3CUART_RX0
);
543 s3c_irq_demux_uart1(unsigned int irq
,
544 struct irq_desc
*desc
)
547 s3c_irq_demux_uart(IRQ_S3CUART_RX1
);
551 s3c_irq_demux_uart2(unsigned int irq
,
552 struct irq_desc
*desc
)
555 s3c_irq_demux_uart(IRQ_S3CUART_RX2
);
559 s3c_irq_demux_extint8(unsigned int irq
,
560 struct irq_desc
*desc
)
562 unsigned long eintpnd
= __raw_readl(S3C24XX_EINTPEND
);
563 unsigned long eintmsk
= __raw_readl(S3C24XX_EINTMASK
);
566 eintpnd
&= ~0xff; /* ignore lower irqs */
568 /* we may as well handle all the pending IRQs here */
571 irq
= __ffs(eintpnd
);
572 eintpnd
&= ~(1<<irq
);
574 irq
+= (IRQ_EINT4
- 4);
575 desc_handle_irq(irq
, irq_desc
+ irq
);
581 s3c_irq_demux_extint4t7(unsigned int irq
,
582 struct irq_desc
*desc
)
584 unsigned long eintpnd
= __raw_readl(S3C24XX_EINTPEND
);
585 unsigned long eintmsk
= __raw_readl(S3C24XX_EINTMASK
);
588 eintpnd
&= 0xff; /* only lower irqs */
590 /* we may as well handle all the pending IRQs here */
593 irq
= __ffs(eintpnd
);
594 eintpnd
&= ~(1<<irq
);
596 irq
+= (IRQ_EINT4
- 4);
598 desc_handle_irq(irq
, irq_desc
+ irq
);
604 static struct sleep_save irq_save
[] = {
605 SAVE_ITEM(S3C2410_INTMSK
),
606 SAVE_ITEM(S3C2410_INTSUBMSK
),
609 /* the extint values move between the s3c2410/s3c2440 and the s3c2412
610 * so we use an array to hold them, and to calculate the address of
611 * the register at run-time
614 static unsigned long save_extint
[3];
615 static unsigned long save_eintflt
[4];
616 static unsigned long save_eintmask
;
618 int s3c24xx_irq_suspend(struct sys_device
*dev
, pm_message_t state
)
622 for (i
= 0; i
< ARRAY_SIZE(save_extint
); i
++)
623 save_extint
[i
] = __raw_readl(S3C24XX_EXTINT0
+ (i
*4));
625 for (i
= 0; i
< ARRAY_SIZE(save_eintflt
); i
++)
626 save_eintflt
[i
] = __raw_readl(S3C24XX_EINFLT0
+ (i
*4));
628 s3c2410_pm_do_save(irq_save
, ARRAY_SIZE(irq_save
));
629 save_eintmask
= __raw_readl(S3C24XX_EINTMASK
);
634 int s3c24xx_irq_resume(struct sys_device
*dev
)
638 for (i
= 0; i
< ARRAY_SIZE(save_extint
); i
++)
639 __raw_writel(save_extint
[i
], S3C24XX_EXTINT0
+ (i
*4));
641 for (i
= 0; i
< ARRAY_SIZE(save_eintflt
); i
++)
642 __raw_writel(save_eintflt
[i
], S3C24XX_EINFLT0
+ (i
*4));
644 s3c2410_pm_do_restore(irq_save
, ARRAY_SIZE(irq_save
));
645 __raw_writel(save_eintmask
, S3C24XX_EINTMASK
);
651 #define s3c24xx_irq_suspend NULL
652 #define s3c24xx_irq_resume NULL
657 * Initialise S3C2410 IRQ system
660 void __init
s3c24xx_init_irq(void)
667 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
669 /* first, clear all interrupts pending... */
672 for (i
= 0; i
< 4; i
++) {
673 pend
= __raw_readl(S3C24XX_EINTPEND
);
675 if (pend
== 0 || pend
== last
)
678 __raw_writel(pend
, S3C24XX_EINTPEND
);
679 printk("irq: clearing pending ext status %08x\n", (int)pend
);
684 for (i
= 0; i
< 4; i
++) {
685 pend
= __raw_readl(S3C2410_INTPND
);
687 if (pend
== 0 || pend
== last
)
690 __raw_writel(pend
, S3C2410_SRCPND
);
691 __raw_writel(pend
, S3C2410_INTPND
);
692 printk("irq: clearing pending status %08x\n", (int)pend
);
697 for (i
= 0; i
< 4; i
++) {
698 pend
= __raw_readl(S3C2410_SUBSRCPND
);
700 if (pend
== 0 || pend
== last
)
703 printk("irq: clearing subpending status %08x\n", (int)pend
);
704 __raw_writel(pend
, S3C2410_SUBSRCPND
);
708 /* register the main interrupts */
710 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
712 for (irqno
= IRQ_EINT4t7
; irqno
<= IRQ_ADCPARENT
; irqno
++) {
713 /* set all the s3c2410 internal irqs */
716 /* deal with the special IRQs (cascaded) */
724 set_irq_chip(irqno
, &s3c_irq_level_chip
);
725 set_irq_handler(irqno
, handle_level_irq
);
734 //irqdbf("registering irq %d (s3c irq)\n", irqno);
735 set_irq_chip(irqno
, &s3c_irq_chip
);
736 set_irq_handler(irqno
, handle_edge_irq
);
737 set_irq_flags(irqno
, IRQF_VALID
);
741 /* setup the cascade irq handlers */
743 set_irq_chained_handler(IRQ_EINT4t7
, s3c_irq_demux_extint4t7
);
744 set_irq_chained_handler(IRQ_EINT8t23
, s3c_irq_demux_extint8
);
746 set_irq_chained_handler(IRQ_UART0
, s3c_irq_demux_uart0
);
747 set_irq_chained_handler(IRQ_UART1
, s3c_irq_demux_uart1
);
748 set_irq_chained_handler(IRQ_UART2
, s3c_irq_demux_uart2
);
749 set_irq_chained_handler(IRQ_ADCPARENT
, s3c_irq_demux_adc
);
751 /* external interrupts */
753 for (irqno
= IRQ_EINT0
; irqno
<= IRQ_EINT3
; irqno
++) {
754 irqdbf("registering irq %d (ext int)\n", irqno
);
755 set_irq_chip(irqno
, &s3c_irq_eint0t4
);
756 set_irq_handler(irqno
, handle_edge_irq
);
757 set_irq_flags(irqno
, IRQF_VALID
);
760 for (irqno
= IRQ_EINT4
; irqno
<= IRQ_EINT23
; irqno
++) {
761 irqdbf("registering irq %d (extended s3c irq)\n", irqno
);
762 set_irq_chip(irqno
, &s3c_irqext_chip
);
763 set_irq_handler(irqno
, handle_edge_irq
);
764 set_irq_flags(irqno
, IRQF_VALID
);
767 /* register the uart interrupts */
769 irqdbf("s3c2410: registering external interrupts\n");
771 for (irqno
= IRQ_S3CUART_RX0
; irqno
<= IRQ_S3CUART_ERR0
; irqno
++) {
772 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno
);
773 set_irq_chip(irqno
, &s3c_irq_uart0
);
774 set_irq_handler(irqno
, handle_level_irq
);
775 set_irq_flags(irqno
, IRQF_VALID
);
778 for (irqno
= IRQ_S3CUART_RX1
; irqno
<= IRQ_S3CUART_ERR1
; irqno
++) {
779 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno
);
780 set_irq_chip(irqno
, &s3c_irq_uart1
);
781 set_irq_handler(irqno
, handle_level_irq
);
782 set_irq_flags(irqno
, IRQF_VALID
);
785 for (irqno
= IRQ_S3CUART_RX2
; irqno
<= IRQ_S3CUART_ERR2
; irqno
++) {
786 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno
);
787 set_irq_chip(irqno
, &s3c_irq_uart2
);
788 set_irq_handler(irqno
, handle_level_irq
);
789 set_irq_flags(irqno
, IRQF_VALID
);
792 for (irqno
= IRQ_TC
; irqno
<= IRQ_ADC
; irqno
++) {
793 irqdbf("registering irq %d (s3c adc irq)\n", irqno
);
794 set_irq_chip(irqno
, &s3c_irq_adc
);
795 set_irq_handler(irqno
, handle_edge_irq
);
796 set_irq_flags(irqno
, IRQF_VALID
);
799 irqdbf("s3c2410: registered interrupt handlers\n");