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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob7678fee9a885ecc8fc0d041dfe5cb14427fc7a75
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/fb.h>
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/spi/spi.h>
14
15 #include <asm/io.h>
16 #include <asm/irq.h>
17
18 #include <asm/arch/at32ap700x.h>
19 #include <asm/arch/board.h>
20 #include <asm/arch/portmux.h>
21
22 #include <video/atmel_lcdc.h>
23
24 #include "clock.h"
25 #include "hmatrix.h"
26 #include "pio.h"
27 #include "pm.h"
28
29
30 #define PBMEM(base) \
31 { \
32 .start = base, \
33 .end = base + 0x3ff, \
34 .flags = IORESOURCE_MEM, \
35 }
36 #define IRQ(num) \
37 { \
38 .start = num, \
39 .end = num, \
40 .flags = IORESOURCE_IRQ, \
41 }
42 #define NAMED_IRQ(num, _name) \
43 { \
44 .start = num, \
45 .end = num, \
46 .name = _name, \
47 .flags = IORESOURCE_IRQ, \
48 }
49
50 /* REVISIT these assume *every* device supports DMA, but several
51 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
52 */
53 #define DEFINE_DEV(_name, _id) \
54 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
55 static struct platform_device _name##_id##_device = { \
56 .name = #_name, \
57 .id = _id, \
58 .dev = { \
59 .dma_mask = &_name##_id##_dma_mask, \
60 .coherent_dma_mask = DMA_32BIT_MASK, \
61 }, \
62 .resource = _name##_id##_resource, \
63 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
64 }
65 #define DEFINE_DEV_DATA(_name, _id) \
66 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
67 static struct platform_device _name##_id##_device = { \
68 .name = #_name, \
69 .id = _id, \
70 .dev = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .platform_data = &_name##_id##_data, \
73 .coherent_dma_mask = DMA_32BIT_MASK, \
74 }, \
75 .resource = _name##_id##_resource, \
76 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
77 }
78
79 #define select_peripheral(pin, periph, flags) \
80 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
81
82 #define DEV_CLK(_name, devname, bus, _index) \
83 static struct clk devname##_##_name = { \
84 .name = #_name, \
85 .dev = &devname##_device.dev, \
86 .parent = &bus##_clk, \
87 .mode = bus##_clk_mode, \
88 .get_rate = bus##_clk_get_rate, \
89 .index = _index, \
90 }
91
92 static DEFINE_SPINLOCK(pm_lock);
93
94 unsigned long at32ap7000_osc_rates[3] = {
95 [0] = 32768,
96 /* FIXME: these are ATSTK1002-specific */
97 [1] = 20000000,
98 [2] = 12000000,
99 };
100
101 static unsigned long osc_get_rate(struct clk *clk)
102 {
103 return at32ap7000_osc_rates[clk->index];
104 }
105
106 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
107 {
108 unsigned long div, mul, rate;
109
110 if (!(control & PM_BIT(PLLEN)))
111 return 0;
112
113 div = PM_BFEXT(PLLDIV, control) + 1;
114 mul = PM_BFEXT(PLLMUL, control) + 1;
115
116 rate = clk->parent->get_rate(clk->parent);
117 rate = (rate + div / 2) / div;
118 rate *= mul;
119
120 return rate;
121 }
122
123 static unsigned long pll0_get_rate(struct clk *clk)
124 {
125 u32 control;
126
127 control = pm_readl(PLL0);
128
129 return pll_get_rate(clk, control);
130 }
131
132 static unsigned long pll1_get_rate(struct clk *clk)
133 {
134 u32 control;
135
136 control = pm_readl(PLL1);
137
138 return pll_get_rate(clk, control);
139 }
140
141 /*
142 * The AT32AP7000 has five primary clock sources: One 32kHz
143 * oscillator, two crystal oscillators and two PLLs.
144 */
145 static struct clk osc32k = {
146 .name = "osc32k",
147 .get_rate = osc_get_rate,
148 .users = 1,
149 .index = 0,
150 };
151 static struct clk osc0 = {
152 .name = "osc0",
153 .get_rate = osc_get_rate,
154 .users = 1,
155 .index = 1,
156 };
157 static struct clk osc1 = {
158 .name = "osc1",
159 .get_rate = osc_get_rate,
160 .index = 2,
161 };
162 static struct clk pll0 = {
163 .name = "pll0",
164 .get_rate = pll0_get_rate,
165 .parent = &osc0,
166 };
167 static struct clk pll1 = {
168 .name = "pll1",
169 .get_rate = pll1_get_rate,
170 .parent = &osc0,
171 };
172
173 /*
174 * The main clock can be either osc0 or pll0. The boot loader may
175 * have chosen one for us, so we don't really know which one until we
176 * have a look at the SM.
177 */
178 static struct clk *main_clock;
179
180 /*
181 * Synchronous clocks are generated from the main clock. The clocks
182 * must satisfy the constraint
183 * fCPU >= fHSB >= fPB
184 * i.e. each clock must not be faster than its parent.
185 */
186 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
187 {
188 return main_clock->get_rate(main_clock) >> shift;
189 };
190
191 static void cpu_clk_mode(struct clk *clk, int enabled)
192 {
193 unsigned long flags;
194 u32 mask;
195
196 spin_lock_irqsave(&pm_lock, flags);
197 mask = pm_readl(CPU_MASK);
198 if (enabled)
199 mask |= 1 << clk->index;
200 else
201 mask &= ~(1 << clk->index);
202 pm_writel(CPU_MASK, mask);
203 spin_unlock_irqrestore(&pm_lock, flags);
204 }
205
206 static unsigned long cpu_clk_get_rate(struct clk *clk)
207 {
208 unsigned long cksel, shift = 0;
209
210 cksel = pm_readl(CKSEL);
211 if (cksel & PM_BIT(CPUDIV))
212 shift = PM_BFEXT(CPUSEL, cksel) + 1;
213
214 return bus_clk_get_rate(clk, shift);
215 }
216
217 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
218 {
219 u32 control;
220 unsigned long parent_rate, child_div, actual_rate, div;
221
222 parent_rate = clk->parent->get_rate(clk->parent);
223 control = pm_readl(CKSEL);
224
225 if (control & PM_BIT(HSBDIV))
226 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
227 else
228 child_div = 1;
229
230 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
231 actual_rate = parent_rate;
232 control &= ~PM_BIT(CPUDIV);
233 } else {
234 unsigned int cpusel;
235 div = (parent_rate + rate / 2) / rate;
236 if (div > child_div)
237 div = child_div;
238 cpusel = (div > 1) ? (fls(div) - 2) : 0;
239 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
240 actual_rate = parent_rate / (1 << (cpusel + 1));
241 }
242
243 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
244 clk->name, rate, actual_rate);
245
246 if (apply)
247 pm_writel(CKSEL, control);
248
249 return actual_rate;
250 }
251
252 static void hsb_clk_mode(struct clk *clk, int enabled)
253 {
254 unsigned long flags;
255 u32 mask;
256
257 spin_lock_irqsave(&pm_lock, flags);
258 mask = pm_readl(HSB_MASK);
259 if (enabled)
260 mask |= 1 << clk->index;
261 else
262 mask &= ~(1 << clk->index);
263 pm_writel(HSB_MASK, mask);
264 spin_unlock_irqrestore(&pm_lock, flags);
265 }
266
267 static unsigned long hsb_clk_get_rate(struct clk *clk)
268 {
269 unsigned long cksel, shift = 0;
270
271 cksel = pm_readl(CKSEL);
272 if (cksel & PM_BIT(HSBDIV))
273 shift = PM_BFEXT(HSBSEL, cksel) + 1;
274
275 return bus_clk_get_rate(clk, shift);
276 }
277
278 static void pba_clk_mode(struct clk *clk, int enabled)
279 {
280 unsigned long flags;
281 u32 mask;
282
283 spin_lock_irqsave(&pm_lock, flags);
284 mask = pm_readl(PBA_MASK);
285 if (enabled)
286 mask |= 1 << clk->index;
287 else
288 mask &= ~(1 << clk->index);
289 pm_writel(PBA_MASK, mask);
290 spin_unlock_irqrestore(&pm_lock, flags);
291 }
292
293 static unsigned long pba_clk_get_rate(struct clk *clk)
294 {
295 unsigned long cksel, shift = 0;
296
297 cksel = pm_readl(CKSEL);
298 if (cksel & PM_BIT(PBADIV))
299 shift = PM_BFEXT(PBASEL, cksel) + 1;
300
301 return bus_clk_get_rate(clk, shift);
302 }
303
304 static void pbb_clk_mode(struct clk *clk, int enabled)
305 {
306 unsigned long flags;
307 u32 mask;
308
309 spin_lock_irqsave(&pm_lock, flags);
310 mask = pm_readl(PBB_MASK);
311 if (enabled)
312 mask |= 1 << clk->index;
313 else
314 mask &= ~(1 << clk->index);
315 pm_writel(PBB_MASK, mask);
316 spin_unlock_irqrestore(&pm_lock, flags);
317 }
318
319 static unsigned long pbb_clk_get_rate(struct clk *clk)
320 {
321 unsigned long cksel, shift = 0;
322
323 cksel = pm_readl(CKSEL);
324 if (cksel & PM_BIT(PBBDIV))
325 shift = PM_BFEXT(PBBSEL, cksel) + 1;
326
327 return bus_clk_get_rate(clk, shift);
328 }
329
330 static struct clk cpu_clk = {
331 .name = "cpu",
332 .get_rate = cpu_clk_get_rate,
333 .set_rate = cpu_clk_set_rate,
334 .users = 1,
335 };
336 static struct clk hsb_clk = {
337 .name = "hsb",
338 .parent = &cpu_clk,
339 .get_rate = hsb_clk_get_rate,
340 };
341 static struct clk pba_clk = {
342 .name = "pba",
343 .parent = &hsb_clk,
344 .mode = hsb_clk_mode,
345 .get_rate = pba_clk_get_rate,
346 .index = 1,
347 };
348 static struct clk pbb_clk = {
349 .name = "pbb",
350 .parent = &hsb_clk,
351 .mode = hsb_clk_mode,
352 .get_rate = pbb_clk_get_rate,
353 .users = 1,
354 .index = 2,
355 };
356
357 /* --------------------------------------------------------------------
358 * Generic Clock operations
359 * -------------------------------------------------------------------- */
360
361 static void genclk_mode(struct clk *clk, int enabled)
362 {
363 u32 control;
364
365 control = pm_readl(GCCTRL(clk->index));
366 if (enabled)
367 control |= PM_BIT(CEN);
368 else
369 control &= ~PM_BIT(CEN);
370 pm_writel(GCCTRL(clk->index), control);
371 }
372
373 static unsigned long genclk_get_rate(struct clk *clk)
374 {
375 u32 control;
376 unsigned long div = 1;
377
378 control = pm_readl(GCCTRL(clk->index));
379 if (control & PM_BIT(DIVEN))
380 div = 2 * (PM_BFEXT(DIV, control) + 1);
381
382 return clk->parent->get_rate(clk->parent) / div;
383 }
384
385 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
386 {
387 u32 control;
388 unsigned long parent_rate, actual_rate, div;
389
390 parent_rate = clk->parent->get_rate(clk->parent);
391 control = pm_readl(GCCTRL(clk->index));
392
393 if (rate > 3 * parent_rate / 4) {
394 actual_rate = parent_rate;
395 control &= ~PM_BIT(DIVEN);
396 } else {
397 div = (parent_rate + rate) / (2 * rate) - 1;
398 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
399 actual_rate = parent_rate / (2 * (div + 1));
400 }
401
402 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
403 clk->name, rate, actual_rate);
404
405 if (apply)
406 pm_writel(GCCTRL(clk->index), control);
407
408 return actual_rate;
409 }
410
411 int genclk_set_parent(struct clk *clk, struct clk *parent)
412 {
413 u32 control;
414
415 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
416 clk->name, parent->name, clk->parent->name);
417
418 control = pm_readl(GCCTRL(clk->index));
419
420 if (parent == &osc1 || parent == &pll1)
421 control |= PM_BIT(OSCSEL);
422 else if (parent == &osc0 || parent == &pll0)
423 control &= ~PM_BIT(OSCSEL);
424 else
425 return -EINVAL;
426
427 if (parent == &pll0 || parent == &pll1)
428 control |= PM_BIT(PLLSEL);
429 else
430 control &= ~PM_BIT(PLLSEL);
431
432 pm_writel(GCCTRL(clk->index), control);
433 clk->parent = parent;
434
435 return 0;
436 }
437
438 static void __init genclk_init_parent(struct clk *clk)
439 {
440 u32 control;
441 struct clk *parent;
442
443 BUG_ON(clk->index > 7);
444
445 control = pm_readl(GCCTRL(clk->index));
446 if (control & PM_BIT(OSCSEL))
447 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
448 else
449 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
450
451 clk->parent = parent;
452 }
453
454 /* --------------------------------------------------------------------
455 * System peripherals
456 * -------------------------------------------------------------------- */
457 static struct resource at32_pm0_resource[] = {
458 {
459 .start = 0xfff00000,
460 .end = 0xfff0007f,
461 .flags = IORESOURCE_MEM,
462 },
463 IRQ(20),
464 };
465
466 static struct resource at32ap700x_rtc0_resource[] = {
467 {
468 .start = 0xfff00080,
469 .end = 0xfff000af,
470 .flags = IORESOURCE_MEM,
471 },
472 IRQ(21),
473 };
474
475 static struct resource at32_wdt0_resource[] = {
476 {
477 .start = 0xfff000b0,
478 .end = 0xfff000cf,
479 .flags = IORESOURCE_MEM,
480 },
481 };
482
483 static struct resource at32_eic0_resource[] = {
484 {
485 .start = 0xfff00100,
486 .end = 0xfff0013f,
487 .flags = IORESOURCE_MEM,
488 },
489 IRQ(19),
490 };
491
492 DEFINE_DEV(at32_pm, 0);
493 DEFINE_DEV(at32ap700x_rtc, 0);
494 DEFINE_DEV(at32_wdt, 0);
495 DEFINE_DEV(at32_eic, 0);
496
497 /*
498 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
499 * is always running.
500 */
501 static struct clk at32_pm_pclk = {
502 .name = "pclk",
503 .dev = &at32_pm0_device.dev,
504 .parent = &pbb_clk,
505 .mode = pbb_clk_mode,
506 .get_rate = pbb_clk_get_rate,
507 .users = 1,
508 .index = 0,
509 };
510
511 static struct resource intc0_resource[] = {
512 PBMEM(0xfff00400),
513 };
514 struct platform_device at32_intc0_device = {
515 .name = "intc",
516 .id = 0,
517 .resource = intc0_resource,
518 .num_resources = ARRAY_SIZE(intc0_resource),
519 };
520 DEV_CLK(pclk, at32_intc0, pbb, 1);
521
522 static struct clk ebi_clk = {
523 .name = "ebi",
524 .parent = &hsb_clk,
525 .mode = hsb_clk_mode,
526 .get_rate = hsb_clk_get_rate,
527 .users = 1,
528 };
529 static struct clk hramc_clk = {
530 .name = "hramc",
531 .parent = &hsb_clk,
532 .mode = hsb_clk_mode,
533 .get_rate = hsb_clk_get_rate,
534 .users = 1,
535 .index = 3,
536 };
537
538 static struct resource smc0_resource[] = {
539 PBMEM(0xfff03400),
540 };
541 DEFINE_DEV(smc, 0);
542 DEV_CLK(pclk, smc0, pbb, 13);
543 DEV_CLK(mck, smc0, hsb, 0);
544
545 static struct platform_device pdc_device = {
546 .name = "pdc",
547 .id = 0,
548 };
549 DEV_CLK(hclk, pdc, hsb, 4);
550 DEV_CLK(pclk, pdc, pba, 16);
551
552 static struct clk pico_clk = {
553 .name = "pico",
554 .parent = &cpu_clk,
555 .mode = cpu_clk_mode,
556 .get_rate = cpu_clk_get_rate,
557 .users = 1,
558 };
559
560 static struct resource dmaca0_resource[] = {
561 {
562 .start = 0xff200000,
563 .end = 0xff20ffff,
564 .flags = IORESOURCE_MEM,
565 },
566 IRQ(2),
567 };
568 DEFINE_DEV(dmaca, 0);
569 DEV_CLK(hclk, dmaca0, hsb, 10);
570
571 /* --------------------------------------------------------------------
572 * HMATRIX
573 * -------------------------------------------------------------------- */
574
575 static struct clk hmatrix_clk = {
576 .name = "hmatrix_clk",
577 .parent = &pbb_clk,
578 .mode = pbb_clk_mode,
579 .get_rate = pbb_clk_get_rate,
580 .index = 2,
581 .users = 1,
582 };
583 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
584
585 #define hmatrix_readl(reg) \
586 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
587 #define hmatrix_writel(reg,value) \
588 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
589
590 /*
591 * Set bits in the HMATRIX Special Function Register (SFR) used by the
592 * External Bus Interface (EBI). This can be used to enable special
593 * features like CompactFlash support, NAND Flash support, etc. on
594 * certain chipselects.
595 */
596 static inline void set_ebi_sfr_bits(u32 mask)
597 {
598 u32 sfr;
599
600 clk_enable(&hmatrix_clk);
601 sfr = hmatrix_readl(SFR4);
602 sfr |= mask;
603 hmatrix_writel(SFR4, sfr);
604 clk_disable(&hmatrix_clk);
605 }
606
607 /* --------------------------------------------------------------------
608 * System Timer/Counter (TC)
609 * -------------------------------------------------------------------- */
610 static struct resource at32_systc0_resource[] = {
611 PBMEM(0xfff00c00),
612 IRQ(22),
613 };
614 struct platform_device at32_systc0_device = {
615 .name = "systc",
616 .id = 0,
617 .resource = at32_systc0_resource,
618 .num_resources = ARRAY_SIZE(at32_systc0_resource),
619 };
620 DEV_CLK(pclk, at32_systc0, pbb, 3);
621
622 /* --------------------------------------------------------------------
623 * PIO
624 * -------------------------------------------------------------------- */
625
626 static struct resource pio0_resource[] = {
627 PBMEM(0xffe02800),
628 IRQ(13),
629 };
630 DEFINE_DEV(pio, 0);
631 DEV_CLK(mck, pio0, pba, 10);
632
633 static struct resource pio1_resource[] = {
634 PBMEM(0xffe02c00),
635 IRQ(14),
636 };
637 DEFINE_DEV(pio, 1);
638 DEV_CLK(mck, pio1, pba, 11);
639
640 static struct resource pio2_resource[] = {
641 PBMEM(0xffe03000),
642 IRQ(15),
643 };
644 DEFINE_DEV(pio, 2);
645 DEV_CLK(mck, pio2, pba, 12);
646
647 static struct resource pio3_resource[] = {
648 PBMEM(0xffe03400),
649 IRQ(16),
650 };
651 DEFINE_DEV(pio, 3);
652 DEV_CLK(mck, pio3, pba, 13);
653
654 static struct resource pio4_resource[] = {
655 PBMEM(0xffe03800),
656 IRQ(17),
657 };
658 DEFINE_DEV(pio, 4);
659 DEV_CLK(mck, pio4, pba, 14);
660
661 void __init at32_add_system_devices(void)
662 {
663 platform_device_register(&at32_pm0_device);
664 platform_device_register(&at32_intc0_device);
665 platform_device_register(&at32ap700x_rtc0_device);
666 platform_device_register(&at32_wdt0_device);
667 platform_device_register(&at32_eic0_device);
668 platform_device_register(&smc0_device);
669 platform_device_register(&pdc_device);
670 platform_device_register(&dmaca0_device);
671
672 platform_device_register(&at32_systc0_device);
673
674 platform_device_register(&pio0_device);
675 platform_device_register(&pio1_device);
676 platform_device_register(&pio2_device);
677 platform_device_register(&pio3_device);
678 platform_device_register(&pio4_device);
679 }
680
681 /* --------------------------------------------------------------------
682 * USART
683 * -------------------------------------------------------------------- */
684
685 static struct atmel_uart_data atmel_usart0_data = {
686 .use_dma_tx = 1,
687 .use_dma_rx = 1,
688 };
689 static struct resource atmel_usart0_resource[] = {
690 PBMEM(0xffe00c00),
691 IRQ(6),
692 };
693 DEFINE_DEV_DATA(atmel_usart, 0);
694 DEV_CLK(usart, atmel_usart0, pba, 3);
695
696 static struct atmel_uart_data atmel_usart1_data = {
697 .use_dma_tx = 1,
698 .use_dma_rx = 1,
699 };
700 static struct resource atmel_usart1_resource[] = {
701 PBMEM(0xffe01000),
702 IRQ(7),
703 };
704 DEFINE_DEV_DATA(atmel_usart, 1);
705 DEV_CLK(usart, atmel_usart1, pba, 4);
706
707 static struct atmel_uart_data atmel_usart2_data = {
708 .use_dma_tx = 1,
709 .use_dma_rx = 1,
710 };
711 static struct resource atmel_usart2_resource[] = {
712 PBMEM(0xffe01400),
713 IRQ(8),
714 };
715 DEFINE_DEV_DATA(atmel_usart, 2);
716 DEV_CLK(usart, atmel_usart2, pba, 5);
717
718 static struct atmel_uart_data atmel_usart3_data = {
719 .use_dma_tx = 1,
720 .use_dma_rx = 1,
721 };
722 static struct resource atmel_usart3_resource[] = {
723 PBMEM(0xffe01800),
724 IRQ(9),
725 };
726 DEFINE_DEV_DATA(atmel_usart, 3);
727 DEV_CLK(usart, atmel_usart3, pba, 6);
728
729 static inline void configure_usart0_pins(void)
730 {
731 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
732 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
733 }
734
735 static inline void configure_usart1_pins(void)
736 {
737 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
738 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
739 }
740
741 static inline void configure_usart2_pins(void)
742 {
743 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
744 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
745 }
746
747 static inline void configure_usart3_pins(void)
748 {
749 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
750 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
751 }
752
753 static struct platform_device *__initdata at32_usarts[4];
754
755 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
756 {
757 struct platform_device *pdev;
758
759 switch (hw_id) {
760 case 0:
761 pdev = &atmel_usart0_device;
762 configure_usart0_pins();
763 break;
764 case 1:
765 pdev = &atmel_usart1_device;
766 configure_usart1_pins();
767 break;
768 case 2:
769 pdev = &atmel_usart2_device;
770 configure_usart2_pins();
771 break;
772 case 3:
773 pdev = &atmel_usart3_device;
774 configure_usart3_pins();
775 break;
776 default:
777 return;
778 }
779
780 if (PXSEG(pdev->resource[0].start) == P4SEG) {
781 /* Addresses in the P4 segment are permanently mapped 1:1 */
782 struct atmel_uart_data *data = pdev->dev.platform_data;
783 data->regs = (void __iomem *)pdev->resource[0].start;
784 }
785
786 pdev->id = line;
787 at32_usarts[line] = pdev;
788 }
789
790 struct platform_device *__init at32_add_device_usart(unsigned int id)
791 {
792 platform_device_register(at32_usarts[id]);
793 return at32_usarts[id];
794 }
795
796 struct platform_device *atmel_default_console_device;
797
798 void __init at32_setup_serial_console(unsigned int usart_id)
799 {
800 atmel_default_console_device = at32_usarts[usart_id];
801 }
802
803 /* --------------------------------------------------------------------
804 * Ethernet
805 * -------------------------------------------------------------------- */
806
807 #ifdef CONFIG_CPU_AT32AP7000
808 static struct eth_platform_data macb0_data;
809 static struct resource macb0_resource[] = {
810 PBMEM(0xfff01800),
811 IRQ(25),
812 };
813 DEFINE_DEV_DATA(macb, 0);
814 DEV_CLK(hclk, macb0, hsb, 8);
815 DEV_CLK(pclk, macb0, pbb, 6);
816
817 static struct eth_platform_data macb1_data;
818 static struct resource macb1_resource[] = {
819 PBMEM(0xfff01c00),
820 IRQ(26),
821 };
822 DEFINE_DEV_DATA(macb, 1);
823 DEV_CLK(hclk, macb1, hsb, 9);
824 DEV_CLK(pclk, macb1, pbb, 7);
825
826 struct platform_device *__init
827 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
828 {
829 struct platform_device *pdev;
830
831 switch (id) {
832 case 0:
833 pdev = &macb0_device;
834
835 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
836 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
837 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
838 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
839 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
840 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
841 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
842 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
843 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
844 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
845
846 if (!data->is_rmii) {
847 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
848 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
849 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
850 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
851 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
852 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
853 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
854 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
855 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
856 }
857 break;
858
859 case 1:
860 pdev = &macb1_device;
861
862 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
863 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
864 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
865 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
866 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
867 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
868 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
869 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
870 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
871 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
872
873 if (!data->is_rmii) {
874 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
875 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
876 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
877 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
878 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
879 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
880 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
881 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
882 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
883 }
884 break;
885
886 default:
887 return NULL;
888 }
889
890 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
891 platform_device_register(pdev);
892
893 return pdev;
894 }
895 #endif
896
897 /* --------------------------------------------------------------------
898 * SPI
899 * -------------------------------------------------------------------- */
900 static struct resource atmel_spi0_resource[] = {
901 PBMEM(0xffe00000),
902 IRQ(3),
903 };
904 DEFINE_DEV(atmel_spi, 0);
905 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
906
907 static struct resource atmel_spi1_resource[] = {
908 PBMEM(0xffe00400),
909 IRQ(4),
910 };
911 DEFINE_DEV(atmel_spi, 1);
912 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
913
914 static void __init
915 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
916 unsigned int n, const u8 *pins)
917 {
918 unsigned int pin, mode;
919
920 for (; n; n--, b++) {
921 b->bus_num = bus_num;
922 if (b->chip_select >= 4)
923 continue;
924 pin = (unsigned)b->controller_data;
925 if (!pin) {
926 pin = pins[b->chip_select];
927 b->controller_data = (void *)pin;
928 }
929 mode = AT32_GPIOF_OUTPUT;
930 if (!(b->mode & SPI_CS_HIGH))
931 mode |= AT32_GPIOF_HIGH;
932 at32_select_gpio(pin, mode);
933 }
934 }
935
936 struct platform_device *__init
937 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
938 {
939 /*
940 * Manage the chipselects as GPIOs, normally using the same pins
941 * the SPI controller expects; but boards can use other pins.
942 */
943 static u8 __initdata spi0_pins[] =
944 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
945 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
946 static u8 __initdata spi1_pins[] =
947 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
948 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
949 struct platform_device *pdev;
950
951 switch (id) {
952 case 0:
953 pdev = &atmel_spi0_device;
954 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
955 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
956 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
957 at32_spi_setup_slaves(0, b, n, spi0_pins);
958 break;
959
960 case 1:
961 pdev = &atmel_spi1_device;
962 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
963 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
964 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
965 at32_spi_setup_slaves(1, b, n, spi1_pins);
966 break;
967
968 default:
969 return NULL;
970 }
971
972 spi_register_board_info(b, n);
973 platform_device_register(pdev);
974 return pdev;
975 }
976
977 /* --------------------------------------------------------------------
978 * TWI
979 * -------------------------------------------------------------------- */
980 static struct resource atmel_twi0_resource[] __initdata = {
981 PBMEM(0xffe00800),
982 IRQ(5),
983 };
984 static struct clk atmel_twi0_pclk = {
985 .name = "twi_pclk",
986 .parent = &pba_clk,
987 .mode = pba_clk_mode,
988 .get_rate = pba_clk_get_rate,
989 .index = 2,
990 };
991
992 struct platform_device *__init at32_add_device_twi(unsigned int id)
993 {
994 struct platform_device *pdev;
995
996 if (id != 0)
997 return NULL;
998
999 pdev = platform_device_alloc("atmel_twi", id);
1000 if (!pdev)
1001 return NULL;
1002
1003 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1004 ARRAY_SIZE(atmel_twi0_resource)))
1005 goto err_add_resources;
1006
1007 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1008 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1009
1010 atmel_twi0_pclk.dev = &pdev->dev;
1011
1012 platform_device_add(pdev);
1013 return pdev;
1014
1015 err_add_resources:
1016 platform_device_put(pdev);
1017 return NULL;
1018 }
1019
1020 /* --------------------------------------------------------------------
1021 * MMC
1022 * -------------------------------------------------------------------- */
1023 static struct resource atmel_mci0_resource[] __initdata = {
1024 PBMEM(0xfff02400),
1025 IRQ(28),
1026 };
1027 static struct clk atmel_mci0_pclk = {
1028 .name = "mci_clk",
1029 .parent = &pbb_clk,
1030 .mode = pbb_clk_mode,
1031 .get_rate = pbb_clk_get_rate,
1032 .index = 9,
1033 };
1034
1035 struct platform_device *__init at32_add_device_mci(unsigned int id)
1036 {
1037 struct platform_device *pdev;
1038
1039 if (id != 0)
1040 return NULL;
1041
1042 pdev = platform_device_alloc("atmel_mci", id);
1043 if (!pdev)
1044 return NULL;
1045
1046 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1047 ARRAY_SIZE(atmel_mci0_resource)))
1048 goto err_add_resources;
1049
1050 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1051 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1052 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1053 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1054 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1055 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1056
1057 atmel_mci0_pclk.dev = &pdev->dev;
1058
1059 platform_device_add(pdev);
1060 return pdev;
1061
1062 err_add_resources:
1063 platform_device_put(pdev);
1064 return NULL;
1065 }
1066
1067 /* --------------------------------------------------------------------
1068 * LCDC
1069 * -------------------------------------------------------------------- */
1070 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1071 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1072 static struct resource atmel_lcdfb0_resource[] = {
1073 {
1074 .start = 0xff000000,
1075 .end = 0xff000fff,
1076 .flags = IORESOURCE_MEM,
1077 },
1078 IRQ(1),
1079 {
1080 /* Placeholder for pre-allocated fb memory */
1081 .start = 0x00000000,
1082 .end = 0x00000000,
1083 .flags = 0,
1084 },
1085 };
1086 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1087 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1088 static struct clk atmel_lcdfb0_pixclk = {
1089 .name = "lcdc_clk",
1090 .dev = &atmel_lcdfb0_device.dev,
1091 .mode = genclk_mode,
1092 .get_rate = genclk_get_rate,
1093 .set_rate = genclk_set_rate,
1094 .set_parent = genclk_set_parent,
1095 .index = 7,
1096 };
1097
1098 struct platform_device *__init
1099 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1100 unsigned long fbmem_start, unsigned long fbmem_len)
1101 {
1102 struct platform_device *pdev;
1103 struct atmel_lcdfb_info *info;
1104 struct fb_monspecs *monspecs;
1105 struct fb_videomode *modedb;
1106 unsigned int modedb_size;
1107
1108 /*
1109 * Do a deep copy of the fb data, monspecs and modedb. Make
1110 * sure all allocations are done before setting up the
1111 * portmux.
1112 */
1113 monspecs = kmemdup(data->default_monspecs,
1114 sizeof(struct fb_monspecs), GFP_KERNEL);
1115 if (!monspecs)
1116 return NULL;
1117
1118 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1119 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1120 if (!modedb)
1121 goto err_dup_modedb;
1122 monspecs->modedb = modedb;
1123
1124 switch (id) {
1125 case 0:
1126 pdev = &atmel_lcdfb0_device;
1127 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1128 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1129 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1130 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1131 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1132 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1133 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1134 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1135 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1136 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1137 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1138 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1139 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1140 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1141 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1142 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1143 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1144 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1145 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1146 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1147 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1148 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1149 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1150 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1151 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1152 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1153 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1154 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1155 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1156 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1157 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1158
1159 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1160 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1161 break;
1162
1163 default:
1164 goto err_invalid_id;
1165 }
1166
1167 if (fbmem_len) {
1168 pdev->resource[2].start = fbmem_start;
1169 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1170 pdev->resource[2].flags = IORESOURCE_MEM;
1171 }
1172
1173 info = pdev->dev.platform_data;
1174 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1175 info->default_monspecs = monspecs;
1176
1177 platform_device_register(pdev);
1178 return pdev;
1179
1180 err_invalid_id:
1181 kfree(modedb);
1182 err_dup_modedb:
1183 kfree(monspecs);
1184 return NULL;
1185 }
1186 #endif
1187
1188 /* --------------------------------------------------------------------
1189 * PWM
1190 * -------------------------------------------------------------------- */
1191 static struct resource atmel_pwm0_resource[] __initdata = {
1192 PBMEM(0xfff01400),
1193 IRQ(24),
1194 };
1195 static struct clk atmel_pwm0_mck = {
1196 .name = "mck",
1197 .parent = &pbb_clk,
1198 .mode = pbb_clk_mode,
1199 .get_rate = pbb_clk_get_rate,
1200 .index = 5,
1201 };
1202
1203 struct platform_device *__init at32_add_device_pwm(u32 mask)
1204 {
1205 struct platform_device *pdev;
1206
1207 if (!mask)
1208 return NULL;
1209
1210 pdev = platform_device_alloc("atmel_pwm", 0);
1211 if (!pdev)
1212 return NULL;
1213
1214 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1215 ARRAY_SIZE(atmel_pwm0_resource)))
1216 goto out_free_pdev;
1217
1218 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1219 goto out_free_pdev;
1220
1221 if (mask & (1 << 0))
1222 select_peripheral(PA(28), PERIPH_A, 0);
1223 if (mask & (1 << 1))
1224 select_peripheral(PA(29), PERIPH_A, 0);
1225 if (mask & (1 << 2))
1226 select_peripheral(PA(21), PERIPH_B, 0);
1227 if (mask & (1 << 3))
1228 select_peripheral(PA(22), PERIPH_B, 0);
1229
1230 atmel_pwm0_mck.dev = &pdev->dev;
1231
1232 platform_device_add(pdev);
1233
1234 return pdev;
1235
1236 out_free_pdev:
1237 platform_device_put(pdev);
1238 return NULL;
1239 }
1240
1241 /* --------------------------------------------------------------------
1242 * SSC
1243 * -------------------------------------------------------------------- */
1244 static struct resource ssc0_resource[] = {
1245 PBMEM(0xffe01c00),
1246 IRQ(10),
1247 };
1248 DEFINE_DEV(ssc, 0);
1249 DEV_CLK(pclk, ssc0, pba, 7);
1250
1251 static struct resource ssc1_resource[] = {
1252 PBMEM(0xffe02000),
1253 IRQ(11),
1254 };
1255 DEFINE_DEV(ssc, 1);
1256 DEV_CLK(pclk, ssc1, pba, 8);
1257
1258 static struct resource ssc2_resource[] = {
1259 PBMEM(0xffe02400),
1260 IRQ(12),
1261 };
1262 DEFINE_DEV(ssc, 2);
1263 DEV_CLK(pclk, ssc2, pba, 9);
1264
1265 struct platform_device *__init
1266 at32_add_device_ssc(unsigned int id, unsigned int flags)
1267 {
1268 struct platform_device *pdev;
1269
1270 switch (id) {
1271 case 0:
1272 pdev = &ssc0_device;
1273 if (flags & ATMEL_SSC_RF)
1274 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1275 if (flags & ATMEL_SSC_RK)
1276 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1277 if (flags & ATMEL_SSC_TK)
1278 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1279 if (flags & ATMEL_SSC_TF)
1280 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1281 if (flags & ATMEL_SSC_TD)
1282 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1283 if (flags & ATMEL_SSC_RD)
1284 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1285 break;
1286 case 1:
1287 pdev = &ssc1_device;
1288 if (flags & ATMEL_SSC_RF)
1289 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1290 if (flags & ATMEL_SSC_RK)
1291 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1292 if (flags & ATMEL_SSC_TK)
1293 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1294 if (flags & ATMEL_SSC_TF)
1295 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1296 if (flags & ATMEL_SSC_TD)
1297 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1298 if (flags & ATMEL_SSC_RD)
1299 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1300 break;
1301 case 2:
1302 pdev = &ssc2_device;
1303 if (flags & ATMEL_SSC_TD)
1304 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1305 if (flags & ATMEL_SSC_RD)
1306 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1307 if (flags & ATMEL_SSC_TK)
1308 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1309 if (flags & ATMEL_SSC_TF)
1310 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1311 if (flags & ATMEL_SSC_RF)
1312 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1313 if (flags & ATMEL_SSC_RK)
1314 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1315 break;
1316 default:
1317 return NULL;
1318 }
1319
1320 platform_device_register(pdev);
1321 return pdev;
1322 }
1323
1324 /* --------------------------------------------------------------------
1325 * USB Device Controller
1326 * -------------------------------------------------------------------- */
1327 static struct resource usba0_resource[] __initdata = {
1328 {
1329 .start = 0xff300000,
1330 .end = 0xff3fffff,
1331 .flags = IORESOURCE_MEM,
1332 }, {
1333 .start = 0xfff03000,
1334 .end = 0xfff033ff,
1335 .flags = IORESOURCE_MEM,
1336 },
1337 IRQ(31),
1338 };
1339 static struct clk usba0_pclk = {
1340 .name = "pclk",
1341 .parent = &pbb_clk,
1342 .mode = pbb_clk_mode,
1343 .get_rate = pbb_clk_get_rate,
1344 .index = 12,
1345 };
1346 static struct clk usba0_hclk = {
1347 .name = "hclk",
1348 .parent = &hsb_clk,
1349 .mode = hsb_clk_mode,
1350 .get_rate = hsb_clk_get_rate,
1351 .index = 6,
1352 };
1353
1354 struct platform_device *__init
1355 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1356 {
1357 struct platform_device *pdev;
1358
1359 if (id != 0)
1360 return NULL;
1361
1362 pdev = platform_device_alloc("atmel_usba_udc", 0);
1363 if (!pdev)
1364 return NULL;
1365
1366 if (platform_device_add_resources(pdev, usba0_resource,
1367 ARRAY_SIZE(usba0_resource)))
1368 goto out_free_pdev;
1369
1370 if (data) {
1371 if (platform_device_add_data(pdev, data, sizeof(*data)))
1372 goto out_free_pdev;
1373
1374 if (data->vbus_pin != GPIO_PIN_NONE)
1375 at32_select_gpio(data->vbus_pin, 0);
1376 }
1377
1378 usba0_pclk.dev = &pdev->dev;
1379 usba0_hclk.dev = &pdev->dev;
1380
1381 platform_device_add(pdev);
1382
1383 return pdev;
1384
1385 out_free_pdev:
1386 platform_device_put(pdev);
1387 return NULL;
1388 }
1389
1390 /* --------------------------------------------------------------------
1391 * IDE / CompactFlash
1392 * -------------------------------------------------------------------- */
1393 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1394 static struct resource at32_smc_cs4_resource[] __initdata = {
1395 {
1396 .start = 0x04000000,
1397 .end = 0x07ffffff,
1398 .flags = IORESOURCE_MEM,
1399 },
1400 IRQ(~0UL), /* Magic IRQ will be overridden */
1401 };
1402 static struct resource at32_smc_cs5_resource[] __initdata = {
1403 {
1404 .start = 0x20000000,
1405 .end = 0x23ffffff,
1406 .flags = IORESOURCE_MEM,
1407 },
1408 IRQ(~0UL), /* Magic IRQ will be overridden */
1409 };
1410
1411 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1412 unsigned int cs, unsigned int extint)
1413 {
1414 static unsigned int extint_pin_map[4] __initdata = {
1415 GPIO_PIN_PB(25),
1416 GPIO_PIN_PB(26),
1417 GPIO_PIN_PB(27),
1418 GPIO_PIN_PB(28),
1419 };
1420 static bool common_pins_initialized __initdata = false;
1421 unsigned int extint_pin;
1422 int ret;
1423
1424 if (extint >= ARRAY_SIZE(extint_pin_map))
1425 return -EINVAL;
1426 extint_pin = extint_pin_map[extint];
1427
1428 switch (cs) {
1429 case 4:
1430 ret = platform_device_add_resources(pdev,
1431 at32_smc_cs4_resource,
1432 ARRAY_SIZE(at32_smc_cs4_resource));
1433 if (ret)
1434 return ret;
1435
1436 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1437 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1438 break;
1439 case 5:
1440 ret = platform_device_add_resources(pdev,
1441 at32_smc_cs5_resource,
1442 ARRAY_SIZE(at32_smc_cs5_resource));
1443 if (ret)
1444 return ret;
1445
1446 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1447 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1448 break;
1449 default:
1450 return -EINVAL;
1451 }
1452
1453 if (!common_pins_initialized) {
1454 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1455 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1456 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1457 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1458 common_pins_initialized = true;
1459 }
1460
1461 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1462
1463 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1464 pdev->resource[1].end = pdev->resource[1].start;
1465
1466 return 0;
1467 }
1468
1469 struct platform_device *__init
1470 at32_add_device_ide(unsigned int id, unsigned int extint,
1471 struct ide_platform_data *data)
1472 {
1473 struct platform_device *pdev;
1474
1475 pdev = platform_device_alloc("at32_ide", id);
1476 if (!pdev)
1477 goto fail;
1478
1479 if (platform_device_add_data(pdev, data,
1480 sizeof(struct ide_platform_data)))
1481 goto fail;
1482
1483 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1484 goto fail;
1485
1486 platform_device_add(pdev);
1487 return pdev;
1488
1489 fail:
1490 platform_device_put(pdev);
1491 return NULL;
1492 }
1493
1494 struct platform_device *__init
1495 at32_add_device_cf(unsigned int id, unsigned int extint,
1496 struct cf_platform_data *data)
1497 {
1498 struct platform_device *pdev;
1499
1500 pdev = platform_device_alloc("at32_cf", id);
1501 if (!pdev)
1502 goto fail;
1503
1504 if (platform_device_add_data(pdev, data,
1505 sizeof(struct cf_platform_data)))
1506 goto fail;
1507
1508 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1509 goto fail;
1510
1511 if (data->detect_pin != GPIO_PIN_NONE)
1512 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1513 if (data->reset_pin != GPIO_PIN_NONE)
1514 at32_select_gpio(data->reset_pin, 0);
1515 if (data->vcc_pin != GPIO_PIN_NONE)
1516 at32_select_gpio(data->vcc_pin, 0);
1517 /* READY is used as extint, so we can't select it as gpio */
1518
1519 platform_device_add(pdev);
1520 return pdev;
1521
1522 fail:
1523 platform_device_put(pdev);
1524 return NULL;
1525 }
1526 #endif
1527
1528 /* --------------------------------------------------------------------
1529 * AC97C
1530 * -------------------------------------------------------------------- */
1531 static struct resource atmel_ac97c0_resource[] __initdata = {
1532 PBMEM(0xfff02800),
1533 IRQ(29),
1534 };
1535 static struct clk atmel_ac97c0_pclk = {
1536 .name = "pclk",
1537 .parent = &pbb_clk,
1538 .mode = pbb_clk_mode,
1539 .get_rate = pbb_clk_get_rate,
1540 .index = 10,
1541 };
1542
1543 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1544 {
1545 struct platform_device *pdev;
1546
1547 if (id != 0)
1548 return NULL;
1549
1550 pdev = platform_device_alloc("atmel_ac97c", id);
1551 if (!pdev)
1552 return NULL;
1553
1554 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1555 ARRAY_SIZE(atmel_ac97c0_resource)))
1556 goto err_add_resources;
1557
1558 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1559 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1560 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1561 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1562
1563 atmel_ac97c0_pclk.dev = &pdev->dev;
1564
1565 platform_device_add(pdev);
1566 return pdev;
1567
1568 err_add_resources:
1569 platform_device_put(pdev);
1570 return NULL;
1571 }
1572
1573 /* --------------------------------------------------------------------
1574 * ABDAC
1575 * -------------------------------------------------------------------- */
1576 static struct resource abdac0_resource[] __initdata = {
1577 PBMEM(0xfff02000),
1578 IRQ(27),
1579 };
1580 static struct clk abdac0_pclk = {
1581 .name = "pclk",
1582 .parent = &pbb_clk,
1583 .mode = pbb_clk_mode,
1584 .get_rate = pbb_clk_get_rate,
1585 .index = 8,
1586 };
1587 static struct clk abdac0_sample_clk = {
1588 .name = "sample_clk",
1589 .mode = genclk_mode,
1590 .get_rate = genclk_get_rate,
1591 .set_rate = genclk_set_rate,
1592 .set_parent = genclk_set_parent,
1593 .index = 6,
1594 };
1595
1596 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1597 {
1598 struct platform_device *pdev;
1599
1600 if (id != 0)
1601 return NULL;
1602
1603 pdev = platform_device_alloc("abdac", id);
1604 if (!pdev)
1605 return NULL;
1606
1607 if (platform_device_add_resources(pdev, abdac0_resource,
1608 ARRAY_SIZE(abdac0_resource)))
1609 goto err_add_resources;
1610
1611 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1612 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1613 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1614 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1615
1616 abdac0_pclk.dev = &pdev->dev;
1617 abdac0_sample_clk.dev = &pdev->dev;
1618
1619 platform_device_add(pdev);
1620 return pdev;
1621
1622 err_add_resources:
1623 platform_device_put(pdev);
1624 return NULL;
1625 }
1626
1627 /* --------------------------------------------------------------------
1628 * GCLK
1629 * -------------------------------------------------------------------- */
1630 static struct clk gclk0 = {
1631 .name = "gclk0",
1632 .mode = genclk_mode,
1633 .get_rate = genclk_get_rate,
1634 .set_rate = genclk_set_rate,
1635 .set_parent = genclk_set_parent,
1636 .index = 0,
1637 };
1638 static struct clk gclk1 = {
1639 .name = "gclk1",
1640 .mode = genclk_mode,
1641 .get_rate = genclk_get_rate,
1642 .set_rate = genclk_set_rate,
1643 .set_parent = genclk_set_parent,
1644 .index = 1,
1645 };
1646 static struct clk gclk2 = {
1647 .name = "gclk2",
1648 .mode = genclk_mode,
1649 .get_rate = genclk_get_rate,
1650 .set_rate = genclk_set_rate,
1651 .set_parent = genclk_set_parent,
1652 .index = 2,
1653 };
1654 static struct clk gclk3 = {
1655 .name = "gclk3",
1656 .mode = genclk_mode,
1657 .get_rate = genclk_get_rate,
1658 .set_rate = genclk_set_rate,
1659 .set_parent = genclk_set_parent,
1660 .index = 3,
1661 };
1662 static struct clk gclk4 = {
1663 .name = "gclk4",
1664 .mode = genclk_mode,
1665 .get_rate = genclk_get_rate,
1666 .set_rate = genclk_set_rate,
1667 .set_parent = genclk_set_parent,
1668 .index = 4,
1669 };
1670
1671 struct clk *at32_clock_list[] = {
1672 &osc32k,
1673 &osc0,
1674 &osc1,
1675 &pll0,
1676 &pll1,
1677 &cpu_clk,
1678 &hsb_clk,
1679 &pba_clk,
1680 &pbb_clk,
1681 &at32_pm_pclk,
1682 &at32_intc0_pclk,
1683 &hmatrix_clk,
1684 &ebi_clk,
1685 &hramc_clk,
1686 &smc0_pclk,
1687 &smc0_mck,
1688 &pdc_hclk,
1689 &pdc_pclk,
1690 &dmaca0_hclk,
1691 &pico_clk,
1692 &pio0_mck,
1693 &pio1_mck,
1694 &pio2_mck,
1695 &pio3_mck,
1696 &pio4_mck,
1697 &at32_systc0_pclk,
1698 &atmel_usart0_usart,
1699 &atmel_usart1_usart,
1700 &atmel_usart2_usart,
1701 &atmel_usart3_usart,
1702 &atmel_pwm0_mck,
1703 #if defined(CONFIG_CPU_AT32AP7000)
1704 &macb0_hclk,
1705 &macb0_pclk,
1706 &macb1_hclk,
1707 &macb1_pclk,
1708 #endif
1709 &atmel_spi0_spi_clk,
1710 &atmel_spi1_spi_clk,
1711 &atmel_twi0_pclk,
1712 &atmel_mci0_pclk,
1713 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1714 &atmel_lcdfb0_hck1,
1715 &atmel_lcdfb0_pixclk,
1716 #endif
1717 &ssc0_pclk,
1718 &ssc1_pclk,
1719 &ssc2_pclk,
1720 &usba0_hclk,
1721 &usba0_pclk,
1722 &atmel_ac97c0_pclk,
1723 &abdac0_pclk,
1724 &abdac0_sample_clk,
1725 &gclk0,
1726 &gclk1,
1727 &gclk2,
1728 &gclk3,
1729 &gclk4,
1730 };
1731 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1732
1733 void __init at32_portmux_init(void)
1734 {
1735 at32_init_pio(&pio0_device);
1736 at32_init_pio(&pio1_device);
1737 at32_init_pio(&pio2_device);
1738 at32_init_pio(&pio3_device);
1739 at32_init_pio(&pio4_device);
1740 }
1741
1742 void __init at32_clock_init(void)
1743 {
1744 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1745 int i;
1746
1747 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1748 main_clock = &pll0;
1749 cpu_clk.parent = &pll0;
1750 } else {
1751 main_clock = &osc0;
1752 cpu_clk.parent = &osc0;
1753 }
1754
1755 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1756 pll0.parent = &osc1;
1757 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1758 pll1.parent = &osc1;
1759
1760 genclk_init_parent(&gclk0);
1761 genclk_init_parent(&gclk1);
1762 genclk_init_parent(&gclk2);
1763 genclk_init_parent(&gclk3);
1764 genclk_init_parent(&gclk4);
1765 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1766 genclk_init_parent(&atmel_lcdfb0_pixclk);
1767 #endif
1768 genclk_init_parent(&abdac0_sample_clk);
1769
1770 /*
1771 * Turn on all clocks that have at least one user already, and
1772 * turn off everything else. We only do this for module
1773 * clocks, and even though it isn't particularly pretty to
1774 * check the address of the mode function, it should do the
1775 * trick...
1776 */
1777 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1778 struct clk *clk = at32_clock_list[i];
1779
1780 if (clk->users == 0)
1781 continue;
1782
1783 if (clk->mode == &cpu_clk_mode)
1784 cpu_mask |= 1 << clk->index;
1785 else if (clk->mode == &hsb_clk_mode)
1786 hsb_mask |= 1 << clk->index;
1787 else if (clk->mode == &pba_clk_mode)
1788 pba_mask |= 1 << clk->index;
1789 else if (clk->mode == &pbb_clk_mode)
1790 pbb_mask |= 1 << clk->index;
1791 }
1792
1793 pm_writel(CPU_MASK, cpu_mask);
1794 pm_writel(HSB_MASK, hsb_mask);
1795 pm_writel(PBA_MASK, pba_mask);
1796 pm_writel(PBB_MASK, pbb_mask);
1797 }
WRT350N Kernel Patches