arch/blackfin/mach-common/dpmc.S

   1 /*
   2  * File:         arch/blackfin/mach-common/dpmc.S
   3  * Based on:
   4  * Author:       LG Soft India
   5  *
   6  * Created:      ?
   7  * Description:  Watchdog Timer APIs
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/linkage.h>
  31 #include <asm/blackfin.h>
  32 #include <asm/mach/irq.h>
  33
  34 <<<<<<< HEAD:arch/blackfin/mach-common/dpmc.S
  35 .text
  36
  37 ENTRY(_unmask_wdog_wakeup_evt)
  38         [--SP] = ( R7:0, P5:0 );
  39 #if defined(CONFIG_BF561)
  40         P0.H = hi(SICA_IWR1);
  41         P0.L = lo(SICA_IWR1);
  42 #elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
  43         P0.h = HI(SIC_IWR0);
  44         P0.l = LO(SIC_IWR0);
  45 #else
  46         P0.h = HI(SIC_IWR);
  47         P0.l = LO(SIC_IWR);
  48 #endif
  49         R7 = [P0];
  50 #if defined(CONFIG_BF561)
  51         BITSET(R7, 27);
  52 #else
  53         BITSET(R7,(IRQ_WATCH - IVG7));
  54 #endif
  55         [P0] = R7;
  56         SSYNC;
  57
  58         ( R7:0, P5:0 ) = [SP++];
  59         RTS;
  60
  61 .LWRITE_TO_STAT:
  62         /* When watch dog timer is enabled, a write to STAT will load the
  63          * contents of CNT to STAT
  64          */
  65         R7 = 0x0000(z);
  66 #if defined(CONFIG_BF561)
  67         P0.h = HI(WDOGA_STAT);
  68         P0.l = LO(WDOGA_STAT);
  69 #else
  70         P0.h = HI(WDOG_STAT);
  71         P0.l = LO(WDOG_STAT);
  72 #endif
  73         [P0] = R7;
  74         SSYNC;
  75         JUMP .LSKIP_WRITE_TO_STAT;
  76
  77 ENTRY(_program_wdog_timer)
  78         [--SP] = ( R7:0, P5:0 );
  79 #if defined(CONFIG_BF561)
  80         P0.h = HI(WDOGA_CNT);
  81         P0.l = LO(WDOGA_CNT);
  82 #else
  83         P0.h = HI(WDOG_CNT);
  84         P0.l = LO(WDOG_CNT);
  85 #endif
  86         [P0] = R0;
  87         SSYNC;
  88
  89 #if defined(CONFIG_BF561)
  90         P0.h = HI(WDOGA_CTL);
  91         P0.l = LO(WDOGA_CTL);
  92 #else
  93         P0.h = HI(WDOG_CTL);
  94         P0.l = LO(WDOG_CTL);
  95 #endif
  96         R7 = W[P0](Z);
  97         CC = BITTST(R7,1);
  98         if !CC JUMP .LWRITE_TO_STAT;
  99         CC = BITTST(R7,2);
 100         if !CC JUMP .LWRITE_TO_STAT;
 101
 102 .LSKIP_WRITE_TO_STAT:
 103 #if defined(CONFIG_BF561)
 104         P0.h = HI(WDOGA_CTL);
 105         P0.l = LO(WDOGA_CTL);
 106 #else
 107         P0.h = HI(WDOG_CTL);
 108         P0.l = LO(WDOG_CTL);
 109 #endif
 110         R7 = W[P0](Z);
 111         BITCLR(R7,1);   /* Enable GP event */
 112         BITSET(R7,2);
 113         W[P0] = R7.L;
 114         SSYNC;
 115         NOP;
 116
 117         R7 = W[P0](Z);
 118         BITCLR(R7,4);   /* Enable the wdog counter */
 119         W[P0] = R7.L;
 120         SSYNC;
 121
 122         ( R7:0, P5:0 ) = [SP++];
 123         RTS;
 124
 125 ENTRY(_clear_wdog_wakeup_evt)
 126         [--SP] = ( R7:0, P5:0 );
 127
 128 #if defined(CONFIG_BF561)
 129         P0.h = HI(WDOGA_CTL);
 130         P0.l = LO(WDOGA_CTL);
 131 #else
 132         P0.h = HI(WDOG_CTL);
 133         P0.l = LO(WDOG_CTL);
 134 #endif
 135         R7 = 0x0AD6(Z);
 136         W[P0] = R7.L;
 137         SSYNC;
 138
 139         R7 = W[P0](Z);
 140         BITSET(R7,15);
 141         W[P0] = R7.L;
 142         SSYNC;
 143
 144         R7 = W[P0](Z);
 145         BITSET(R7,1);
 146         BITSET(R7,2);
 147         W[P0] = R7.L;
 148         SSYNC;
 149
 150         ( R7:0, P5:0 ) = [SP++];
 151         RTS;
 152
 153 ENTRY(_disable_wdog_timer)
 154         [--SP] = ( R7:0, P5:0 );
 155 #if defined(CONFIG_BF561)
 156         P0.h = HI(WDOGA_CTL);
 157         P0.l = LO(WDOGA_CTL);
 158 #else
 159         P0.h = HI(WDOG_CTL);
 160         P0.l = LO(WDOG_CTL);
 161 #endif
 162         R7 = 0xAD6(Z);
 163         W[P0] = R7.L;
 164         SSYNC;
 165         ( R7:0, P5:0 ) = [SP++];
 166         RTS;
 167
 168 #if !defined(CONFIG_BF561)
 169 =======
 170 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/dpmc.S
 171
 172 .section .l1.text
 173
 174 ENTRY(_sleep_mode)
 175         [--SP] = ( R7:0, P5:0 );
 176         [--SP] =  RETS;
 177
 178         call _set_sic_iwr;
 179
 180         R0 = 0xFFFF (Z);
 181         call _set_rtc_istat;
 182
 183         P0.H = hi(PLL_CTL);
 184         P0.L = lo(PLL_CTL);
 185         R1 = W[P0](z);
 186         BITSET (R1, 3);
 187         W[P0] = R1.L;
 188
 189         CLI R2;
 190         SSYNC;
 191         IDLE;
 192         STI R2;
 193
 194         call _test_pll_locked;
 195
 196         R0 = IWR_ENABLE(0);
 197         R1 = IWR_DISABLE_ALL;
 198         R2 = IWR_DISABLE_ALL;
 199
 200         call _set_sic_iwr;
 201
 202         P0.H = hi(PLL_CTL);
 203         P0.L = lo(PLL_CTL);
 204         R7 = w[p0](z);
 205         BITCLR (R7, 3);
 206         BITCLR (R7, 5);
 207         w[p0] = R7.L;
 208         IDLE;
 209         call _test_pll_locked;
 210
 211         RETS = [SP++];
 212         ( R7:0, P5:0 ) = [SP++];
 213         RTS;
 214
 215 ENTRY(_hibernate_mode)
 216         [--SP] = ( R7:0, P5:0 );
 217         [--SP] =  RETS;
 218
 219         call _set_sic_iwr;
 220
 221         R0 = 0xFFFF (Z);
 222         call _set_rtc_istat;
 223
 224         P0.H = hi(VR_CTL);
 225         P0.L = lo(VR_CTL);
 226         R1 = W[P0](z);
 227         BITSET (R1, 8);
 228         BITCLR (R1, 0);
 229         BITCLR (R1, 1);
 230         W[P0] = R1.L;
 231         SSYNC;
 232
 233         CLI R2;
 234         IDLE;
 235
 236         /* Actually, adding anything may not be necessary...SDRAM contents
 237          * are lost
 238          */
 239
 240 ENTRY(_deep_sleep)
 241         [--SP] = ( R7:0, P5:0 );
 242         [--SP] =  RETS;
 243
 244         CLI R4;
 245
 246         R0 = IWR_ENABLE(0);
 247         R1 = IWR_DISABLE_ALL;
 248         R2 = IWR_DISABLE_ALL;
 249
 250         call _set_sic_iwr;
 251
 252         call _set_dram_srfs;
 253
 254         /* Clear all the interrupts,bits sticky */
 255         R0 = 0xFFFF (Z);
 256         call _set_rtc_istat
 257
 258         P0.H = hi(PLL_CTL);
 259         P0.L = lo(PLL_CTL);
 260         R0 = W[P0](z);
 261         BITSET (R0, 5);
 262         W[P0] = R0.L;
 263
 264         call _test_pll_locked;
 265
 266         SSYNC;
 267         IDLE;
 268
 269         call _unset_dram_srfs;
 270
 271         call _test_pll_locked;
 272
 273         R0 = IWR_ENABLE(0);
 274         R1 = IWR_DISABLE_ALL;
 275         R2 = IWR_DISABLE_ALL;
 276
 277         call _set_sic_iwr;
 278
 279         P0.H = hi(PLL_CTL);
 280         P0.L = lo(PLL_CTL);
 281         R0 = w[p0](z);
 282         BITCLR (R0, 3);
 283         BITCLR (R0, 5);
 284         BITCLR (R0, 8);
 285         w[p0] = R0;
 286         IDLE;
 287         call _test_pll_locked;
 288
 289         STI R4;
 290
 291         RETS = [SP++];
 292         ( R7:0, P5:0 ) = [SP++];
 293         RTS;
 294
 295 ENTRY(_sleep_deeper)
 296         [--SP] = ( R7:0, P5:0 );
 297         [--SP] =  RETS;
 298
 299         CLI R4;
 300
 301         P3 = R0;
 302         P4 = R1;
 303         P5 = R2;
 304
 305         R0 = IWR_ENABLE(0);
 306         R1 = IWR_DISABLE_ALL;
 307         R2 = IWR_DISABLE_ALL;
 308
 309         call _set_sic_iwr;
 310         call _set_dram_srfs;    /* Set SDRAM Self Refresh */
 311
 312         /* Clear all the interrupts,bits sticky */
 313         R0 = 0xFFFF (Z);
 314         call _set_rtc_istat;
 315         P0.H = hi(PLL_DIV);
 316         P0.L = lo(PLL_DIV);
 317         R6 = W[P0](z);
 318         R0.L = 0xF;
 319         W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
 320
 321         P0.H = hi(PLL_CTL);
 322         P0.L = lo(PLL_CTL);
 323         R5 = W[P0](z);
 324         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
 325         W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
 326
 327         SSYNC;
 328         IDLE;
 329
 330         call _test_pll_locked;
 331
 332         P0.H = hi(VR_CTL);
 333         P0.L = lo(VR_CTL);
 334         R7 = W[P0](z);
 335         R1 = 0x6;
 336         R1 <<= 16;
 337         R2 = 0x0404(Z);
 338         R1 = R1|R2;
 339
 340         R2 = DEPOSIT(R7, R1);
 341         W[P0] = R2;             /* Set Min Core Voltage */
 342
 343         SSYNC;
 344         IDLE;
 345
 346         call _test_pll_locked;
 347
 348         R0 = P3;
 349         R1 = P4;
 350         R3 = P5;
 351         call _set_sic_iwr;      /* Set Awake from IDLE */
 352
 353         P0.H = hi(PLL_CTL);
 354         P0.L = lo(PLL_CTL);
 355         R0 = W[P0](z);
 356         BITSET (R0, 3);
 357         W[P0] = R0.L;           /* Turn CCLK OFF */
 358         SSYNC;
 359         IDLE;
 360
 361         call _test_pll_locked;
 362
 363         R0 = IWR_ENABLE(0);
 364         R1 = IWR_DISABLE_ALL;
 365         R2 = IWR_DISABLE_ALL;
 366
 367         call _set_sic_iwr;      /* Set Awake from IDLE PLL */
 368
 369         P0.H = hi(VR_CTL);
 370         P0.L = lo(VR_CTL);
 371         W[P0]= R7;
 372
 373         SSYNC;
 374         IDLE;
 375
 376         call _test_pll_locked;
 377
 378         P0.H = hi(PLL_DIV);
 379         P0.L = lo(PLL_DIV);
 380         W[P0]= R6;              /* Restore CCLK and SCLK divider */
 381
 382         P0.H = hi(PLL_CTL);
 383         P0.L = lo(PLL_CTL);
 384         w[p0] = R5;             /* Restore VCO multiplier */
 385         IDLE;
 386         call _test_pll_locked;
 387
 388         call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
 389
 390         STI R4;
 391
 392         RETS = [SP++];
 393         ( R7:0, P5:0 ) = [SP++];
 394         RTS;
 395
 396 ENTRY(_set_dram_srfs)
 397         /*  set the dram to self refresh mode */
 398 #if defined(CONFIG_BF54x)
 399         P0.H = hi(EBIU_RSTCTL);
 400         P0.L = lo(EBIU_RSTCTL);
 401         R2 = [P0];
 402         R3.H = hi(SRREQ);
 403         R3.L = lo(SRREQ);
 404 #else
 405         P0.H = hi(EBIU_SDGCTL);
 406         P0.L = lo(EBIU_SDGCTL);
 407         R2 = [P0];
 408         R3.H = hi(SRFS);
 409         R3.L = lo(SRFS);
 410 #endif
 411         R2 = R2|R3;
 412         [P0] = R2;
 413         ssync;
 414 #if defined(CONFIG_BF54x)
 415 .LSRR_MODE:
 416         R2 = [P0];
 417         CC = BITTST(R2, 4);
 418         if !CC JUMP .LSRR_MODE;
 419 #endif
 420         RTS;
 421
 422 ENTRY(_unset_dram_srfs)
 423         /*  set the dram out of self refresh mode */
 424 #if defined(CONFIG_BF54x)
 425         P0.H = hi(EBIU_RSTCTL);
 426         P0.L = lo(EBIU_RSTCTL);
 427         R2 = [P0];
 428         R3.H = hi(SRREQ);
 429         R3.L = lo(SRREQ);
 430 #else
 431         P0.H = hi(EBIU_SDGCTL);
 432         P0.L = lo(EBIU_SDGCTL);
 433         R2 = [P0];
 434         R3.H = hi(SRFS);
 435         R3.L = lo(SRFS);
 436 #endif
 437         R3 = ~R3;
 438         R2 = R2&R3;
 439         [P0] = R2;
 440         ssync;
 441         RTS;
 442
 443 ENTRY(_set_sic_iwr)
 444 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
 445         P0.H = hi(SIC_IWR0);
 446         P0.L = lo(SIC_IWR0);
 447         P1.H = hi(SIC_IWR1);
 448         P1.L = lo(SIC_IWR1);
 449         [P1] = R1;
 450 #if defined(CONFIG_BF54x)
 451         P1.H = hi(SIC_IWR2);
 452         P1.L = lo(SIC_IWR2);
 453         [P1] = R2;
 454 #endif
 455 #else
 456         P0.H = hi(SIC_IWR);
 457         P0.L = lo(SIC_IWR);
 458 #endif
 459         [P0] = R0;
 460
 461         SSYNC;
 462         RTS;
 463
 464 ENTRY(_set_rtc_istat)
 465 <<<<<<< HEAD:arch/blackfin/mach-common/dpmc.S
 466 =======
 467 #ifndef CONFIG_BF561
 468 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/dpmc.S
 469         P0.H = hi(RTC_ISTAT);
 470         P0.L = lo(RTC_ISTAT);
 471         w[P0] = R0.L;
 472         SSYNC;
 473 <<<<<<< HEAD:arch/blackfin/mach-common/dpmc.S
 474 =======
 475 #endif
 476 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/dpmc.S
 477         RTS;
 478
 479 ENTRY(_test_pll_locked)
 480         P0.H = hi(PLL_STAT);
 481         P0.L = lo(PLL_STAT);
 482 1:
 483         R0 = W[P0] (Z);
 484         CC = BITTST(R0,5);
 485         IF !CC JUMP 1b;
 486         RTS;
 487 <<<<<<< HEAD:arch/blackfin/mach-common/dpmc.S
 488 #endif
 489 =======
 490 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/dpmc.S