arch/cris/arch-v10/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v10/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   5  *  Copyright (C) 1999-2002 Axis Communications AB
   6  *
   7  */
   8
   9 #include <linux/timex.h>
  10 #include <linux/time.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/swap.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 <<<<<<< HEAD:arch/cris/arch-v10/kernel/time.c
  17 #include <linux/vmstat.h>
  18 =======
  19 #include <linux/mm.h>
  20 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/cris/arch-v10/kernel/time.c
  21 #include <asm/arch/svinto.h>
  22 #include <asm/types.h>
  23 #include <asm/signal.h>
  24 #include <asm/io.h>
  25 #include <asm/delay.h>
  26 #include <asm/rtc.h>
  27 #include <asm/irq_regs.h>
  28
  29 /* define this if you need to use print_timestamp */
  30 /* it will make jiffies at 96 hz instead of 100 hz though */
  31 #undef USE_CASCADE_TIMERS
  32
  33 extern void update_xtime_from_cmos(void);
  34 extern int set_rtc_mmss(unsigned long nowtime);
  35 extern int setup_irq(int, struct irqaction *);
  36 extern int have_rtc;
  37
  38 unsigned long get_ns_in_jiffie(void)
  39 {
  40         unsigned char timer_count, t1;
  41         unsigned short presc_count;
  42         unsigned long ns;
  43         unsigned long flags;
  44
  45         local_irq_save(flags);
  46         timer_count = *R_TIMER0_DATA;
  47         presc_count = *R_TIM_PRESC_STATUS;
  48         /* presc_count might be wrapped */
  49         t1 = *R_TIMER0_DATA;
  50
  51         if (timer_count != t1){
  52                 /* it wrapped, read prescaler again...  */
  53                 presc_count = *R_TIM_PRESC_STATUS;
  54                 timer_count = t1;
  55         }
  56         local_irq_restore(flags);
  57         if (presc_count >= PRESCALE_VALUE/2 ){
  58                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  59         } else {
  60                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  61         }
  62
  63         ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
  64              ( (presc_count) * (1000000000/PRESCALE_FREQ));
  65         return ns;
  66 }
  67
  68 unsigned long do_slow_gettimeoffset(void)
  69 {
  70         unsigned long count, t1;
  71         unsigned long usec_count = 0;
  72         unsigned short presc_count;
  73
  74         static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
  75         static unsigned long jiffies_p = 0;
  76
  77         /*
  78          * cache volatile jiffies temporarily; we have IRQs turned off.
  79          */
  80         unsigned long jiffies_t;
  81
  82         /* The timer interrupt comes from Etrax timer 0. In order to get
  83          * better precision, we check the current value. It might have
  84          * underflowed already though.
  85          */
  86
  87 #ifndef CONFIG_SVINTO_SIM
  88         /* Not available in the xsim simulator. */
  89         count = *R_TIMER0_DATA;
  90         presc_count = *R_TIM_PRESC_STATUS;
  91         /* presc_count might be wrapped */
  92         t1 = *R_TIMER0_DATA;
  93         if (count != t1){
  94                 /* it wrapped, read prescaler again...  */
  95                 presc_count = *R_TIM_PRESC_STATUS;
  96                 count = t1;
  97         }
  98 #else
  99         count = 0;
 100         presc_count = 0;
 101 #endif
 102
 103         jiffies_t = jiffies;
 104
 105         /*
 106          * avoiding timer inconsistencies (they are rare, but they happen)...
 107          * there are one problem that must be avoided here:
 108          *  1. the timer counter underflows
 109          */
 110         if( jiffies_t == jiffies_p ) {
 111                 if( count > count_p ) {
 112                         /* Timer wrapped, use new count and prescale
 113                          * increase the time corresponding to one jiffie
 114                          */
 115                         usec_count = 1000000/HZ;
 116                 }
 117         } else
 118                 jiffies_p = jiffies_t;
 119         count_p = count;
 120         if (presc_count >= PRESCALE_VALUE/2 ){
 121                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
 122         } else {
 123                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
 124         }
 125         /* Convert timer value to usec */
 126         usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
 127                       (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
 128
 129         return usec_count;
 130 }
 131
 132 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 133  *
 134  * 3.10.4 Watchdog timer
 135
 136  * When the watchdog timer is started, it generates an NMI if the watchdog
 137  * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 138  * stopped after an additional 3.3 ms, the watchdog resets the chip.
 139  * The watchdog timer is stopped after reset. The watchdog timer is controlled
 140  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 141  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 142  * described in the table below:
 143  *
 144  *   Watchdog    Value written:
 145  *   state:      To enable:  To key:      Operation:
 146  *   --------    ----------  -------      ----------
 147  *   stopped         0         X          No effect.
 148  *   stopped         1       key_val      Start watchdog with key = key_val.
 149  *   started         0       ~key         Stop watchdog
 150  *   started         1       ~key         Restart watchdog with key = ~key.
 151  *   started         X       new_key_val  Change key to new_key_val.
 152  *
 153  * Note: '~' is the bitwise NOT operator.
 154  *
 155  */
 156
 157 /* right now, starting the watchdog is the same as resetting it */
 158 #define start_watchdog reset_watchdog
 159
 160 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 161 static int watchdog_key = 0;  /* arbitrary number */
 162 #endif
 163
 164 /* number of pages to consider "out of memory". it is normal that the memory
 165  * is used though, so put this really low.
 166  */
 167
 168 #define WATCHDOG_MIN_FREE_PAGES 8
 169
 170 void
 171 reset_watchdog(void)
 172 {
 173 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 174         /* only keep watchdog happy as long as we have memory left! */
 175         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 176                 /* reset the watchdog with the inverse of the old key */
 177                 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 178                 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 179                         IO_STATE(R_WATCHDOG, enable, start);
 180         }
 181 #endif
 182 }
 183
 184 /* stop the watchdog - we still need the correct key */
 185
 186 void
 187 stop_watchdog(void)
 188 {
 189 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 190         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 191         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 192                 IO_STATE(R_WATCHDOG, enable, stop);
 193 #endif
 194 }
 195
 196 /* last time the cmos clock got updated */
 197 static long last_rtc_update = 0;
 198
 199 /*
 200  * timer_interrupt() needs to keep up the real-time clock,
 201  * as well as call the "do_timer()" routine every clocktick
 202  */
 203
 204 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
 205
 206 extern void cris_do_profile(struct pt_regs *regs);
 207
 208 static inline irqreturn_t
 209 timer_interrupt(int irq, void *dev_id)
 210 {
 211         struct pt_regs *regs = get_irq_regs();
 212         /* acknowledge the timer irq */
 213
 214 #ifdef USE_CASCADE_TIMERS
 215         *R_TIMER_CTRL =
 216                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 217                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 218                 IO_STATE( R_TIMER_CTRL, i1, clr) |
 219                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 220                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 221                 IO_STATE( R_TIMER_CTRL, i0, clr) |
 222                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 223                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 224 #else
 225         *R_TIMER_CTRL = r_timer_ctrl_shadow |
 226                 IO_STATE(R_TIMER_CTRL, i0, clr);
 227 #endif
 228
 229         /* reset watchdog otherwise it resets us! */
 230         reset_watchdog();
 231
 232         /* Update statistics. */
 233         update_process_times(user_mode(regs));
 234
 235         /* call the real timer interrupt handler */
 236
 237         do_timer(1);
 238
 239         cris_do_profile(regs); /* Save profiling information */
 240
 241         /*
 242          * If we have an externally synchronized Linux clock, then update
 243          * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 244          * called as close as possible to 500 ms before the new second starts.
 245          *
 246          * The division here is not time critical since it will run once in
 247          * 11 minutes
 248          */
 249         if (ntp_synced() &&
 250             xtime.tv_sec > last_rtc_update + 660 &&
 251             (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 252             (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 253                 if (set_rtc_mmss(xtime.tv_sec) == 0)
 254                         last_rtc_update = xtime.tv_sec;
 255                 else
 256                         last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 257         }
 258         return IRQ_HANDLED;
 259 }
 260
 261 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 262  * it needs to be IRQF_DISABLED to make the jiffies update work properly
 263  */
 264
 265 static struct irqaction irq2  = {
 266         .handler = timer_interrupt,
 267         .flags = IRQF_SHARED | IRQF_DISABLED,
 268         .mask = CPU_MASK_NONE,
 269         .name = "timer",
 270 };
 271
 272 void __init
 273 time_init(void)
 274 {
 275         /* probe for the RTC and read it if it exists
 276          * Before the RTC can be probed the loops_per_usec variable needs
 277          * to be initialized to make usleep work. A better value for
 278          * loops_per_usec is calculated by the kernel later once the
 279          * clock has started.
 280          */
 281         loops_per_usec = 50;
 282
 283         if(RTC_INIT() < 0) {
 284                 /* no RTC, start at 1980 */
 285                 xtime.tv_sec = 0;
 286                 xtime.tv_nsec = 0;
 287                 have_rtc = 0;
 288         } else {
 289                 /* get the current time */
 290                 have_rtc = 1;
 291                 update_xtime_from_cmos();
 292         }
 293
 294         /*
 295          * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
 296          * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
 297          */
 298         set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 299
 300         /* Setup the etrax timers
 301          * Base frequency is 25000 hz, divider 250 -> 100 HZ
 302          * In normal mode, we use timer0, so timer1 is free. In cascade
 303          * mode (which we sometimes use for debugging) both timers are used.
 304          * Remember that linux/timex.h contains #defines that rely on the
 305          * timer settings below (hz and divide factor) !!!
 306          */
 307
 308 #ifdef USE_CASCADE_TIMERS
 309         *R_TIMER_CTRL =
 310                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 311                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 312                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 313                 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 314                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 315                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 316                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 317                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 318
 319         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 320                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 321                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 322                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 323                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 324                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 325                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 326                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 327                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 328 #else
 329         *R_TIMER_CTRL =
 330                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 331                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 332                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 333                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 334                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 335                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 336                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 337                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 338
 339         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 340                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 341                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 342                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 343                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 344                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 345                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 346                 IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 347                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 348
 349         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 350 #endif
 351
 352         *R_IRQ_MASK0_SET =
 353                 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
 354
 355         /* now actually register the timer irq handler that calls timer_interrupt() */
 356
 357         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 358
 359         /* enable watchdog if we should use one */
 360
 361 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 362         printk("Enabling watchdog...\n");
 363         start_watchdog();
 364
 365         /* If we use the hardware watchdog, we want to trap it as an NMI
 366            and dump registers before it resets us.  For this to happen, we
 367            must set the "m" NMI enable flag (which once set, is unset only
 368            when an NMI is taken).
 369
 370            The same goes for the external NMI, but that doesn't have any
 371            driver or infrastructure support yet.  */
 372         asm ("setf m");
 373
 374         *R_IRQ_MASK0_SET =
 375                 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 376         *R_VECT_MASK_SET =
 377                 IO_STATE(R_VECT_MASK_SET, nmi, set);
 378 #endif
 379 }