arch/ia64/hp/common/hwsw_iommu.c

   1 /*
   2  * Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
   3  *   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4  *
   5  * This is a pseudo I/O MMU which dispatches to the hardware I/O MMU
   6  * whenever possible.  We assume that the hardware I/O MMU requires
   7  * full 32-bit addressability, as is the case, e.g., for HP zx1-based
   8  * systems (there, the I/O MMU window is mapped at 3-4GB).  If a
   9  * device doesn't provide full 32-bit addressability, we fall back on
  10  * the sw I/O TLB.  This is good enough to let us support broken
  11  * hardware such as soundcards which have a DMA engine that can
  12  * address only 28 bits.
  13  */
  14
  15 #include <linux/device.h>
  16
  17 #include <asm/machvec.h>
  18
  19 /* swiotlb declarations & definitions: */
  20 extern int swiotlb_late_init_with_default_size (size_t size);
  21 extern ia64_mv_dma_alloc_coherent       swiotlb_alloc_coherent;
  22 extern ia64_mv_dma_free_coherent        swiotlb_free_coherent;
  23 extern ia64_mv_dma_map_single           swiotlb_map_single;
  24 extern ia64_mv_dma_unmap_single         swiotlb_unmap_single;
  25 extern ia64_mv_dma_map_sg               swiotlb_map_sg;
  26 extern ia64_mv_dma_unmap_sg             swiotlb_unmap_sg;
  27 extern ia64_mv_dma_supported            swiotlb_dma_supported;
  28 extern ia64_mv_dma_mapping_error        swiotlb_dma_mapping_error;
  29
  30 /* hwiommu declarations & definitions: */
  31
  32 extern ia64_mv_dma_alloc_coherent       sba_alloc_coherent;
  33 extern ia64_mv_dma_free_coherent        sba_free_coherent;
  34 extern ia64_mv_dma_map_single           sba_map_single;
  35 extern ia64_mv_dma_unmap_single         sba_unmap_single;
  36 extern ia64_mv_dma_map_sg               sba_map_sg;
  37 extern ia64_mv_dma_unmap_sg             sba_unmap_sg;
  38 extern ia64_mv_dma_supported            sba_dma_supported;
  39 extern ia64_mv_dma_mapping_error        sba_dma_mapping_error;
  40
  41 #define hwiommu_alloc_coherent          sba_alloc_coherent
  42 #define hwiommu_free_coherent           sba_free_coherent
  43 #define hwiommu_map_single              sba_map_single
  44 #define hwiommu_unmap_single            sba_unmap_single
  45 #define hwiommu_map_sg                  sba_map_sg
  46 #define hwiommu_unmap_sg                sba_unmap_sg
  47 #define hwiommu_dma_supported           sba_dma_supported
  48 #define hwiommu_dma_mapping_error       sba_dma_mapping_error
  49 #define hwiommu_sync_single_for_cpu     machvec_dma_sync_single
  50 #define hwiommu_sync_sg_for_cpu         machvec_dma_sync_sg
  51 #define hwiommu_sync_single_for_device  machvec_dma_sync_single
  52 #define hwiommu_sync_sg_for_device      machvec_dma_sync_sg
  53
  54
  55 /*
  56  * Note: we need to make the determination of whether or not to use
  57  * the sw I/O TLB based purely on the device structure.  Anything else
  58  * would be unreliable or would be too intrusive.
  59  */
  60 static inline int
  61 use_swiotlb (struct device *dev)
  62 {
  63         return dev && dev->dma_mask && !hwiommu_dma_supported(dev, *dev->dma_mask);
  64 }
  65
  66 void __init
  67 hwsw_init (void)
  68 {
  69         /* default to a smallish 2MB sw I/O TLB */
  70         if (swiotlb_late_init_with_default_size (2 * (1<<20)) != 0) {
  71 #ifdef CONFIG_IA64_GENERIC
  72                 /* Better to have normal DMA than panic */
  73                 printk(KERN_WARNING "%s: Failed to initialize software I/O TLB,"
  74 <<<<<<< HEAD:arch/ia64/hp/common/hwsw_iommu.c
  75                        " reverting to hpzx1 platform vector\n", __FUNCTION__);
  76 =======
  77                        " reverting to hpzx1 platform vector\n", __func__);
  78 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ia64/hp/common/hwsw_iommu.c
  79                 machvec_init("hpzx1");
  80 #else
  81                 panic("Unable to initialize software I/O TLB services");
  82 #endif
  83         }
  84 }
  85
  86 void *
  87 hwsw_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags)
  88 {
  89         if (use_swiotlb(dev))
  90                 return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
  91         else
  92                 return hwiommu_alloc_coherent(dev, size, dma_handle, flags);
  93 }
  94
  95 void
  96 hwsw_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
  97 {
  98         if (use_swiotlb(dev))
  99                 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
 100         else
 101                 hwiommu_free_coherent(dev, size, vaddr, dma_handle);
 102 }
 103
 104 dma_addr_t
 105 hwsw_map_single (struct device *dev, void *addr, size_t size, int dir)
 106 {
 107         if (use_swiotlb(dev))
 108                 return swiotlb_map_single(dev, addr, size, dir);
 109         else
 110                 return hwiommu_map_single(dev, addr, size, dir);
 111 }
 112
 113 void
 114 hwsw_unmap_single (struct device *dev, dma_addr_t iova, size_t size, int dir)
 115 {
 116         if (use_swiotlb(dev))
 117                 return swiotlb_unmap_single(dev, iova, size, dir);
 118         else
 119                 return hwiommu_unmap_single(dev, iova, size, dir);
 120 }
 121
 122
 123 int
 124 hwsw_map_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
 125 {
 126         if (use_swiotlb(dev))
 127                 return swiotlb_map_sg(dev, sglist, nents, dir);
 128         else
 129                 return hwiommu_map_sg(dev, sglist, nents, dir);
 130 }
 131
 132 void
 133 hwsw_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
 134 {
 135         if (use_swiotlb(dev))
 136                 return swiotlb_unmap_sg(dev, sglist, nents, dir);
 137         else
 138                 return hwiommu_unmap_sg(dev, sglist, nents, dir);
 139 }
 140
 141 void
 142 hwsw_sync_single_for_cpu (struct device *dev, dma_addr_t addr, size_t size, int dir)
 143 {
 144         if (use_swiotlb(dev))
 145                 swiotlb_sync_single_for_cpu(dev, addr, size, dir);
 146         else
 147                 hwiommu_sync_single_for_cpu(dev, addr, size, dir);
 148 }
 149
 150 void
 151 hwsw_sync_sg_for_cpu (struct device *dev, struct scatterlist *sg, int nelems, int dir)
 152 {
 153         if (use_swiotlb(dev))
 154                 swiotlb_sync_sg_for_cpu(dev, sg, nelems, dir);
 155         else
 156                 hwiommu_sync_sg_for_cpu(dev, sg, nelems, dir);
 157 }
 158
 159 void
 160 hwsw_sync_single_for_device (struct device *dev, dma_addr_t addr, size_t size, int dir)
 161 {
 162         if (use_swiotlb(dev))
 163                 swiotlb_sync_single_for_device(dev, addr, size, dir);
 164         else
 165                 hwiommu_sync_single_for_device(dev, addr, size, dir);
 166 }
 167
 168 void
 169 hwsw_sync_sg_for_device (struct device *dev, struct scatterlist *sg, int nelems, int dir)
 170 {
 171         if (use_swiotlb(dev))
 172                 swiotlb_sync_sg_for_device(dev, sg, nelems, dir);
 173         else
 174                 hwiommu_sync_sg_for_device(dev, sg, nelems, dir);
 175 }
 176
 177 int
 178 hwsw_dma_supported (struct device *dev, u64 mask)
 179 {
 180         if (hwiommu_dma_supported(dev, mask))
 181                 return 1;
 182         return swiotlb_dma_supported(dev, mask);
 183 }
 184
 185 int
 186 hwsw_dma_mapping_error (dma_addr_t dma_addr)
 187 {
 188         return hwiommu_dma_mapping_error (dma_addr) || swiotlb_dma_mapping_error(dma_addr);
 189 }
 190
 191 EXPORT_SYMBOL(hwsw_dma_mapping_error);
 192 EXPORT_SYMBOL(hwsw_map_single);
 193 EXPORT_SYMBOL(hwsw_unmap_single);
 194 EXPORT_SYMBOL(hwsw_map_sg);
 195 EXPORT_SYMBOL(hwsw_unmap_sg);
 196 EXPORT_SYMBOL(hwsw_dma_supported);
 197 EXPORT_SYMBOL(hwsw_alloc_coherent);
 198 EXPORT_SYMBOL(hwsw_free_coherent);
 199 EXPORT_SYMBOL(hwsw_sync_single_for_cpu);
 200 EXPORT_SYMBOL(hwsw_sync_single_for_device);
 201 EXPORT_SYMBOL(hwsw_sync_sg_for_cpu);
 202 EXPORT_SYMBOL(hwsw_sync_sg_for_device);