arch/ia64/sn/pci/pci_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
   7  *
   8  * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
   9  * a description of how these routines should be used.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <asm/dma.h>
  14 #include <asm/sn/intr.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17 #include <asm/sn/sn_sal.h>
  18
  19 #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
  20 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
  21
  22 /**
  23  * sn_dma_supported - test a DMA mask
  24  * @dev: device to test
  25  * @mask: DMA mask to test
  26  *
  27  * Return whether the given PCI device DMA address mask can be supported
  28  * properly.  For example, if your device can only drive the low 24-bits
  29  * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
  30  * this function.  Of course, SN only supports devices that have 32 or more
  31  * address bits when using the PMU.
  32  */
  33 int sn_dma_supported(struct device *dev, u64 mask)
  34 {
  35         BUG_ON(dev->bus != &pci_bus_type);
  36
  37         if (mask < 0x7fffffff)
  38                 return 0;
  39         return 1;
  40 }
  41 EXPORT_SYMBOL(sn_dma_supported);
  42
  43 /**
  44  * sn_dma_set_mask - set the DMA mask
  45  * @dev: device to set
  46  * @dma_mask: new mask
  47  *
  48  * Set @dev's DMA mask if the hw supports it.
  49  */
  50 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
  51 {
  52         BUG_ON(dev->bus != &pci_bus_type);
  53
  54         if (!sn_dma_supported(dev, dma_mask))
  55                 return 0;
  56
  57         *dev->dma_mask = dma_mask;
  58         return 1;
  59 }
  60 EXPORT_SYMBOL(sn_dma_set_mask);
  61
  62 /**
  63  * sn_dma_alloc_coherent - allocate memory for coherent DMA
  64  * @dev: device to allocate for
  65  * @size: size of the region
  66  * @dma_handle: DMA (bus) address
  67  * @flags: memory allocation flags
  68  *
  69  * dma_alloc_coherent() returns a pointer to a memory region suitable for
  70  * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
  71  * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
  72  *
  73  * This interface is usually used for "command" streams (e.g. the command
  74  * queue for a SCSI controller).  See Documentation/DMA-API.txt for
  75  * more information.
  76  */
  77 void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  78                             dma_addr_t * dma_handle, gfp_t flags)
  79 {
  80         void *cpuaddr;
  81         unsigned long phys_addr;
  82         int node;
  83         struct pci_dev *pdev = to_pci_dev(dev);
  84         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
  85
  86         BUG_ON(dev->bus != &pci_bus_type);
  87
  88         /*
  89          * Allocate the memory.
  90          */
  91         node = pcibus_to_node(pdev->bus);
  92         if (likely(node >=0)) {
  93                 struct page *p = alloc_pages_node(node, flags, get_order(size));
  94
  95                 if (likely(p))
  96                         cpuaddr = page_address(p);
  97                 else
  98                         return NULL;
  99         } else
 100                 cpuaddr = (void *)__get_free_pages(flags, get_order(size));
 101
 102         if (unlikely(!cpuaddr))
 103                 return NULL;
 104
 105         memset(cpuaddr, 0x0, size);
 106
 107         /* physical addr. of the memory we just got */
 108         phys_addr = __pa(cpuaddr);
 109
 110         /*
 111          * 64 bit address translations should never fail.
 112          * 32 bit translations can fail if there are insufficient mapping
 113          * resources.
 114          */
 115
 116         *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
 117                                                    SN_DMA_ADDR_PHYS);
 118         if (!*dma_handle) {
 119 <<<<<<< HEAD:arch/ia64/sn/pci/pci_dma.c
 120                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 121 =======
 122                 printk(KERN_ERR "%s: out of ATEs\n", __func__);
 123 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ia64/sn/pci/pci_dma.c
 124                 free_pages((unsigned long)cpuaddr, get_order(size));
 125                 return NULL;
 126         }
 127
 128         return cpuaddr;
 129 }
 130 EXPORT_SYMBOL(sn_dma_alloc_coherent);
 131
 132 /**
 133  * sn_pci_free_coherent - free memory associated with coherent DMAable region
 134  * @dev: device to free for
 135  * @size: size to free
 136  * @cpu_addr: kernel virtual address to free
 137  * @dma_handle: DMA address associated with this region
 138  *
 139  * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 140  * any associated IOMMU mappings.
 141  */
 142 void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
 143                           dma_addr_t dma_handle)
 144 {
 145         struct pci_dev *pdev = to_pci_dev(dev);
 146         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 147
 148         BUG_ON(dev->bus != &pci_bus_type);
 149
 150         provider->dma_unmap(pdev, dma_handle, 0);
 151         free_pages((unsigned long)cpu_addr, get_order(size));
 152 }
 153 EXPORT_SYMBOL(sn_dma_free_coherent);
 154
 155 /**
 156  * sn_dma_map_single - map a single page for DMA
 157  * @dev: device to map for
 158  * @cpu_addr: kernel virtual address of the region to map
 159  * @size: size of the region
 160  * @direction: DMA direction
 161  *
 162  * Map the region pointed to by @cpu_addr for DMA and return the
 163  * DMA address.
 164  *
 165  * We map this to the one step pcibr_dmamap_trans interface rather than
 166  * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 167  * no way of saving the dmamap handle from the alloc to later free
 168  * (which is pretty much unacceptable).
 169  *
 170  * TODO: simplify our interface;
 171  *       figure out how to save dmamap handle so can use two step.
 172  */
 173 dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
 174                              int direction)
 175 {
 176         dma_addr_t dma_addr;
 177         unsigned long phys_addr;
 178         struct pci_dev *pdev = to_pci_dev(dev);
 179         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 180
 181         BUG_ON(dev->bus != &pci_bus_type);
 182
 183         phys_addr = __pa(cpu_addr);
 184         dma_addr = provider->dma_map(pdev, phys_addr, size, SN_DMA_ADDR_PHYS);
 185         if (!dma_addr) {
 186 <<<<<<< HEAD:arch/ia64/sn/pci/pci_dma.c
 187                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 188 =======
 189                 printk(KERN_ERR "%s: out of ATEs\n", __func__);
 190 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ia64/sn/pci/pci_dma.c
 191                 return 0;
 192         }
 193         return dma_addr;
 194 }
 195 EXPORT_SYMBOL(sn_dma_map_single);
 196
 197 /**
 198  * sn_dma_unmap_single - unamp a DMA mapped page
 199  * @dev: device to sync
 200  * @dma_addr: DMA address to sync
 201  * @size: size of region
 202  * @direction: DMA direction
 203  *
 204  * This routine is supposed to sync the DMA region specified
 205  * by @dma_handle into the coherence domain.  On SN, we're always cache
 206  * coherent, so we just need to free any ATEs associated with this mapping.
 207  */
 208 void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 209                          int direction)
 210 {
 211         struct pci_dev *pdev = to_pci_dev(dev);
 212         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 213
 214         BUG_ON(dev->bus != &pci_bus_type);
 215
 216         provider->dma_unmap(pdev, dma_addr, direction);
 217 }
 218 EXPORT_SYMBOL(sn_dma_unmap_single);
 219
 220 /**
 221  * sn_dma_unmap_sg - unmap a DMA scatterlist
 222  * @dev: device to unmap
 223  * @sg: scatterlist to unmap
 224  * @nhwentries: number of scatterlist entries
 225  * @direction: DMA direction
 226  *
 227  * Unmap a set of streaming mode DMA translations.
 228  */
 229 void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
 230                      int nhwentries, int direction)
 231 {
 232         int i;
 233         struct pci_dev *pdev = to_pci_dev(dev);
 234         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 235         struct scatterlist *sg;
 236
 237         BUG_ON(dev->bus != &pci_bus_type);
 238
 239         for_each_sg(sgl, sg, nhwentries, i) {
 240                 provider->dma_unmap(pdev, sg->dma_address, direction);
 241                 sg->dma_address = (dma_addr_t) NULL;
 242                 sg->dma_length = 0;
 243         }
 244 }
 245 EXPORT_SYMBOL(sn_dma_unmap_sg);
 246
 247 /**
 248  * sn_dma_map_sg - map a scatterlist for DMA
 249  * @dev: device to map for
 250  * @sg: scatterlist to map
 251  * @nhwentries: number of entries
 252  * @direction: direction of the DMA transaction
 253  *
 254  * Maps each entry of @sg for DMA.
 255  */
 256 int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl, int nhwentries,
 257                   int direction)
 258 {
 259         unsigned long phys_addr;
 260         struct scatterlist *saved_sg = sgl, *sg;
 261         struct pci_dev *pdev = to_pci_dev(dev);
 262         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 263         int i;
 264
 265         BUG_ON(dev->bus != &pci_bus_type);
 266
 267         /*
 268          * Setup a DMA address for each entry in the scatterlist.
 269          */
 270         for_each_sg(sgl, sg, nhwentries, i) {
 271                 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
 272                 sg->dma_address = provider->dma_map(pdev,
 273                                                     phys_addr, sg->length,
 274                                                     SN_DMA_ADDR_PHYS);
 275
 276                 if (!sg->dma_address) {
 277 <<<<<<< HEAD:arch/ia64/sn/pci/pci_dma.c
 278                         printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 279 =======
 280                         printk(KERN_ERR "%s: out of ATEs\n", __func__);
 281 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ia64/sn/pci/pci_dma.c
 282
 283                         /*
 284                          * Free any successfully allocated entries.
 285                          */
 286                         if (i > 0)
 287                                 sn_dma_unmap_sg(dev, saved_sg, i, direction);
 288                         return 0;
 289                 }
 290
 291                 sg->dma_length = sg->length;
 292         }
 293
 294         return nhwentries;
 295 }
 296 EXPORT_SYMBOL(sn_dma_map_sg);
 297
 298 void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 299                                 size_t size, int direction)
 300 {
 301         BUG_ON(dev->bus != &pci_bus_type);
 302 }
 303 EXPORT_SYMBOL(sn_dma_sync_single_for_cpu);
 304
 305 void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 306                                    size_t size, int direction)
 307 {
 308         BUG_ON(dev->bus != &pci_bus_type);
 309 }
 310 EXPORT_SYMBOL(sn_dma_sync_single_for_device);
 311
 312 void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 313                             int nelems, int direction)
 314 {
 315         BUG_ON(dev->bus != &pci_bus_type);
 316 }
 317 EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu);
 318
 319 void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 320                                int nelems, int direction)
 321 {
 322         BUG_ON(dev->bus != &pci_bus_type);
 323 }
 324 EXPORT_SYMBOL(sn_dma_sync_sg_for_device);
 325
 326 int sn_dma_mapping_error(dma_addr_t dma_addr)
 327 {
 328         return 0;
 329 }
 330 EXPORT_SYMBOL(sn_dma_mapping_error);
 331
 332 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
 333 {
 334         if (!SN_PCIBUS_BUSSOFT(bus))
 335                 return ERR_PTR(-ENODEV);
 336
 337         return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
 338 }
 339
 340 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 341 {
 342         unsigned long addr;
 343         int ret;
 344         struct ia64_sal_retval isrv;
 345
 346         /*
 347          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 348          * around hw issues at the pci bus level.  SGI proms older than
 349          * 4.10 don't implement this.
 350          */
 351
 352         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 353                  pci_domain_nr(bus), bus->number,
 354                  0, /* io */
 355                  0, /* read */
 356                  port, size, __pa(val));
 357
 358         if (isrv.status == 0)
 359                 return size;
 360
 361         /*
 362          * If the above failed, retry using the SAL_PROBE call which should
 363          * be present in all proms (but which cannot work round PCI chipset
 364          * bugs).  This code is retained for compatibility with old
 365          * pre-4.10 proms, and should be removed at some point in the future.
 366          */
 367
 368         if (!SN_PCIBUS_BUSSOFT(bus))
 369                 return -ENODEV;
 370
 371         addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 372         addr += port;
 373
 374         ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
 375
 376         if (ret == 2)
 377                 return -EINVAL;
 378
 379         if (ret == 1)
 380                 *val = -1;
 381
 382         return size;
 383 }
 384
 385 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 386 {
 387         int ret = size;
 388         unsigned long paddr;
 389         unsigned long *addr;
 390         struct ia64_sal_retval isrv;
 391
 392         /*
 393          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 394          * around hw issues at the pci bus level.  SGI proms older than
 395          * 4.10 don't implement this.
 396          */
 397
 398         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 399                  pci_domain_nr(bus), bus->number,
 400                  0, /* io */
 401                  1, /* write */
 402                  port, size, __pa(&val));
 403
 404         if (isrv.status == 0)
 405                 return size;
 406
 407         /*
 408          * If the above failed, retry using the SAL_PROBE call which should
 409          * be present in all proms (but which cannot work round PCI chipset
 410          * bugs).  This code is retained for compatibility with old
 411          * pre-4.10 proms, and should be removed at some point in the future.
 412          */
 413
 414         if (!SN_PCIBUS_BUSSOFT(bus)) {
 415                 ret = -ENODEV;
 416                 goto out;
 417         }
 418
 419         /* Put the phys addr in uncached space */
 420         paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 421         paddr += port;
 422         addr = (unsigned long *)paddr;
 423
 424         switch (size) {
 425         case 1:
 426                 *(volatile u8 *)(addr) = (u8)(val);
 427                 break;
 428         case 2:
 429                 *(volatile u16 *)(addr) = (u16)(val);
 430                 break;
 431         case 4:
 432                 *(volatile u32 *)(addr) = (u32)(val);
 433                 break;
 434         default:
 435                 ret = -EINVAL;
 436                 break;
 437         }
 438  out:
 439         return ret;
 440 }